290 lines
12 KiB
VHDL
290 lines
12 KiB
VHDL
-- #################################################################################################
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-- # << NEORV32 - Generic Single-Clock FIFO Component >> #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 #
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-- # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_fifo is
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generic (
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FIFO_DEPTH : natural := 4; -- number of fifo entries; has to be a power of two; min 1
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FIFO_WIDTH : natural := 32; -- size of data elements in fifo
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FIFO_RSYNC : boolean := false; -- false = async read; true = sync read
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FIFO_SAFE : boolean := false; -- true = allow read/write only if data available
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FULL_RESET : boolean := false -- true = reset all memory cells (cannot be mapped to BRAM)
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);
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port (
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-- control --
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clk_i : in std_ulogic; -- clock, rising edge
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rstn_i : in std_ulogic; -- async reset, low-active
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clear_i : in std_ulogic; -- sync reset, high-active
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half_o : out std_ulogic; -- FIFO is at least half full
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-- write port --
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wdata_i : in std_ulogic_vector(FIFO_WIDTH-1 downto 0); -- write data
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we_i : in std_ulogic; -- write enable
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free_o : out std_ulogic; -- at least one entry is free when set
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-- read port --
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re_i : in std_ulogic; -- read enable
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rdata_o : out std_ulogic_vector(FIFO_WIDTH-1 downto 0); -- read data
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avail_o : out std_ulogic -- data available when set
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);
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end neorv32_fifo;
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architecture neorv32_fifo_rtl of neorv32_fifo is
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-- make sure FIFO depth is a power of two --
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constant fifo_depth_c : natural := cond_sel_natural_f(is_power_of_two_f(FIFO_DEPTH), FIFO_DEPTH, 2**index_size_f(FIFO_DEPTH));
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-- FIFO storage --
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type fifo_mem_t is array (0 to fifo_depth_c-1) of std_ulogic_vector(FIFO_WIDTH-1 downto 0);
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signal fifo_mem : fifo_mem_t; -- for fifo_depth_c > 1
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signal fifo_reg : std_ulogic_vector(FIFO_WIDTH-1 downto 0); -- for fifo_depth_c = 1
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-- FIFO control --
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signal we, re : std_ulogic; -- write-/read-enable
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signal w_pnt, r_pnt : std_ulogic_vector(index_size_f(fifo_depth_c) downto 0); -- write/read pointer
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signal w_nxt, r_nxt : std_ulogic_vector(index_size_f(fifo_depth_c) downto 0);
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-- read access pointer register for async. read --
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signal r_pnt_ff : std_ulogic_vector(index_size_f(fifo_depth_c) downto 0);
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-- status --
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signal match, empty, full, half, free, avail : std_ulogic;
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-- fill level --
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signal diff : std_ulogic_vector(index_size_f(fifo_depth_c) downto 0);
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begin
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-- Access Control -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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re <= re_i when (FIFO_SAFE = false) else (re_i and avail); -- SAFE = read only if data available
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we <= we_i when (FIFO_SAFE = false) else (we_i and free); -- SAFE = write only if free space left
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-- Pointers -------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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pointer_update: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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w_pnt <= (others => '0');
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r_pnt <= (others => '0');
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elsif rising_edge(clk_i) then
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w_pnt <= w_nxt;
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r_pnt <= r_nxt;
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end if;
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end process pointer_update;
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-- async pointer update --
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w_nxt <= (others => '0') when (clear_i = '1') else std_ulogic_vector(unsigned(w_pnt) + 1) when (we = '1') else w_pnt;
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r_nxt <= (others => '0') when (clear_i = '1') else std_ulogic_vector(unsigned(r_pnt) + 1) when (re = '1') else r_pnt;
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-- Status ---------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- more than 1 FIFO entries --
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check_large:
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if (fifo_depth_c > 1) generate
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match <= '1' when (r_pnt(r_pnt'left-1 downto 0) = w_pnt(w_pnt'left-1 downto 0)) else '0';
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full <= '1' when (r_pnt(r_pnt'left) /= w_pnt(w_pnt'left)) and (match = '1') else '0';
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empty <= '1' when (r_pnt(r_pnt'left) = w_pnt(w_pnt'left)) and (match = '1') else '0';
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diff <= std_ulogic_vector(unsigned(w_pnt) - unsigned(r_pnt));
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half <= diff(diff'left-1) or full;
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end generate;
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-- just 1 FIFO entry --
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check_small:
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if (fifo_depth_c = 1) generate
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match <= '1' when (r_pnt(0) = w_pnt(0)) else '0';
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full <= not match;
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empty <= match;
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half <= full;
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end generate;
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free <= not full;
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avail <= not empty;
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-- Write Access (with Reset) --------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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memory_full_reset: -- cannot be mapped to memory primitives
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if FULL_RESET generate
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-- just 1 FIFO entry --
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fifo_write_reset_small:
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if (fifo_depth_c = 1) generate
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write_reset_small: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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fifo_reg <= (others => '0');
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elsif rising_edge(clk_i) then
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if (we = '1') then
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fifo_reg <= wdata_i;
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end if;
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end if;
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end process write_reset_small;
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end generate;
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-- more than 1 FIFO entries --
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fifo_write_reset_large:
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if (fifo_depth_c > 1) generate
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write_reset_large: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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fifo_mem <= (others => (others => '0'));
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elsif rising_edge(clk_i) then
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if (we = '1') then
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fifo_mem(to_integer(unsigned(w_pnt(w_pnt'left-1 downto 0)))) <= wdata_i;
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end if;
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end if;
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end process write_reset_large;
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end generate;
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end generate;
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-- Write Access (without Reset) -----------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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memory_no_reset: -- no reset to infer memory primitives
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if not FULL_RESET generate
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-- just 1 FIFO entry --
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fifo_write_noreset_small:
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if (fifo_depth_c = 1) generate
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write_small: process(clk_i)
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begin
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if rising_edge(clk_i) then
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if (we = '1') then
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fifo_reg <= wdata_i;
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end if;
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end if;
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end process write_small;
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end generate;
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-- more than 1 FIFO entries --
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fifo_write_noreset_large:
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if (fifo_depth_c > 1) generate
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write_large: process(clk_i)
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begin
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if rising_edge(clk_i) then
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if (we = '1') then
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fifo_mem(to_integer(unsigned(w_pnt(w_pnt'left-1 downto 0)))) <= wdata_i;
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end if;
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end if;
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end process write_large;
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end generate;
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end generate;
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-- Asynchronous Read Access ---------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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fifo_read_async:
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if not FIFO_RSYNC generate
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-- just 1 FIFO entry --
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fifo_read_async_small:
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if (fifo_depth_c = 1) generate
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rdata_o <= fifo_reg;
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end generate;
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-- more than 1 FIFO entries --
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fifo_read_async_large:
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if (fifo_depth_c > 1) generate
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async_r_pnt_reg: process(clk_i)
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begin
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if rising_edge(clk_i) then
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r_pnt_ff <= r_nxt; -- individual read address register; allows mapping "async" FIFOs to memory primitives
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end if;
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end process async_r_pnt_reg;
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rdata_o <= fifo_mem(to_integer(unsigned(r_pnt_ff(r_pnt_ff'left-1 downto 0))));
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end generate;
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-- status --
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free_o <= free;
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avail_o <= avail;
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half_o <= half;
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end generate;
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-- Synchronous Read Access ----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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fifo_read_sync:
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if FIFO_RSYNC generate
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-- just 1 FIFO entry --
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fifo_read_sync_small:
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if (fifo_depth_c = 1) generate
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sync_read_small: process(clk_i)
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begin
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if rising_edge(clk_i) then
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rdata_o <= fifo_reg;
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end if;
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end process sync_read_small;
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end generate;
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-- more than 1 FIFO entries --
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fifo_read_sync_large:
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if (fifo_depth_c > 1) generate
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sync_read_large: process(clk_i)
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begin
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if rising_edge(clk_i) then
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rdata_o <= fifo_mem(to_integer(unsigned(r_pnt(r_pnt'left-1 downto 0))));
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end if;
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end process sync_read_large;
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end generate;
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-- registered status --
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sync_status: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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free_o <= '0';
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avail_o <= '0';
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half_o <= '0';
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elsif rising_edge(clk_i) then
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free_o <= free;
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avail_o <= avail;
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half_o <= half;
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end if;
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end process sync_status;
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end generate;
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end neorv32_fifo_rtl;
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