54 lines
2.6 KiB
Plaintext
54 lines
2.6 KiB
Plaintext
<<<
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:sectnums:
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==== Processor-Internal Data Cache (dCACHE)
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[cols="<3,<3,<4"]
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[frame="topbot",grid="none"]
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|=======================
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| Hardware source file(s): | neorv32_dcache.vhd |
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| Software driver file(s): | none | _implicitly used_
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| Top entity port: | none |
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| Configuration generics: | `DCACHE_EN` | implement processor-internal data cache when `true`
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| | `DCACHE_NUM_BLOCKS` | number of cache blocks (pages/lines)
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| | `DCACHE_BLOCK_SIZE` | size of a cache block in bytes
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| CPU interrupts: | none |
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|=======================
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The processor features an optional data cache to improve performance when using memories with high
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access latencies. The cache is directly connected to the CPU's data access interface and provides
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full-transparent buffering.
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The cache is implemented if the `DCACHE_EN` generic is `true`. The size of the cache memory is defined via the
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`DCACHE_BLOCK_SIZE` (the size of a single cache block/page/line in bytes; has to be a power of two and greater than or
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equal to 4 bytes) and `DCACHE_NUM_BLOCKS` (the total amount of cache blocks; has to be a power of two and greater than or
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equal to 1) generics. The data cache provides only a single set, hence it is direct-mapped.
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**Cached/Uncached Accesses**
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The data cache provides direct accesses (= uncached) to memory in order to access memory-mapped IO (like the
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processor-internal IO/peripheral modules). All accesses that target the address range from `0xF0000000` to `0xFFFFFFFF`
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will not be cached at all (see section <<_address_space>>).
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.Caching Internal Memories
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[NOTE]
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The data cache is intended to accelerate data access to **processor-external** memories
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(via the external bus interface or via the XIP module). The cache(s) should not be implemented
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when using only processor-internal data and instruction memories.
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.Manual Cache Clear/Reload
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[NOTE]
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By executing the `fence(.i)` instruction the cache is cleared and a reload from main memory is triggered.
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.Retrieve Cache Configuration from Software
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[TIP]
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Software can retrieve the cache configuration/layout from the <<_sysinfo_cache_configuration>> register.
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.Bus Access Fault Handling
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[NOTE]
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The cache always loads a complete cache block (aligned to the block size) every time a
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cache miss is detected. Each cached word from this block provides a single status bit that indicates if the
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according bus access was successful or caused a bus error. Hence, the whole cache block remains valid even
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if certain addresses inside caused a bus error. If the CPU accesses any of the faulty cache words, a
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data bus error exception is raised.
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