47 lines
2.5 KiB
Plaintext
47 lines
2.5 KiB
Plaintext
<<<
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:sectnums:
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== Packaging the Processor as IP block for Xilinx Vivado Block Designer
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[start=1]
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. Import all the core files from `rtl/core` (including default internal memory architectures from `rtl/core/mem`)
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and assign them to a _new_ design library `neorv32`.
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. Instantiate the `rtl/system_integration/neorv32_top_axi4lite.vhd` module.
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. Then either directly use that module in a new block-design ("Create Block Design", right-click -> "Add Module",
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thats easier for a first try) or package it ("Tools", "Create and Package new IP") for the use in other projects.
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. Connect your AXI-peripheral directly to the core's AXI4-Interface if you only have one, or to an AXI-Interconnect
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(from the IP-catalog) if you have multiple peripherals.
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. Connect ALL the `ACLK` and `ARESETN` pins of all peripherals and interconnects to the processor's clock and reset
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signals to have a _unified_ clock and reset domain (easier for a first setup).
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. Open the "Address Editor" tab and let Vivado assign the base-addresses for the AXI-peripherals (you can modify them
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according to your needs).
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. For all FPGA-external signals (like UART signals) make all the connections you need "external"
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(right-click on the signal/pin -> "Make External").
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. Save everything, let VIVADO create a HDL-Wrapper for the block-design and choose this as your _Top Level Design_.
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. Define your constraints and generate your bitstream.
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.Example AXI SoC using Xilinx Vivado
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image::neorv32_axi_soc.png[]
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.True Random Number Generator
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[IMPORTANT]
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The NEORV32 TRNG peripheral is enabled by default in the `neorv32_top_axi4lite` AXI wrapper. Otherwise, Vivado
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cannot insert the wrapper into a block design (see https://github.com/stnolting/neorv32/issues/227.).
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footnote:[Seems like Vivado has problem evaluating design source files that have more than two in-file sub-entities.]
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If the TRNG is not needed, you can disable it by double-clicking on the module's block and de-selecting
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"IO_TRNG_EN" after inserting the module.
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**Combinatorial Loops DRC error**
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If the TRNG is enabled it is recommended to add the following commands to the project's constraints file in order
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to prevent DRC errors during bitstream generation:
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[source,xdc]
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----
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set_property SEVERITY {warning} [get_drc_checks LUTLP-1]
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set_property IS_ENABLED FALSE [get_drc_checks LUTLP-1]
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set_property ALLOW_COMBINATORIAL_LOOPS TRUE
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----
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[NOTE]
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Guide provided by GitHub user https://github.com/AWenzel83[`AWenzel83`] (see
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https://github.com/stnolting/neorv32/discussions/52#discussioncomment-819013). ❤️
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