345 lines
17 KiB
VHDL
345 lines
17 KiB
VHDL
-- #################################################################################################
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-- # << NEORV32 - RISC-V Debug Transport Module (DTM) >> #
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-- # ********************************************************************************************* #
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-- # Provides a JTAG-compatible TAP to access the DMI register interface. #
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-- # Compatible to the RISC-V debug specification version 0.13 and 1.0. #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 #
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-- # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_debug_dtm is
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generic (
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IDCODE_VERSION : std_ulogic_vector(03 downto 0); -- version
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IDCODE_PARTID : std_ulogic_vector(15 downto 0); -- part number
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IDCODE_MANID : std_ulogic_vector(10 downto 0) -- manufacturer id
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);
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port (
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-- global control --
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clk_i : in std_ulogic; -- global clock line
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rstn_i : in std_ulogic; -- global reset line, low-active
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-- jtag connection --
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jtag_trst_i : in std_ulogic;
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jtag_tck_i : in std_ulogic;
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jtag_tdi_i : in std_ulogic;
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jtag_tdo_o : out std_ulogic;
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jtag_tms_i : in std_ulogic;
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-- debug module interface (DMI) --
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dmi_req_o : out dmi_req_t; -- request
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dmi_rsp_i : in dmi_rsp_t -- response
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);
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end neorv32_debug_dtm;
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architecture neorv32_debug_dtm_rtl of neorv32_debug_dtm is
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-- DMI Configuration (fixed!) --
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constant dmi_idle_c : std_ulogic_vector(02 downto 0) := "000"; -- no idle cycles required
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constant dmi_version_c : std_ulogic_vector(03 downto 0) := "0001"; -- debug spec. version (0.13 & 1.0)
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constant dmi_abits_c : std_ulogic_vector(05 downto 0) := "000111"; -- number of DMI address bits (7)
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-- TAP data register addresses --
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constant addr_idcode_c : std_ulogic_vector(4 downto 0) := "00001"; -- identifier
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constant addr_dtmcs_c : std_ulogic_vector(4 downto 0) := "10000"; -- DTM status and control
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constant addr_dmi_c : std_ulogic_vector(4 downto 0) := "10001"; -- debug module interface
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-- tap JTAG signal synchronizer --
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type tap_sync_t is record
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-- internal --
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trst_ff : std_ulogic_vector(2 downto 0);
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tck_ff : std_ulogic_vector(2 downto 0);
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tdi_ff : std_ulogic_vector(2 downto 0);
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tms_ff : std_ulogic_vector(2 downto 0);
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-- external --
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trst : std_ulogic;
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tck_rising : std_ulogic;
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tck_falling : std_ulogic;
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tdi : std_ulogic;
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tms : std_ulogic;
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end record;
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signal tap_sync : tap_sync_t;
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-- tap controller --
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type tap_ctrl_state_t is (LOGIC_RESET, DR_SCAN, DR_CAPTURE, DR_SHIFT, DR_EXIT1, DR_PAUSE, DR_EXIT2, DR_UPDATE,
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RUN_IDLE, IR_SCAN, IR_CAPTURE, IR_SHIFT, IR_EXIT1, IR_PAUSE, IR_EXIT2, IR_UPDATE);
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signal tap_ctrl_state : tap_ctrl_state_t;
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-- tap registers --
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type tap_reg_t is record
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ireg : std_ulogic_vector(04 downto 0);
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bypass : std_ulogic;
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idcode : std_ulogic_vector(31 downto 0);
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dtmcs, dtmcs_nxt : std_ulogic_vector(31 downto 0);
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dmi, dmi_nxt : std_ulogic_vector((7+32+2)-1 downto 0); -- 7-bit address + 32-bit data + 2-bit operation
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end record;
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signal tap_reg : tap_reg_t;
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-- update trigger --
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type dr_trigger_t is record
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sreg : std_ulogic_vector(1 downto 0);
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valid : std_ulogic;
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end record;
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signal dr_trigger : dr_trigger_t;
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-- debug module interface controller --
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type dmi_ctrl_t is record
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busy : std_ulogic;
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op : std_ulogic_vector(01 downto 0);
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dmihardreset : std_ulogic;
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dmireset : std_ulogic;
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err : std_ulogic;
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rdata : std_ulogic_vector(31 downto 0);
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wdata : std_ulogic_vector(31 downto 0);
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addr : std_ulogic_vector(06 downto 0);
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end record;
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signal dmi_ctrl : dmi_ctrl_t;
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begin
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-- JTAG Input Synchronizer ----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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tap_synchronizer: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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tap_sync.trst_ff <= (others => '0');
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tap_sync.tck_ff <= (others => '0');
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tap_sync.tdi_ff <= (others => '0');
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tap_sync.tms_ff <= (others => '0');
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elsif rising_edge(clk_i) then
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tap_sync.trst_ff <= tap_sync.trst_ff(1 downto 0) & jtag_trst_i;
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tap_sync.tck_ff <= tap_sync.tck_ff( 1 downto 0) & jtag_tck_i;
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tap_sync.tdi_ff <= tap_sync.tdi_ff( 1 downto 0) & jtag_tdi_i;
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tap_sync.tms_ff <= tap_sync.tms_ff( 1 downto 0) & jtag_tms_i;
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end if;
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end process tap_synchronizer;
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-- JTAG reset --
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tap_sync.trst <= '0' when (tap_sync.trst_ff(2 downto 1) = "00") else '1';
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-- JTAG clock edge --
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tap_sync.tck_rising <= '1' when (tap_sync.tck_ff(2 downto 1) = "01") else '0';
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tap_sync.tck_falling <= '1' when (tap_sync.tck_ff(2 downto 1) = "10") else '0';
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-- JTAG test mode select --
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tap_sync.tms <= tap_sync.tms_ff(2);
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-- JTAG serial data input --
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tap_sync.tdi <= tap_sync.tdi_ff(2);
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-- Tap Control FSM ------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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tap_control: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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tap_ctrl_state <= LOGIC_RESET;
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elsif rising_edge(clk_i) then
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if (tap_sync.trst = '0') then -- reset
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tap_ctrl_state <= LOGIC_RESET;
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elsif (tap_sync.tck_rising = '1') then -- clock pulse (evaluate TMS on the rising edge of TCK)
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case tap_ctrl_state is -- JTAG state machine
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when LOGIC_RESET => if (tap_sync.tms = '0') then tap_ctrl_state <= RUN_IDLE; else tap_ctrl_state <= LOGIC_RESET; end if;
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when RUN_IDLE => if (tap_sync.tms = '0') then tap_ctrl_state <= RUN_IDLE; else tap_ctrl_state <= DR_SCAN; end if;
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when DR_SCAN => if (tap_sync.tms = '0') then tap_ctrl_state <= DR_CAPTURE; else tap_ctrl_state <= IR_SCAN; end if;
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when DR_CAPTURE => if (tap_sync.tms = '0') then tap_ctrl_state <= DR_SHIFT; else tap_ctrl_state <= DR_EXIT1; end if;
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when DR_SHIFT => if (tap_sync.tms = '0') then tap_ctrl_state <= DR_SHIFT; else tap_ctrl_state <= DR_EXIT1; end if;
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when DR_EXIT1 => if (tap_sync.tms = '0') then tap_ctrl_state <= DR_PAUSE; else tap_ctrl_state <= DR_UPDATE; end if;
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when DR_PAUSE => if (tap_sync.tms = '0') then tap_ctrl_state <= DR_PAUSE; else tap_ctrl_state <= DR_EXIT2; end if;
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when DR_EXIT2 => if (tap_sync.tms = '0') then tap_ctrl_state <= DR_SHIFT; else tap_ctrl_state <= DR_UPDATE; end if;
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when DR_UPDATE => if (tap_sync.tms = '0') then tap_ctrl_state <= RUN_IDLE; else tap_ctrl_state <= DR_SCAN; end if;
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when IR_SCAN => if (tap_sync.tms = '0') then tap_ctrl_state <= IR_CAPTURE; else tap_ctrl_state <= LOGIC_RESET; end if;
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when IR_CAPTURE => if (tap_sync.tms = '0') then tap_ctrl_state <= IR_SHIFT; else tap_ctrl_state <= IR_EXIT1; end if;
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when IR_SHIFT => if (tap_sync.tms = '0') then tap_ctrl_state <= IR_SHIFT; else tap_ctrl_state <= IR_EXIT1; end if;
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when IR_EXIT1 => if (tap_sync.tms = '0') then tap_ctrl_state <= IR_PAUSE; else tap_ctrl_state <= IR_UPDATE; end if;
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when IR_PAUSE => if (tap_sync.tms = '0') then tap_ctrl_state <= IR_PAUSE; else tap_ctrl_state <= IR_EXIT2; end if;
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when IR_EXIT2 => if (tap_sync.tms = '0') then tap_ctrl_state <= IR_SHIFT; else tap_ctrl_state <= IR_UPDATE; end if;
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when IR_UPDATE => if (tap_sync.tms = '0') then tap_ctrl_state <= RUN_IDLE; else tap_ctrl_state <= DR_SCAN; end if;
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when others => tap_ctrl_state <= LOGIC_RESET;
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end case;
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end if;
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end if;
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end process tap_control;
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-- trigger for UPDATE state --
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update_trigger: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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dr_trigger.sreg <= "00";
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elsif rising_edge(clk_i) then
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if (tap_ctrl_state = DR_UPDATE) then
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dr_trigger.sreg(0) <= '1';
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else
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dr_trigger.sreg(0) <= '0';
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end if;
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dr_trigger.sreg(1) <= dr_trigger.sreg(0);
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end if;
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end process update_trigger;
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dr_trigger.valid <= '1' when (dr_trigger.sreg = "01") else '0';
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-- Tap Register Access --------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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reg_access: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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tap_reg.ireg <= (others => '0');
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tap_reg.idcode <= (others => '0');
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tap_reg.dtmcs <= (others => '0');
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tap_reg.dmi <= (others => '0');
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tap_reg.bypass <= '0';
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jtag_tdo_o <= '0';
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elsif rising_edge(clk_i) then
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-- serial data input: instruction register --
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if (tap_ctrl_state = LOGIC_RESET) or (tap_ctrl_state = IR_CAPTURE) then -- preload phase
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tap_reg.ireg <= addr_idcode_c;
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elsif (tap_ctrl_state = IR_SHIFT) then -- access phase
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if (tap_sync.tck_rising = '1') then -- [JTAG-SYNC] evaluate TDI on rising edge of TCK
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tap_reg.ireg <= tap_sync.tdi & tap_reg.ireg(tap_reg.ireg'left downto 1);
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end if;
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end if;
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-- serial data input: data register --
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if (tap_ctrl_state = DR_CAPTURE) then -- preload phase
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case tap_reg.ireg is
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when addr_idcode_c => tap_reg.idcode <= IDCODE_VERSION & IDCODE_PARTID & IDCODE_MANID & '1'; -- identifier (LSB has to be set)
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when addr_dtmcs_c => tap_reg.dtmcs <= tap_reg.dtmcs_nxt; -- status register
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when addr_dmi_c => tap_reg.dmi <= tap_reg.dmi_nxt; -- register interface
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when others => tap_reg.bypass <= '0'; -- pass through
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end case;
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elsif (tap_ctrl_state = DR_SHIFT) then -- access phase
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if (tap_sync.tck_rising = '1') then -- [JTAG-SYNC] evaluate TDI on rising edge of TCK
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case tap_reg.ireg is
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when addr_idcode_c => tap_reg.idcode <= tap_sync.tdi & tap_reg.idcode(tap_reg.idcode'left downto 1);
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when addr_dtmcs_c => tap_reg.dtmcs <= tap_sync.tdi & tap_reg.dtmcs(tap_reg.dtmcs'left downto 1);
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when addr_dmi_c => tap_reg.dmi <= tap_sync.tdi & tap_reg.dmi(tap_reg.dmi'left downto 1);
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when others => tap_reg.bypass <= tap_sync.tdi;
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end case;
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end if;
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end if;
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-- serial data output --
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if (tap_sync.tck_falling = '1') then -- [JTAG-SYNC] update TDO on falling edge of TCK
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if (tap_ctrl_state = IR_SHIFT) then
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jtag_tdo_o <= tap_reg.ireg(0);
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else
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case tap_reg.ireg is
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when addr_idcode_c => jtag_tdo_o <= tap_reg.idcode(0);
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when addr_dtmcs_c => jtag_tdo_o <= tap_reg.dtmcs(0);
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when addr_dmi_c => jtag_tdo_o <= tap_reg.dmi(0);
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when others => jtag_tdo_o <= tap_reg.bypass;
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end case;
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end if;
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end if;
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end if;
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end process reg_access;
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-- DTM Control and Status Register (dtmcs) --
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tap_reg.dtmcs_nxt(31 downto 18) <= (others => '0'); -- reserved
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tap_reg.dtmcs_nxt(17) <= dmi_ctrl.dmihardreset; -- dmihardreset
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tap_reg.dtmcs_nxt(16) <= dmi_ctrl.dmireset; -- dmireset
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tap_reg.dtmcs_nxt(15) <= '0'; -- reserved
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tap_reg.dtmcs_nxt(14 downto 12) <= dmi_idle_c; -- minimum number of idle cycles
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tap_reg.dtmcs_nxt(11 downto 10) <= tap_reg.dmi_nxt(1 downto 0); -- dmistat
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tap_reg.dtmcs_nxt(09 downto 04) <= dmi_abits_c; -- number of DMI address bits
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tap_reg.dtmcs_nxt(03 downto 00) <= dmi_version_c; -- version
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-- DMI register read access --
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tap_reg.dmi_nxt(40 downto 34) <= dmi_ctrl.addr; -- address
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tap_reg.dmi_nxt(33 downto 02) <= dmi_ctrl.rdata; -- read data
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tap_reg.dmi_nxt(01 downto 00) <= (others => dmi_ctrl.err); -- status
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-- Debug Module Interface -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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dmi_controller: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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dmi_ctrl.busy <= '0';
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dmi_ctrl.op <= "00";
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dmi_ctrl.dmihardreset <= '1';
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dmi_ctrl.dmireset <= '0';
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dmi_ctrl.err <= '0';
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dmi_ctrl.rdata <= (others => '0');
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dmi_ctrl.wdata <= (others => '0');
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dmi_ctrl.addr <= (others => '0');
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elsif rising_edge(clk_i) then
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-- DMI reset control --
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if (dr_trigger.valid = '1') and (tap_reg.ireg = addr_dtmcs_c) then
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dmi_ctrl.dmireset <= tap_reg.dtmcs(16);
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dmi_ctrl.dmihardreset <= tap_reg.dtmcs(17);
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elsif (dmi_ctrl.busy = '0') then
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dmi_ctrl.dmihardreset <= '0';
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dmi_ctrl.dmireset <= '0';
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end if;
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-- sticky error --
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if (dmi_ctrl.dmireset = '1') or (dmi_ctrl.dmihardreset = '1') then
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dmi_ctrl.err <= '0';
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elsif (dmi_ctrl.busy = '1') and (dr_trigger.valid = '1') and (tap_reg.ireg = addr_dmi_c) then -- access attempt while DMI is busy
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dmi_ctrl.err <= '1';
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end if;
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-- DMI interface arbiter --
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dmi_ctrl.op <= dmi_req_nop_c; -- default
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if (dmi_ctrl.busy = '0') then -- idle: waiting for new request
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if (dmi_ctrl.dmihardreset = '0') then -- no DMI hard reset
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if (dr_trigger.valid = '1') and (tap_reg.ireg = addr_dmi_c) then
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dmi_ctrl.addr <= tap_reg.dmi(40 downto 34);
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dmi_ctrl.wdata <= tap_reg.dmi(33 downto 02);
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if (tap_reg.dmi(1 downto 0) = dmi_req_rd_c) or (tap_reg.dmi(1 downto 0) = dmi_req_wr_c) then
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dmi_ctrl.op <= tap_reg.dmi(1 downto 0);
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dmi_ctrl.busy <= '1';
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end if;
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end if;
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end if;
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else -- busy: read/write access in progress
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dmi_ctrl.rdata <= dmi_rsp_i.data;
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if (dmi_rsp_i.ack = '1') then
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dmi_ctrl.busy <= '0';
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end if;
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end if;
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end if;
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end process dmi_controller;
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-- direct DMI output --
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dmi_req_o.op <= dmi_ctrl.op;
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dmi_req_o.data <= dmi_ctrl.wdata;
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dmi_req_o.addr <= dmi_ctrl.addr;
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end neorv32_debug_dtm_rtl;
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