218 lines
10 KiB
VHDL
218 lines
10 KiB
VHDL
-- #################################################################################################
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-- # << NEORV32 - External Interrupt Controller (XIRQ) >> #
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-- # ********************************************************************************************* #
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-- # Simple interrupt controller for platform (processor-external) interrupts. Up to 32 channels #
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-- # are supported that get (optionally) prioritized into a single CPU interrupt. #
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-- # #
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-- # The actual trigger configuration has to be done BEFORE synthesis using the XIRQ_TRIGGER_TYPE #
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-- # and XIRQ_TRIGGER_POLARITY generics. These allow to configure channel-independent low-level, #
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-- # high-level, falling-edge and rising-edge triggers. #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 #
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-- # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_xirq is
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generic (
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XIRQ_NUM_CH : natural range 0 to 32; -- number of external IRQ channels
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XIRQ_TRIGGER_TYPE : std_ulogic_vector(31 downto 0); -- trigger type: 0=level, 1=edge
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XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
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);
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port (
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clk_i : in std_ulogic; -- global clock line
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rstn_i : in std_ulogic; -- global reset line, low-active
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bus_req_i : in bus_req_t; -- bus request
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bus_rsp_o : out bus_rsp_t; -- bus response
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xirq_i : in std_ulogic_vector(31 downto 0); -- external IRQ channels
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cpu_irq_o : out std_ulogic -- CPU interrupt
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);
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end neorv32_xirq;
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architecture neorv32_xirq_rtl of neorv32_xirq is
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-- interface registers --
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signal irq_enable : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0); -- r/w: channel enable
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signal nclr_pending : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0); -- r/w: pending IRQs
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signal irq_source : std_ulogic_vector(4 downto 0); -- r/w: source IRQ, ACK on write
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-- interrupt trigger --
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signal irq_sync : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0);
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signal irq_sync2 : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0);
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signal irq_trig : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0);
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-- interrupt buffer --
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signal irq_pending : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0);
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signal irq_raw : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0);
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signal irq_fire : std_ulogic;
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-- interrupt arbiter --
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signal irq_source_nxt : std_ulogic_vector(4 downto 0);
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signal irq_active : std_ulogic;
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begin
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-- Bus Access -----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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bus_access: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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bus_rsp_o.ack <= '0';
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bus_rsp_o.err <= '0';
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bus_rsp_o.data <= (others => '0');
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nclr_pending <= (others => '0');
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irq_enable <= (others => '0');
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elsif rising_edge(clk_i) then
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-- bus handshake --
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bus_rsp_o.ack <= bus_req_i.stb;
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bus_rsp_o.err <= '0';
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bus_rsp_o.data <= (others => '0');
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-- defaults --
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nclr_pending <= (others => '1');
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if (bus_req_i.stb = '1') then
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-- write access --
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if (bus_req_i.rw = '1') then
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if (bus_req_i.addr(3 downto 2) = "00") then -- channel-enable
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irq_enable <= bus_req_i.data(XIRQ_NUM_CH-1 downto 0);
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end if;
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if (bus_req_i.addr(3 downto 2) = "01") then -- clear pending IRQs
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nclr_pending <= bus_req_i.data(XIRQ_NUM_CH-1 downto 0); -- set zero to clear pending IRQ
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end if;
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-- read access --
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else
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case bus_req_i.addr(3 downto 2) is
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when "00" => bus_rsp_o.data(XIRQ_NUM_CH-1 downto 0) <= irq_enable; -- channel-enable
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when "01" => bus_rsp_o.data(XIRQ_NUM_CH-1 downto 0) <= irq_pending; -- pending IRQs
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when others => bus_rsp_o.data(4 downto 0) <= irq_source; -- IRQ source
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end case;
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end if;
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end if;
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end if;
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end process bus_access;
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-- IRQ Trigger --------------------------------------------------------------
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-- -----------------------------------------------------------------------------
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synchronizer: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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irq_sync <= (others => '0');
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irq_sync2 <= (others => '0');
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elsif rising_edge(clk_i) then
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irq_sync <= xirq_i(XIRQ_NUM_CH-1 downto 0);
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irq_sync2 <= irq_sync;
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end if;
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end process synchronizer;
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-- trigger type select --
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irq_trigger_gen:
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for i in 0 to XIRQ_NUM_CH-1 generate
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irq_trigger: process(irq_sync, irq_sync2)
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variable sel_v : std_ulogic_vector(1 downto 0);
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begin
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sel_v := XIRQ_TRIGGER_TYPE(i) & XIRQ_TRIGGER_POLARITY(i);
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case sel_v is
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when "00" => irq_trig(i) <= not irq_sync(i); -- low-level
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when "01" => irq_trig(i) <= irq_sync(i); -- high-level
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when "10" => irq_trig(i) <= (not irq_sync(i)) and irq_sync2(i); -- falling-edge
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when "11" => irq_trig(i) <= irq_sync(i) and (not irq_sync2(i)); -- rising-edge
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when others => irq_trig(i) <= '0';
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end case;
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end process irq_trigger;
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end generate;
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-- IRQ Buffer ---------------------------------------------------------------
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-- -----------------------------------------------------------------------------
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irq_buffer: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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irq_pending <= (others => '0');
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elsif rising_edge(clk_i) then
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irq_pending <= (irq_pending and nclr_pending) or irq_trig;
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end if;
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end process irq_buffer;
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-- filter enabled channels --
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irq_raw <= irq_pending and irq_enable;
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-- encode current IRQ's priority --
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priority_encoder: process(irq_raw)
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begin
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irq_source_nxt <= (others => '0');
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if (XIRQ_NUM_CH > 1) then
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for i in 0 to XIRQ_NUM_CH-1 loop
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if (irq_raw(i) = '1') then
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irq_source_nxt <= std_ulogic_vector(to_unsigned(i, irq_source_nxt'length));
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exit;
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end if;
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end loop;
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end if;
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end process priority_encoder;
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-- anyone firing? --
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irq_fire <= '1' when (or_reduce_f(irq_raw) = '1') else '0';
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-- IRQ Arbiter --------------------------------------------------------------
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-- -----------------------------------------------------------------------------
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irq_arbiter: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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cpu_irq_o <= '0';
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irq_active <= '0';
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irq_source <= (others => '0');
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elsif rising_edge(clk_i) then
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cpu_irq_o <= '0';
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if (irq_active = '0') then -- no active IRQ
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irq_source <= irq_source_nxt; -- get IRQ source that has highest priority
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if (irq_fire = '1') then
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cpu_irq_o <= '1';
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irq_active <= '1';
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end if;
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elsif (bus_req_i.stb = '1') and (bus_req_i.rw = '1') and (bus_req_i.addr(3 downto 2) = "10") then -- acknowledge on write access
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irq_active <= '0';
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end if;
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end if;
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end process irq_arbiter;
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end neorv32_xirq_rtl;
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