neorv32/rtl/test_setups/neorv32_test_setup_bootload...

112 lines
5.6 KiB
Verilog

// #################################################################################################
// # << NEORV32 - Test Setup using the default UART-Bootloader to upload and run executables >> #
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
// # #
// # 1. Redistributions of source code must retain the above copyright notice, this list of #
// # conditions and the following disclaimer. #
// # #
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
// # conditions and the following disclaimer in the documentation and/or other materials #
// # provided with the distribution. #
// # #
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
// # endorse or promote products derived from this software without specific prior written #
// # permission. #
// # #
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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// # OF THE POSSIBILITY OF SUCH DAMAGE. #
// # ********************************************************************************************* #
// # The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 #
// #################################################################################################
// no timescale needed
module neorv32_test_setup_bootloader(
input wire clk_i,
input wire rstn_i,
output wire [7:0] gpio_o,
output wire uart0_txd_o,
input wire uart0_rxd_i
);
// adapt these for your setup --
parameter [31:0] CLOCK_FREQUENCY=100000000;
parameter [31:0] MEM_INT_IMEM_SIZE=16 * 1024;
parameter [31:0] MEM_INT_DMEM_SIZE=8 * 1024;
// size of processor-internal data memory in bytes
// Global control --
// global clock, rising edge
// global reset, low-active, async
// GPIO --
// parallel output
// UART0 --
// UART0 send data
// UART0 receive data
wire [63:0] con_gpio_o;
// The Core Of The Problem ----------------------------------------------------------------
// -------------------------------------------------------------------------------------------
neorv32_top #(
// General --
.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
// clock frequency of clk_i in Hz
.INT_BOOTLOADER_EN(true),
// boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
// RISC-V CPU Extensions --
.CPU_EXTENSION_RISCV_C(true),
// implement compressed extension?
.CPU_EXTENSION_RISCV_M(true),
// implement mul/div extension?
.CPU_EXTENSION_RISCV_Zicntr(true),
// implement base counters?
// Internal Instruction memory --
.MEM_INT_IMEM_EN(true),
// implement processor-internal instruction memory
.MEM_INT_IMEM_SIZE(MEM_INT_IMEM_SIZE),
// size of processor-internal instruction memory in bytes
// Internal Data memory --
.MEM_INT_DMEM_EN(true),
// implement processor-internal data memory
.MEM_INT_DMEM_SIZE(MEM_INT_DMEM_SIZE),
// size of processor-internal data memory in bytes
// Processor peripherals --
.IO_GPIO_NUM(8),
// number of GPIO input/output pairs (0..64)
.IO_MTIME_EN(true),
// implement machine system timer (MTIME)?
.IO_UART0_EN(true))
neorv32_top_inst(
// Global control --
.clk_i(clk_i),
// global clock, rising edge
.rstn_i(rstn_i),
// global reset, low-active, async
// GPIO (available if IO_GPIO_EN = true) --
.gpio_o(con_gpio_o),
// parallel output
// primary UART0 (available if IO_GPIO_NUM > 0) --
.uart0_txd_o(uart0_txd_o),
// UART0 send data
.uart0_rxd_i(uart0_rxd_i));
// GPIO output --
assign gpio_o = con_gpio_o[7:0];
endmodule