57 lines
3.0 KiB
Plaintext
57 lines
3.0 KiB
Plaintext
<<<
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:sectnums:
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==== Processor-Internal Instruction Cache (iCACHE)
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[cols="<3,<3,<4"]
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[frame="topbot",grid="none"]
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|=======================
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| Hardware source file(s): | neorv32_icache.vhd |
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| Software driver file(s): | none | _implicitly used_
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| Top entity port: | none |
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| Configuration generics: | `ICACHE_EN` | implement processor-internal instruction cache when `true`
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| | `ICACHE_NUM_BLOCKS` | number of cache blocks (pages/lines)
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| | `ICACHE_BLOCK_SIZE` | size of a cache block in bytes
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| | `ICACHE_ASSOCIATIVITY` | associativity / number of sets
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| CPU interrupts: | none |
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|=======================
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The processor features an optional instruction cache to improve performance when using memories with high
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access latencies. The cache is directly connected to the CPU's instruction fetch interface and provides
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full-transparent buffering of instruction fetch accesses to the **entire address space**.
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The cache is implemented if the `ICACHE_EN` generic is `true`. The size of the cache memory is defined via
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`ICACHE_BLOCK_SIZE` (the size of a single cache block/page/line in bytes; has to be a power of two and greater than or
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equal to 4 bytes), `ICACHE_NUM_BLOCKS` (the total amount of cache blocks; has to be a power of two and greater than or
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equal to 1) and the actual cache associativity `ICACHE_ASSOCIATIVITY` (number of sets; 1 = direct-mapped, 2 = 2-way
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set-associative) generics. If the cache associativity is greater than one the LRU replacement policy (least recently
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used) is used.
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**Cached/Uncached Accesses**
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The data cache provides direct accesses (= uncached) to memory in order to access memory-mapped IO (like the
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processor-internal IO/peripheral modules). All accesses that target the address range from `0xF0000000` to `0xFFFFFFFF`
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will not be cached at all (see section <<_address_space>>).
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.Caching Internal Memories
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[NOTE]
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The instruction cache is intended to accelerate instruction fetches from **processor-external** memories
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(via the external bus interface or via the XIP module). The cache(s) should not be implemented
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when using only processor-internal data and instruction memories.
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.Manual Cache Clear/Reload
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[NOTE]
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By executing the `fence(.i)` instruction the cache is cleared and a reload from main memory is triggered.
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.Retrieve Cache Configuration from Software
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[TIP]
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Software can retrieve the cache configuration/layout from the <<_sysinfo_cache_configuration>> register.
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.Bus Access Fault Handling
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[NOTE]
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The cache always loads a complete cache block (aligned to the block size) every time a
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cache miss is detected. Each cached word from this block provides a single status bit that indicates if the
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according bus access was successful or caused a bus error. Hence, the whole cache block remains valid even
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if certain addresses inside caused a bus error. If the CPU accesses any of the faulty cache words, an
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instruction bus error exception is raised.
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