39 lines
1.7 KiB
Plaintext
39 lines
1.7 KiB
Plaintext
<<<
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:sectnums:
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== NEORV32 in Verilog
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If you are more of a Verilog fan or if your EDA toolchain does not support VHDL or mixed-language designs
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you can use an **all-Verilog** version of the processor provided by the https://github.com/stnolting/neorv32-verilog[`neorv32-verilog`] repository.
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[IMPORTANT]
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Note that this is **not a manual re-implementation of the core in Verilog** but rather an automated conversion.
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GHDL's synthesis feature is used to convert a pre-configured NEORV32 setup - including all peripherals, memories
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and memory images - into an unoptimized plain-Verilog netlist module file without any (technology-specific) primitives.
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.GHDL Synthesis
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[TIP]
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More information regarding GHDL's synthesis option can be found at https://ghdl.github.io/ghdl/using/Synthesis.html.
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An intermediate VHDL wrapper is provided that can be used to configure the processor (using VHDL generics) and to customize
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the interface ports. After conversion, a single Verilog file is generated that contains the whole NEORV32 processor.
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The original processor module hierarchy is preserved as well as most (all?) signal names, which allows easy inspection and debugging
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of simulation waveforms and synthesis results.
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.Example: interface of the resulting NEORV32 Verilog module (for a minimal SoC configuration)
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[source,verilog]
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----
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module neorv32_verilog_wrapper
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(input clk_i,
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input rstn_i,
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input uart0_rxd_i,
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output uart0_txd_o);
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----
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The generated Verilog netlist has been tested with
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https://github.com/steveicarus/iverilog[Icarus Verilog]
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(simulation) and Xilinx Vivado (simulation and synthesis).
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[TIP]
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For detailed information check out the `neorv32-verilog` repository at https://github.com/stnolting/neorv32-verilog.
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