109 lines
6.9 KiB
Plaintext
109 lines
6.9 KiB
Plaintext
:sectnums:
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=== Rationale
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[discrete]
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==== Why did you make this?
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Processor and CPU architecture designs are fascinating things: they are the magic frontier where software meets hardware.
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This project started as something like a _journey_ into this magic realm to understand how things actually work
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down on this very low level and evolved over time to a capable system on chip.
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But there is more: when I started to dive into the emerging RISC-V ecosystem I felt overwhelmed by the complexity.
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As a beginner it is hard to get an overview - especially when you want to setup a minimal platform to tinker with...
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Which core to use? How to get the right toolchain? What features do I need? How does booting work? How do I
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create an actual executable? How to get that into the hardware? How to customize things? **_Where to start???_**
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This project aims to provide a _simple to understand_ and _easy to use_ yet _powerful_ and _flexible_ platform
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that targets FPGA and RISC-V beginners as well as advanced users.
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[discrete]
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==== Why a _soft-core_ processor?
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As a matter of fact soft-core processors _cannot_ compete with discrete (like FPGA hard-macro) processors in terms
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of performance, energy efficiency and size. But they do fill a niche in FPGA design space: for example, soft-core
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processors allow to implement the _control flow part_ of certain applications (e.g. communication protocol handling)
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using software like plain C. This provides high flexibility as software can be easily changed, re-compiled and
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re-uploaded again.
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Furthermore, the concept of flexibility applies to all aspects of a soft-core processor. The user can add
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_exactly_ the features that are required by the application: additional memories, custom interfaces, specialized
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co-processors and even user-defined instructions.
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[discrete]
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==== Why RISC-V?
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image::riscv_logo.png[width=250,align=left]
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[quote, RISC-V International, https://riscv.org/about/]
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____
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RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration.
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____
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Open-source is a great thing!
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While open-source has already become quite popular in _software_, hardware-focused projects still need to catch up.
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Admittedly, there has been quite a development, but mainly in terms of _platforms_ and _applications_ (so
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schematics, PCBs, etc.). Although processors and CPUs are the heart of almost every digital system, having a true
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open-source silicon is still a rarity. RISC-V aims to change that - and even it is _just one approach_, it helps paving
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the road for future development.
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Furthermore, I highly appreciate the community aspect of RISC-V. The ISA and everything beyond is developed in direct
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contact with the community: this includes businesses and professionals but also hobbyist, amateurs and people
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that are just curious. Everyone can join discussions and contribute to RISC-V in their very own way.
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Finally, I really like the RISC-V ISA itself. It aims to be a clean, orthogonal and "intuitive" ISA that
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resembles with the basic concepts of _RISC_: simple yet effective.
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[discrete]
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==== Yet another RISC-V core? What makes it special?
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The NEORV32 is not based on another RISC-V core. It was build entirely from ground up (just following the official
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ISA specs). The project does not intend to replace certain RISC-V cores or
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just beat existing ones like https://github.com/SpinalHDL/VexRiscv[VexRISC] in terms of performance or
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https://github.com/olofk/serv[SERV] in terms of size. It was build having a different design goal in mind.
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The project aims to provide _another option_ in the RISC-V / soft-core design space with a different performance
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vs. size trade-off and a different focus: _embrace_ concepts like documentation, platform-independence / portability,
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RISC-V compatibility, _extensibility & customization_ and _ease of use_ (see the <<_project_key_features>> below).
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Furthermore, the NEORV32 pays special focus on _execution safety_ using <<_full_virtualization>>. The CPU aims to
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provide fall-backs for _everything that could go wrong_. This includes malformed instruction words, privilege escalations
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and even memory accesses that are checked for address space holes and deterministic response times of memory-mapped
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devices. Precise exceptions allow a defined and fully-synchronized state of the CPU at every time an in every situation.
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[discrete]
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==== A multi-cycle architecture?!?!
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Most mainstream CPUs out there are pipelined architectures to increase throughput. In contrast, most CPUs used for
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teaching are single-cycle designs since they are probably the most easiest to understand. But what about the
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multi-cycle architectures?
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In terms of energy, throughput, area and maximal clock frequency multi-cycle architectures are somewhere in between
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single-cycle and fully-pipelined designs: they provide higher throughput and clock speed when compared to their
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single-cycle counterparts while having less hardware complexity (= area) then a fully-pipelined designs. I decided to
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use the multi-cycle approach because of the following reasons:
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* Multi-cycle architecture are quite small! There is no need for pipeline hazard detection and resolution logic
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(e.g. forwarding). Furthermore, you can "re-use" parts of the core to do several tasks (e.g. the ALU is used for the
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actual data processing, but also for address generation, branch condition check and branch target computation).
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* Single-cycle architectures require memories that can be read asynchronously - a thing that is not feasible to implement
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in real world applications (i.e. FPGA block RAM is entirely synchronous). Furthermore, such design usually have a very
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long critical path tremendously reducing maximal operating frequency.
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* Pipelined designs increase performance by having several instruction "in fly" at the same time. But this also means
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there is some kind of "out-of-order" behavior: if an instruction at the end of the pipeline causes an exception
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all the instructions in earlier stages have to be invalidated. Potential architecture state changes have to be made _undone_
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requiring additional (exception-handling) logic. In a multi-cycle architecture this situation cannot occur because only a
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single instruction is "in fly" at a time.
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* Having only a single instruction in fly does not only reduce hardware costs, it also simplifies
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simulation/verification/debugging, state preservation/restoring during exceptions and extensibility (no need to care
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about pipeline hazards) - but of course at the cost of reduced throughput.
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To counteract the loss of performance implied by a _pure_ multi-cycle architecture, the NEORV32 CPU uses a _mixed_
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approach: instruction fetch (front-end) and instruction execution (back-end) are de-coupled to operate independently
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of each other. Data is interchanged via a queue building a simple 2-stage pipeline. Each "pipeline" stage in terms is
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implemented as multi-cycle architecture to simplify the hardware and to provide _precise_ state control (e.g. during
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exceptions).
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