45 lines
2.0 KiB
Plaintext
45 lines
2.0 KiB
Plaintext
<<<
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:sectnums:
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==== General Purpose Input and Output Port (GPIO)
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[cols="<3,<3,<4"]
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[frame="topbot",grid="none"]
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|=======================
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| Hardware source file(s): | neorv32_gpio.vhd |
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| Software driver file(s): | neorv32_gpio.c |
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| | neorv32_gpio.h |
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| Top entity port: | `gpio_o` | 64-bit parallel output port
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| | `gpio_i` | 64-bit parallel input port
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| Configuration generics: | `IO_GPIO_NUM` | number of input/output pairs to implement (0..64)
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| CPU interrupts: | none |
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|=======================
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The general purpose parallel IO unit provides a simple parallel input and output port. These ports can be used
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chip-externally (for example to drive status LEDs, connect buttons, etc.) or chip-internally to provide control
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signals for other IP modules.
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The actual number of input/output pairs is defined by the `IO_GPIO_NUM` generic. When set to zero, the GPIO module
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is excluded from synthesis and the output port `gpio_o` is tied to all-zero. If `IO_GPIO_NUM` is less than the
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maximum value of 64, only the LSB-aligned bits in `gpio_o` and `gpio_i` are actually connected while the remaining
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bits are tied to zero or are left unconnected, respectively.
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.Access Atomicity
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[NOTE]
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The GPIO modules uses two memory-mapped registers (each 32-bit) each for accessing the input and
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output signals. Since the CPU can only process 32-bit "at once" updating the entire output cannot
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be performed within a single clock cycle.
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**Register Map**
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.GPIO unit register map (`struct NEORV32_GPIO`)
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[cols="<2,<2,^1,^1,<6"]
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[options="header",grid="rows"]
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|=======================
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| Address | Name [C] | Bit(s) | R/W | Function
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| `0xfffffc00` | `INPUT_LO` | 31:0 | r/- | parallel input port pins 31:0
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| `0xfffffc04` | `INPUT_HI` | 31:0 | r/- | parallel input port pins 63:32
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| `0xfffffc08` | `OUTPUT_LO` | 31:0 | r/w | parallel output port pins 31:0
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| `0xfffffc0c` | `OUTPUT_HI` | 31:0 | r/w | parallel output port pins 63:32
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|=======================
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