379 lines
15 KiB
Verilog
379 lines
15 KiB
Verilog
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// #################################################################################################
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// # << NEORV32 - Processor Top Entity with AvalonMM Compatible Host Interface >> #
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// # ********************************************************************************************* #
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// # (c) "AvalonMM", "Qsys", "MegaWizard" and "Platform Designer" are trademarks of Intel corp. #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License #
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// # #
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// # The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 #
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// # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
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// # #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # permitted provided that the following conditions are met: #
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// # #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of #
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// # conditions and the following disclaimer. #
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// # #
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// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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// # conditions and the following disclaimer in the documentation and/or other materials #
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// # provided with the distribution. #
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// # #
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// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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// # endorse or promote products derived from this software without specific prior written #
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// # permission. #
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// # #
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// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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// # OF THE POSSIBILITY OF SUCH DAMAGE. #
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// #################################################################################################
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// no timescale needed
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module neorv32_top_avalonmm(
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input wire clk_i,
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input wire rstn_i,
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input wire jtag_trst_i,
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input wire jtag_tck_i,
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input wire jtag_tdi_i,
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output wire jtag_tdo_o,
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input wire jtag_tms_i,
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output wire read_o,
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output wire write_o,
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input wire waitrequest_i,
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output wire [3:0] byteenable_o,
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output wire [31:0] address_o,
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output wire [31:0] writedata_o,
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input wire [31:0] readdata_i,
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output wire xip_csn_o,
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output wire xip_clk_o,
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input wire xip_dat_i,
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output wire xip_dat_o,
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output wire [63:0] gpio_o,
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input wire [63:0] gpio_i,
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output wire uart0_txd_o,
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input wire uart0_rxd_i,
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output wire uart0_rts_o,
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input wire uart0_cts_i,
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output wire uart1_txd_o,
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input wire uart1_rxd_i,
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output wire uart1_rts_o,
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input wire uart1_cts_i,
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output wire spi_clk_o,
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output wire spi_dat_o,
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input wire spi_dat_i,
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output wire [7:0] spi_csn_o,
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input wire twi_sda_i,
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output wire twi_sda_o,
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input wire twi_scl_i,
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output wire twi_scl_o,
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input wire onewire_i,
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output wire onewire_o,
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output wire [11:0] pwm_o,
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input wire [IO_CFS_IN_SIZE - 1:0] cfs_in_i,
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output wire [IO_CFS_OUT_SIZE - 1:0] cfs_out_o,
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output wire neoled_o,
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input wire [31:0] xirq_i,
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input wire mtime_irq_i,
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input wire msw_irq_i,
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input wire mext_irq_i
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);
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// General --
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parameter [31:0] CLOCK_FREQUENCY;
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parameter [31:0] HART_ID=32'h00000000;
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parameter [31:0] VENDOR_ID=32'h00000000;
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parameter INT_BOOTLOADER_EN=false;
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parameter ON_CHIP_DEBUGGER_EN=false;
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parameter CPU_EXTENSION_RISCV_B=false;
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parameter CPU_EXTENSION_RISCV_C=false;
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parameter CPU_EXTENSION_RISCV_E=false;
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parameter CPU_EXTENSION_RISCV_M=false;
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parameter CPU_EXTENSION_RISCV_U=false;
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parameter CPU_EXTENSION_RISCV_Zfinx=false;
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parameter CPU_EXTENSION_RISCV_Zicntr=true;
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parameter CPU_EXTENSION_RISCV_Zihpm=false;
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parameter CPU_EXTENSION_RISCV_Zmmul=false;
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parameter CPU_EXTENSION_RISCV_Zxcfu=false;
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parameter FAST_MUL_EN=false;
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parameter FAST_SHIFT_EN=false;
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parameter [31:0] PMP_NUM_REGIONS=0;
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parameter [31:0] PMP_MIN_GRANULARITY=4;
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parameter [31:0] HPM_NUM_CNTS=0;
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parameter [31:0] HPM_CNT_WIDTH=40;
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parameter MEM_INT_IMEM_EN=false;
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parameter [31:0] MEM_INT_IMEM_SIZE=16 * 1024;
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parameter MEM_INT_DMEM_EN=false;
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parameter [31:0] MEM_INT_DMEM_SIZE=8 * 1024;
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parameter ICACHE_EN=false;
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parameter [31:0] ICACHE_NUM_BLOCKS=4;
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parameter [31:0] ICACHE_BLOCK_SIZE=64;
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parameter [31:0] ICACHE_ASSOCIATIVITY=1;
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parameter DCACHE_EN=false;
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parameter [31:0] DCACHE_NUM_BLOCKS=4;
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parameter [31:0] DCACHE_BLOCK_SIZE=64;
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parameter XIP_EN=false;
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parameter XIP_CACHE_EN=false;
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parameter [31:0] XIP_CACHE_NUM_BLOCKS=8;
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parameter [31:0] XIP_CACHE_BLOCK_SIZE=256;
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parameter [31:0] XIRQ_NUM_CH=0;
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parameter [31:0] XIRQ_TRIGGER_TYPE=32'hffffffff;
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parameter [31:0] XIRQ_TRIGGER_POLARITY=32'hffffffff;
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parameter [31:0] IO_GPIO_NUM=0;
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parameter IO_MTIME_EN=false;
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parameter IO_UART0_EN=false;
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parameter [31:0] IO_UART0_RX_FIFO=1;
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parameter [31:0] IO_UART0_TX_FIFO=1;
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parameter IO_UART1_EN=false;
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parameter [31:0] IO_UART1_RX_FIFO=1;
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parameter [31:0] IO_UART1_TX_FIFO=1;
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parameter IO_SPI_EN=false;
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parameter [31:0] IO_SPI_FIFO=1;
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parameter IO_TWI_EN=false;
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parameter [31:0] IO_PWM_NUM_CH=0;
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parameter IO_WDT_EN=false;
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parameter IO_TRNG_EN=false;
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parameter [31:0] IO_TRNG_FIFO=1;
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parameter IO_CFS_EN=false;
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parameter [31:0] IO_CFS_CONFIG=32'h00000000;
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parameter [31:0] IO_CFS_IN_SIZE=32;
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parameter [31:0] IO_CFS_OUT_SIZE=32;
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parameter IO_NEOLED_EN=false;
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parameter [31:0] IO_NEOLED_TX_FIFO=1;
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parameter IO_GPTMR_EN=false;
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parameter IO_ONEWIRE_EN=false;
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// implement 1-wire interface (ONEWIRE)?
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// Global control --
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// global clock, rising edge
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// global reset, low-active, async
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// JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
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// low-active TAP reset (optional)
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// serial clock
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// serial data input
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// serial data output
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// mode select
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// AvalonMM interface
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// XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) --
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// chip-select, low-active
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// serial clock
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// device data input
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// controller data output
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// GPIO (available if IO_GPIO_EN = true) --
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// parallel output
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// parallel input
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// primary UART0 (available if IO_UART0_EN = true) --
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// UART0 send data
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// UART0 receive data
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// HW flow control: UART0.RX ready to receive ("RTR"), low-active, optional
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// HW flow control: UART0.TX allowed to transmit, low-active, optional
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// secondary UART1 (available if IO_UART1_EN = true) --
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// UART1 send data
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// UART1 receive data
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// HW flow control: UART1.RX ready to receive ("RTR"), low-active, optional
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// HW flow control: UART1.TX allowed to transmit, low-active, optional
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// SPI (available if IO_SPI_EN = true) --
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// SPI serial clock
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// controller data out, peripheral data in
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// controller data in, peripheral data out
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// chip-select
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// TWI (available if IO_TWI_EN = true) --
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// serial data line sense input
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// serial data line output (pull low only)
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// serial clock line sense input
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// serial clock line output (pull low only)
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// 1-Wire Interface (available if IO_ONEWIRE_EN = true) --
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// 1-wire bus sense input
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// 1-wire bus output (pull low only)
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// PWM (available if IO_PWM_NUM_CH > 0) --
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// pwm channels
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// Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
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// custom CFS inputs conduit
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// custom CFS outputs conduit
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// NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
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// async serial data line
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// External platform interrupts (available if XIRQ_NUM_CH > 0) --
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// IRQ channels
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// CPU interrupts --
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// machine timer interrupt, available if IO_MTIME_EN = false
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// machine software interrupt
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// machine external interrupt
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// Wishbone bus interface (available if MEM_EXT_EN = true) --
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wire [2:0] wb_tag_o; // request tag
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wire [31:0] wb_adr_o; // address
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wire [31:0] wb_dat_i = 1'bU; // read data
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wire [31:0] wb_dat_o; // write data
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wire wb_we_o; // read/write
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wire [3:0] wb_sel_o; // byte enable
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wire wb_stb_o; // strobe
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wire wb_cyc_o; // valid cycle
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wire wb_ack_i = 1'bL; // transfer acknowledge
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wire wb_err_i = 1'bL; // transfer error
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neorv32_top #(
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// General --
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.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
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.HART_ID(HART_ID),
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.VENDOR_ID(VENDOR_ID),
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// On-Chip Debugger (OCD) --
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.ON_CHIP_DEBUGGER_EN(ON_CHIP_DEBUGGER_EN),
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// RISC-V CPU Extensions --
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.CPU_EXTENSION_RISCV_B(CPU_EXTENSION_RISCV_B),
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.CPU_EXTENSION_RISCV_C(CPU_EXTENSION_RISCV_C),
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.CPU_EXTENSION_RISCV_E(CPU_EXTENSION_RISCV_E),
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.CPU_EXTENSION_RISCV_M(CPU_EXTENSION_RISCV_M),
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.CPU_EXTENSION_RISCV_U(CPU_EXTENSION_RISCV_U),
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.CPU_EXTENSION_RISCV_Zfinx(CPU_EXTENSION_RISCV_Zfinx),
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.CPU_EXTENSION_RISCV_Zicntr(CPU_EXTENSION_RISCV_Zicntr),
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.CPU_EXTENSION_RISCV_Zihpm(CPU_EXTENSION_RISCV_Zihpm),
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.CPU_EXTENSION_RISCV_Zmmul(CPU_EXTENSION_RISCV_Zmmul),
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.CPU_EXTENSION_RISCV_Zxcfu(CPU_EXTENSION_RISCV_Zxcfu),
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// Extension Options --
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.FAST_MUL_EN(FAST_MUL_EN),
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.FAST_SHIFT_EN(FAST_SHIFT_EN),
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// Physical Memory Protection (PMP) --
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.PMP_NUM_REGIONS(PMP_NUM_REGIONS),
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.PMP_MIN_GRANULARITY(PMP_MIN_GRANULARITY),
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// Hardware Performance Monitors (HPM) --
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.HPM_NUM_CNTS(HPM_NUM_CNTS),
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.HPM_CNT_WIDTH(HPM_CNT_WIDTH),
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// Internal Instruction memory (IMEM) --
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.MEM_INT_IMEM_EN(MEM_INT_IMEM_EN),
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.MEM_INT_IMEM_SIZE(MEM_INT_IMEM_SIZE),
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// Internal Data memory (DMEM) --
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.MEM_INT_DMEM_EN(MEM_INT_IMEM_EN),
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.MEM_INT_DMEM_SIZE(MEM_INT_DMEM_SIZE),
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// Internal Cache memory (iCACHE) --
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.ICACHE_EN(ICACHE_EN),
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.ICACHE_NUM_BLOCKS(ICACHE_NUM_BLOCKS),
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.ICACHE_BLOCK_SIZE(ICACHE_BLOCK_SIZE),
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.ICACHE_ASSOCIATIVITY(ICACHE_ASSOCIATIVITY),
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// Internal Data Cache (dCACHE) --
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.DCACHE_EN(DCACHE_EN),
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.DCACHE_NUM_BLOCKS(DCACHE_NUM_BLOCKS),
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.DCACHE_BLOCK_SIZE(DCACHE_BLOCK_SIZE),
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// External memory interface (WISHBONE) --
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.MEM_EXT_EN(true),
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.MEM_EXT_TIMEOUT(0),
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.MEM_EXT_PIPE_MODE(false),
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.MEM_EXT_BIG_ENDIAN(false),
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.MEM_EXT_ASYNC_RX(false),
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.MEM_EXT_ASYNC_TX(false),
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// Execute in-place module (XIP) --
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.XIP_EN(XIP_EN),
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.XIP_CACHE_EN(XIP_CACHE_EN),
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.XIP_CACHE_NUM_BLOCKS(XIP_CACHE_NUM_BLOCKS),
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.XIP_CACHE_BLOCK_SIZE(XIP_CACHE_BLOCK_SIZE),
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// External Interrupts Controller (XIRQ) --
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.XIRQ_NUM_CH(XIRQ_NUM_CH),
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.XIRQ_TRIGGER_TYPE(XIRQ_TRIGGER_TYPE),
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.XIRQ_TRIGGER_POLARITY(XIRQ_TRIGGER_POLARITY),
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// Processor peripherals --
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.IO_GPIO_NUM(IO_GPIO_NUM),
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.IO_MTIME_EN(IO_MTIME_EN),
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.IO_UART0_EN(IO_UART0_EN),
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.IO_UART0_RX_FIFO(IO_UART0_RX_FIFO),
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.IO_UART0_TX_FIFO(IO_UART0_TX_FIFO),
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.IO_UART1_EN(IO_UART1_EN),
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.IO_UART1_RX_FIFO(IO_UART1_RX_FIFO),
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.IO_UART1_TX_FIFO(IO_UART1_TX_FIFO),
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.IO_SPI_EN(IO_SPI_EN),
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.IO_SPI_FIFO(IO_SPI_FIFO),
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.IO_TWI_EN(IO_TWI_EN),
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.IO_PWM_NUM_CH(IO_PWM_NUM_CH),
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.IO_WDT_EN(IO_WDT_EN),
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.IO_TRNG_EN(IO_TRNG_EN),
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.IO_TRNG_FIFO(IO_TRNG_FIFO),
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.IO_CFS_EN(IO_CFS_EN),
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.IO_CFS_CONFIG(IO_CFS_CONFIG),
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.IO_CFS_IN_SIZE(IO_CFS_IN_SIZE),
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.IO_CFS_OUT_SIZE(IO_CFS_OUT_SIZE),
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.IO_NEOLED_EN(IO_NEOLED_EN),
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.IO_NEOLED_TX_FIFO(IO_NEOLED_TX_FIFO),
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.IO_GPTMR_EN(IO_GPTMR_EN),
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.IO_ONEWIRE_EN(IO_ONEWIRE_EN))
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neorv32_top_map(
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// Global control --
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.clk_i(clk_i),
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.rstn_i(rstn_i),
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// JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
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.jtag_trst_i(jtag_trst_i),
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.jtag_tck_i(jtag_tck_i),
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.jtag_tdi_i(jtag_tdi_i),
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.jtag_tdo_o(jtag_tdo_o),
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.jtag_tms_i(jtag_tms_i),
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// Wishbone bus interface (available if MEM_EXT_EN = true) --
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.wb_tag_o(wb_tag_o),
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.wb_adr_o(wb_adr_o),
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.wb_dat_i(wb_dat_i),
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.wb_dat_o(wb_dat_o),
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.wb_we_o(wb_we_o),
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.wb_sel_o(wb_sel_o),
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.wb_stb_o(wb_stb_o),
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.wb_cyc_o(wb_cyc_o),
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.wb_ack_i(wb_ack_i),
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.wb_err_i(wb_err_i),
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// XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) --
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.xip_csn_o(xip_csn_o),
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.xip_clk_o(xip_clk_o),
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.xip_dat_i(xip_dat_i),
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.xip_dat_o(xip_dat_o),
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// GPIO (available if IO_GPIO_EN = true) --
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.gpio_o(gpio_o),
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.gpio_i(gpio_i),
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// primary UART0 (available if IO_UART0_EN = true) --
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.uart0_txd_o(uart0_txd_o),
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.uart0_rxd_i(uart0_rxd_i),
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.uart0_rts_o(uart0_rts_o),
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.uart0_cts_i(uart0_cts_i),
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// secondary UART1 (available if IO_UART1_EN = true) --
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.uart1_txd_o(uart1_txd_o),
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.uart1_rxd_i(uart1_rxd_i),
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.uart1_rts_o(uart1_rts_o),
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.uart1_cts_i(uart1_cts_i),
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// SPI (available if IO_SPI_EN = true) --
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.spi_clk_o(spi_clk_o),
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.spi_dat_o(spi_dat_o),
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.spi_dat_i(spi_dat_i),
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.spi_csn_o(spi_csn_o),
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// TWI (available if IO_TWI_EN = true) --
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.twi_sda_i(twi_sda_i),
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.twi_sda_o(twi_sda_o),
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.twi_scl_i(twi_scl_i),
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.twi_scl_o(twi_scl_o),
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// 1-Wire Interface (available if IO_ONEWIRE_EN = true) --
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.onewire_i(onewire_i),
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.onewire_o(onewire_o),
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// PWM (available if IO_PWM_NUM_CH > 0) --
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.pwm_o(pwm_o),
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// Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
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.cfs_in_i(cfs_in_i),
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.cfs_out_o(cfs_out_o),
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// NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
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.neoled_o(neoled_o),
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// External platform interrupts (available if XIRQ_NUM_CH > 0) --
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.xirq_i(xirq_i),
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// CPU interrupts --
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.mtime_irq_i(mtime_irq_i),
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.msw_irq_i(msw_irq_i),
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.mext_irq_i(mext_irq_i));
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// Wishbone to AvalonMM bridge
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assign read_o = (wb_stb_o == 1'b1 && wb_we_o == 1'b0) ? 1'b1 : 1'b0;
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assign write_o = (wb_stb_o == 1'b1 && wb_we_o == 1'b1) ? 1'b1 : 1'b0;
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assign address_o = wb_adr_o;
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assign writedata_o = wb_dat_o;
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assign byteenable_o = wb_sel_o;
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assign wb_dat_i = readdata_i;
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assign wb_ack_i = ~(waitrequest_i);
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assign wb_err_i = 1'b0;
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endmodule
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