1656 lines
68 KiB
XML
1656 lines
68 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
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<vendor>stnolting</vendor>
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<name>neorv32</name>
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<series>RISC-V</series>
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<version>1.9.5</version>
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<description>The NEORV32 RISC-V Processor</description>
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<!-- CPU core -->
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<cpu>
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<name>NEORV32</name>
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<revision>r2p0</revision>
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<endian>little</endian>
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<mpuPresent>true</mpuPresent>
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<fpuPresent>true</fpuPresent>
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<fpuDP>false</fpuDP>
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<dspPresent>false</dspPresent>
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<icachePresent>true</icachePresent>
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<dcachePresent>true</dcachePresent>
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<nvicPrioBits>4</nvicPrioBits>
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<vendorSystickConfig>false</vendorSystickConfig>
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</cpu>
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<!-- defaults for all peripherals -->
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<addressUnitBits>8</addressUnitBits>
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<width>32</width>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0x00000000</resetMask> <!-- default IO devices do not have a dedicated reset -->
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<!-- Peripherals -->
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<peripherals>
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<!-- CFS ------------------------------------------------------------------------------------->
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<!-------------------------------------------------------------------------------------------->
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<peripheral>
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<name>CFS</name>
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<description>Custom functions subsystem</description>
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<groupName>CFS</groupName>
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<baseAddress>0xFFFFEB00</baseAddress>
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<interrupt><name>CFS_FIRQ</name><value>1</value></interrupt>
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<addressBlock>
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<offset>0</offset>
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<size>0x100</size>
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<usage>registers</usage>
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</addressBlock>
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<registers>
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<register><name>REG0</name><description>User-defined</description><addressOffset>0x00</addressOffset></register>
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<register><name>REG1</name><description>User-defined</description><addressOffset>0x04</addressOffset></register>
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<register><name>REG2</name><description>User-defined</description><addressOffset>0x08</addressOffset></register>
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<register><name>REG3</name><description>User-defined</description><addressOffset>0x0C</addressOffset></register>
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<register><name>REG4</name><description>User-defined</description><addressOffset>0x10</addressOffset></register>
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<register><name>REG5</name><description>User-defined</description><addressOffset>0x14</addressOffset></register>
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<register><name>REG6</name><description>User-defined</description><addressOffset>0x18</addressOffset></register>
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<register><name>REG7</name><description>User-defined</description><addressOffset>0x1C</addressOffset></register>
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<register><name>REG8</name><description>User-defined</description><addressOffset>0x20</addressOffset></register>
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<register><name>REG9</name><description>User-defined</description><addressOffset>0x24</addressOffset></register>
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<register><name>REG10</name><description>User-defined</description><addressOffset>0x28</addressOffset></register>
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<register><name>REG11</name><description>User-defined</description><addressOffset>0x2C</addressOffset></register>
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<register><name>REG12</name><description>User-defined</description><addressOffset>0x30</addressOffset></register>
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<register><name>REG13</name><description>User-defined</description><addressOffset>0x34</addressOffset></register>
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<register><name>REG14</name><description>User-defined</description><addressOffset>0x38</addressOffset></register>
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<register><name>REG15</name><description>User-defined</description><addressOffset>0x3C</addressOffset></register>
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<register><name>REG16</name><description>User-defined</description><addressOffset>0x40</addressOffset></register>
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<register><name>REG17</name><description>User-defined</description><addressOffset>0x44</addressOffset></register>
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<register><name>REG18</name><description>User-defined</description><addressOffset>0x48</addressOffset></register>
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<register><name>REG19</name><description>User-defined</description><addressOffset>0x4C</addressOffset></register>
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<register><name>REG20</name><description>User-defined</description><addressOffset>0x50</addressOffset></register>
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<register><name>REG21</name><description>User-defined</description><addressOffset>0x54</addressOffset></register>
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<register><name>REG22</name><description>User-defined</description><addressOffset>0x58</addressOffset></register>
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<register><name>REG23</name><description>User-defined</description><addressOffset>0x5C</addressOffset></register>
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<register><name>REG24</name><description>User-defined</description><addressOffset>0x60</addressOffset></register>
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<register><name>REG25</name><description>User-defined</description><addressOffset>0x64</addressOffset></register>
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<register><name>REG26</name><description>User-defined</description><addressOffset>0x68</addressOffset></register>
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<register><name>REG27</name><description>User-defined</description><addressOffset>0x6C</addressOffset></register>
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<register><name>REG28</name><description>User-defined</description><addressOffset>0x70</addressOffset></register>
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<register><name>REG29</name><description>User-defined</description><addressOffset>0x74</addressOffset></register>
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<register><name>REG30</name><description>User-defined</description><addressOffset>0x78</addressOffset></register>
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<register><name>REG31</name><description>User-defined</description><addressOffset>0x7C</addressOffset></register>
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<register><name>REG32</name><description>User-defined</description><addressOffset>0x80</addressOffset></register>
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<register><name>REG33</name><description>User-defined</description><addressOffset>0x84</addressOffset></register>
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<register><name>REG34</name><description>User-defined</description><addressOffset>0x88</addressOffset></register>
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<register><name>REG35</name><description>User-defined</description><addressOffset>0x8C</addressOffset></register>
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<register><name>REG36</name><description>User-defined</description><addressOffset>0x90</addressOffset></register>
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<register><name>REG37</name><description>User-defined</description><addressOffset>0x94</addressOffset></register>
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<register><name>REG38</name><description>User-defined</description><addressOffset>0x98</addressOffset></register>
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<register><name>REG39</name><description>User-defined</description><addressOffset>0x9C</addressOffset></register>
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<register><name>REG40</name><description>User-defined</description><addressOffset>0xA0</addressOffset></register>
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<register><name>REG41</name><description>User-defined</description><addressOffset>0xA4</addressOffset></register>
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<register><name>REG42</name><description>User-defined</description><addressOffset>0xA8</addressOffset></register>
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<register><name>REG43</name><description>User-defined</description><addressOffset>0xAC</addressOffset></register>
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<register><name>REG44</name><description>User-defined</description><addressOffset>0xB0</addressOffset></register>
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<register><name>REG45</name><description>User-defined</description><addressOffset>0xB4</addressOffset></register>
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<register><name>REG46</name><description>User-defined</description><addressOffset>0xB8</addressOffset></register>
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<register><name>REG47</name><description>User-defined</description><addressOffset>0xBC</addressOffset></register>
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<register><name>REG48</name><description>User-defined</description><addressOffset>0xC0</addressOffset></register>
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<register><name>REG49</name><description>User-defined</description><addressOffset>0xC4</addressOffset></register>
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<register><name>REG50</name><description>User-defined</description><addressOffset>0xC8</addressOffset></register>
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<register><name>REG51</name><description>User-defined</description><addressOffset>0xCC</addressOffset></register>
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<register><name>REG52</name><description>User-defined</description><addressOffset>0xD0</addressOffset></register>
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<register><name>REG53</name><description>User-defined</description><addressOffset>0xD4</addressOffset></register>
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<register><name>REG54</name><description>User-defined</description><addressOffset>0xD8</addressOffset></register>
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<register><name>REG55</name><description>User-defined</description><addressOffset>0xDC</addressOffset></register>
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<register><name>REG56</name><description>User-defined</description><addressOffset>0xE0</addressOffset></register>
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<register><name>REG57</name><description>User-defined</description><addressOffset>0xE4</addressOffset></register>
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<register><name>REG58</name><description>User-defined</description><addressOffset>0xE8</addressOffset></register>
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<register><name>REG59</name><description>User-defined</description><addressOffset>0xEC</addressOffset></register>
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<register><name>REG60</name><description>User-defined</description><addressOffset>0xF0</addressOffset></register>
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<register><name>REG61</name><description>User-defined</description><addressOffset>0xF4</addressOffset></register>
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<register><name>REG62</name><description>User-defined</description><addressOffset>0xF8</addressOffset></register>
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<register><name>REG63</name><description>User-defined</description><addressOffset>0xFC</addressOffset></register>
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</registers>
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</peripheral>
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<!-- SDI ------------------------------------------------------------------------------------->
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<!-------------------------------------------------------------------------------------------->
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<peripheral>
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<name>SDI</name>
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<description>Serial data interface controller</description>
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<groupName>SDI</groupName>
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<baseAddress>0xFFFFF700</baseAddress>
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<interrupt><name>SDI_FIRQ</name><value>11</value></interrupt>
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<addressBlock>
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<offset>0</offset>
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<size>0x08</size>
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<usage>registers</usage>
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</addressBlock>
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<registers>
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<register>
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<name>CTRL</name>
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<description>Control register</description>
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<addressOffset>0x00</addressOffset>
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<fields>
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<field>
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<name>SDI_CTRL_EN</name>
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<bitRange>[0:0]</bitRange>
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<description>SDI enable flag</description>
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</field>
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<field>
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<name>SDI_CTRL_CLR_RX</name>
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<bitRange>[1:1]</bitRange>
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<description>Clear RX FIFO, bit auto-clears</description>
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</field>
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<field>
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<name>SDI_CTRL_FIFO</name>
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<bitRange>[7:4]</bitRange>
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<description>Log2 of SDI FIFO size</description>
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</field>
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<field>
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<name>SDI_CTRL_IRQ_RX_AVAIL</name>
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<bitRange>[15:15]</bitRange>
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<description>Fire interrupt if RX FIFO is not empty</description>
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</field>
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<field>
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<name>SDI_CTRL_IRQ_RX_HALF</name>
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<bitRange>[16:16]</bitRange>
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<description>Fire interrupt if RX FIFO is at least half full</description>
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</field>
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<field>
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<name>SDI_CTRL_IRQ_RX_FULL</name>
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<bitRange>[17:17]</bitRange>
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<description>Fire interrupt if RX FIFO is full</description>
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</field>
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<field>
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<name>SDI_CTRL_IRQ_TX_EMPTY</name>
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<bitRange>[18:18]</bitRange>
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<description>Fire interrupt if TX FIFO is empty</description>
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</field>
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<field>
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<name>SDI_CTRL_RX_AVAIL</name>
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<bitRange>[23:23]</bitRange>
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<access>read-only</access>
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<description>RX FIFO not empty (data available)</description>
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</field>
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<field>
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<name>SDI_CTRL_RX_HALF</name>
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<bitRange>[24:24]</bitRange>
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<access>read-only</access>
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<description>RX FIFO at least half full</description>
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</field>
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<field>
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<name>SDI_CTRL_RX_FULL</name>
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<bitRange>[25:25]</bitRange>
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<access>read-only</access>
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<description>RX FIFO full</description>
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</field>
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<field>
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<name>SDI_CTRL_TX_EMPTY</name>
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<bitRange>[26:26]</bitRange>
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<access>read-only</access>
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<description>TX FIFO empty</description>
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</field>
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<field>
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<name>SDI_CTRL_TX_FULL</name>
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<bitRange>[27:27]</bitRange>
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<access>read-only</access>
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<description>TX FIFO full</description>
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</field>
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</fields>
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</register>
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<register>
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<name>DATA</name>
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<description>RX/TX data register (lowest 8 bit)</description>
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<addressOffset>0x04</addressOffset>
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</register>
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</registers>
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</peripheral>
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<!-- SLINK ----------------------------------------------------------------------------------->
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<!-------------------------------------------------------------------------------------------->
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<peripheral>
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<name>SLINK</name>
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<description>Stream Link Interface</description>
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<groupName>SLINK</groupName>
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<baseAddress>0xFFFFEC00</baseAddress>
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<interrupt><name>SLINK_FIRQ</name><value>14</value></interrupt>
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<addressBlock>
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<offset>0</offset>
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<size>0x10</size>
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<usage>registers</usage>
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</addressBlock>
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<registers>
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<register>
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<name>CTRL</name>
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<description>Control register</description>
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<addressOffset>0x00</addressOffset>
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<fields>
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<field>
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<name>SLINK_CTRL_EN</name>
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<bitRange>[0:0]</bitRange>
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<description>SLINK enable flag</description>
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</field>
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<field>
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<name>SLINK_CTRL_RX_CLR</name>
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<bitRange>[1:1]</bitRange>
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<description>Clear RX FIFO (auto-clears)</description>
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</field>
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<field>
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<name>SLINK_CTRL_TX_CLR</name>
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<bitRange>[2:2]</bitRange>
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<description>Clear TX FIFO (auto-clears)</description>
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</field>
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<field>
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<name>SLINK_CTRL_RX_LAST</name>
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<bitRange>[4:4]</bitRange>
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<description>RX link end-of-stream delimiter</description>
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</field>
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<field>
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<name>SLINK_CTRL_RX_EMPTY</name>
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<bitRange>[8:8]</bitRange>
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<access>read-only</access>
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<description>RX FIFO empty</description>
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</field>
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<field>
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<name>SLINK_CTRL_RX_HALF</name>
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<bitRange>[9:9]</bitRange>
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<access>read-only</access>
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<description>RX FIFO at least half full</description>
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</field>
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<field>
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<name>SLINK_CTRL_RX_FULL</name>
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<bitRange>[10:10]</bitRange>
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<access>read-only</access>
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<description>RX FIFO full</description>
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</field>
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<field>
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<name>SLINK_CTRL_TX_EMPTY</name>
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<bitRange>[11:11]</bitRange>
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<access>read-only</access>
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<description>TX FIFO empty</description>
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</field>
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<field>
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<name>SLINK_CTRL_TX_HALF</name>
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<bitRange>[12:12]</bitRange>
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<access>read-only</access>
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<description>TX FIFO at least half full</description>
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</field>
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<field>
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<name>SLINK_CTRL_TX_FULL</name>
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<bitRange>[13:13]</bitRange>
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<access>read-only</access>
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<description>TX FIFO full</description>
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</field>
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<field>
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<name>SLINK_CTRL_IRQ_RX_NEMPTY</name>
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<bitRange>[16:16]</bitRange>
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<description>IRQ if RX FIFO not empty</description>
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</field>
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<field>
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<name>SLINK_CTRL_IRQ_RX_HALF</name>
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<bitRange>[17:17]</bitRange>
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<description>IRQ if RX FIFO at least half full</description>
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</field>
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<field>
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<name>SLINK_CTRL_IRQ_RX_FULL</name>
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<bitRange>[18:18]</bitRange>
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<description>IRQ if RX FIFO full</description>
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</field>
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<field>
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<name>SLINK_CTRL_IRQ_TX_EMPTY</name>
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<bitRange>[19:19]</bitRange>
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<description>IRQ if TX FIFO empty</description>
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</field>
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<field>
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<name>SLINK_CTRL_IRQ_TX_NHALF</name>
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<bitRange>[20:20]</bitRange>
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<description>IRQ if TX FIFO not at least half full</description>
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</field>
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<field>
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<name>SLINK_CTRL_IRQ_TX_NFULL</name>
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<bitRange>[21:21]</bitRange>
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<description>IRQ if TX FIFO not full</description>
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</field>
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<field>
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<name>SLINK_CTRL_RX_FIFO</name>
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<bitRange>[27:24]</bitRange>
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<access>read-only</access>
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<description>log2(RX FIFO size)</description>
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</field>
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<field>
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<name>SLINK_CTRL_TX_FIFO</name>
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<bitRange>[31:28]</bitRange>
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<access>read-only</access>
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<description>log2(TX FIFO size)</description>
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</field>
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</fields>
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</register>
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<register>
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<name>RX_DATA</name>
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<description>RX link receive data</description>
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<access>read-only</access>
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<addressOffset>0x04</addressOffset>
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</register>
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<register>
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<name>TX_DATA</name>
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<description>TX link transmit data</description>
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<addressOffset>0x08</addressOffset>
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</register>
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<register>
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<name>TX_DATA_LAST</name>
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<description>TX link transmit data (plus end-of-stream delimiter)</description>
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<addressOffset>0x0c</addressOffset>
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</register>
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</registers>
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</peripheral>
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<!-- DMA ------------------------------------------------------------------------------------->
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<!-------------------------------------------------------------------------------------------->
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<peripheral>
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<name>DMA</name>
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<description>Direct memory access controller</description>
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<groupName>DMA</groupName>
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<baseAddress>0xFFFFED00</baseAddress>
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<interrupt><name>DMA_FIRQ</name><value>10</value></interrupt>
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<addressBlock>
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<offset>0</offset>
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<size>0x10</size>
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<usage>registers</usage>
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</addressBlock>
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<registers>
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<register>
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<name>CTRL</name>
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<description>Control register</description>
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<addressOffset>0x00</addressOffset>
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<fields>
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<field>
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<name>DMA_CTRL_EN</name>
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<bitRange>[0:0]</bitRange>
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<description>DMA enable flag</description>
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</field>
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<field>
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<name>DMA_CTRL_AUTO</name>
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<bitRange>[1:1]</bitRange>
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<description>Enable automatic transfer trigger (FIRQ-triggered)</description>
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</field>
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<field>
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<name>DMA_CTRL_FENCE</name>
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<bitRange>[2:2]</bitRange>
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<description>Issue a downstream FENCE operation when DMA transfer completes (without errors)</description>
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</field>
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<field>
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<name>DMA_CTRL_ERROR_RD</name>
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<bitRange>[8:8]</bitRange>
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<access>read-only</access>
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<description>Error during last read access</description>
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</field>
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<field>
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<name>DMA_CTRL_ERROR_WR</name>
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<bitRange>[9:9]</bitRange>
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<access>read-only</access>
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<description>Error during last write access</description>
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</field>
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<field>
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<name>DMA_CTRL_BUSY</name>
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<bitRange>[10:10]</bitRange>
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<access>read-only</access>
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<description>DMA transfer in progress</description>
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</field>
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<field>
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<name>DMA_CTRL_DONE</name>
|
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<bitRange>[11:11]</bitRange>
|
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<description>DMA transfer done; auto-clears on write access</description>
|
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</field>
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<field>
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|
<name>DMA_CTRL_FIRQ_MASK</name>
|
|
<bitRange>[31:16]</bitRange>
|
|
<description>FIRQ trigger mask</description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRC_BASE</name>
|
|
<description>Source base address; shows the last accessed read address on read access</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>DST_BASE</name>
|
|
<description>Destination base address; shows the last accessed write address on read access</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>TTYPE</name>
|
|
<description>Destination base address; shows the last accessed write address on read access</description>
|
|
<addressOffset>0x0c</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>DMA_TTYPE_NUM</name>
|
|
<bitRange>[23:0]</bitRange>
|
|
<description>Number of elements to transfer</description>
|
|
</field>
|
|
<field>
|
|
<name>DMA_TTYPE_QSEL</name>
|
|
<bitRange>[28:27]</bitRange>
|
|
<description>Data quantity select</description>
|
|
</field>
|
|
<field>
|
|
<name>DMA_TTYPE_SRC_INC</name>
|
|
<bitRange>[29:29]</bitRange>
|
|
<description>Source constant (0) or incrementing (1) address</description>
|
|
</field>
|
|
<field>
|
|
<name>DMA_TTYPE_DST_INC</name>
|
|
<bitRange>[30:30]</bitRange>
|
|
<description>Destination constant (0) or incrementing (1) address</description>
|
|
</field>
|
|
<field>
|
|
<name>DMA_TTYPE_ENDIAN</name>
|
|
<bitRange>[31:31]</bitRange>
|
|
<description>Convert Endianness when set</description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<!-- CRC ------------------------------------------------------------------------------------->
|
|
<!-------------------------------------------------------------------------------------------->
|
|
<peripheral>
|
|
<name>CRC</name>
|
|
<description>Cyclic redundancy check unit</description>
|
|
<groupName>CRC</groupName>
|
|
<baseAddress>0xFFFFEE00</baseAddress>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>MODE</name>
|
|
<description>CRC mode control (CRC8, CRC16, CRC32)</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>POLY</name>
|
|
<description>CRC polynomial</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>LSB-aligned data input (bytes)</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>SREG</name>
|
|
<description>CRC shift register</description>
|
|
<addressOffset>0x0c</addressOffset>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<!-- PWM ------------------------------------------------------------------------------------->
|
|
<!-------------------------------------------------------------------------------------------->
|
|
<peripheral>
|
|
<name>PWM</name>
|
|
<description>Pulse-width modulation controller</description>
|
|
<groupName>PWM</groupName>
|
|
<baseAddress>0xFFFFF000</baseAddress>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_CTRL_EN</name>
|
|
<bitRange>[0:0]</bitRange>
|
|
<description>PWM controller enable flag</description>
|
|
</field>
|
|
<field>
|
|
<name>PWM_CTRL_PRSCx</name>
|
|
<bitRange>[3:1]</bitRange>
|
|
<description>Clock prescaler select</description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DC[0]</name>
|
|
<description>Duty cycle register 0</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>DC[1]</name>
|
|
<description>Duty cycle register 1</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>DC[2]</name>
|
|
<description>Duty cycle register 2</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<!-- XIP ------------------------------------------------------------------------------------->
|
|
<!-------------------------------------------------------------------------------------------->
|
|
<peripheral>
|
|
<name>XIP</name>
|
|
<description>Execute In Place Module</description>
|
|
<groupName>CIP</groupName>
|
|
<baseAddress>0xFFFFEF00</baseAddress>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>XIP_CTRL_EN</name>
|
|
<bitRange>[0:0]</bitRange>
|
|
<description>XIP module enable flag</description>
|
|
</field>
|
|
<field>
|
|
<name>XIP_CTRL_PRSC</name>
|
|
<bitRange>[3:1]</bitRange>
|
|
<description>SPI clock prescaler select</description>
|
|
</field>
|
|
<field>
|
|
<name>XIP_CTRL_CPOL</name>
|
|
<bitRange>[4:4]</bitRange>
|
|
<description>SPI clock (idle) polarity</description>
|
|
</field>
|
|
<field>
|
|
<name>XIP_CTRL_CPHA</name>
|
|
<bitRange>[5:5]</bitRange>
|
|
<description>SPI clock phase</description>
|
|
</field>
|
|
<field>
|
|
<name>XIP_CTRL_SPI_NBYTES</name>
|
|
<bitRange>[9:6]</bitRange>
|
|
<description>Number of bytes in SPI transmission</description>
|
|
</field>
|
|
<field>
|
|
<name>XIP_CTRL_XIP_EN</name>
|
|
<bitRange>[10:10]</bitRange>
|
|
<description>XIP mode enable</description>
|
|
</field>
|
|
<field>
|
|
<name>XIP_CTRL_XIP_ABYTES</name>
|
|
<bitRange>[12:11]</bitRange>
|
|
<description>Number of XIP address bytes (minus 1)</description>
|
|
</field>
|
|
<field>
|
|
<name>XIP_CTRL_RD_CMD</name>
|
|
<bitRange>[20:13]</bitRange>
|
|
<description>SPI flash read command</description>
|
|
</field>
|
|
<field>
|
|
<name>XIP_CTRL_SPI_CSEN</name>
|
|
<bitRange>[21:21]</bitRange>
|
|
<description>SPI chip-select enable</description>
|
|
</field>
|
|
<field>
|
|
<name>XIP_CTRL_HIGHSPEED</name>
|
|
<bitRange>[22:22]</bitRange>
|
|
<description>SPI high-speed mode enable (ignoring XIP_CTRL_PRSC)</description>
|
|
</field>
|
|
<field>
|
|
<name>XIP_CTRL_CDIV</name>
|
|
<bitRange>[23:26]</bitRange>
|
|
<description>SPI clock divider</description>
|
|
</field>
|
|
<field>
|
|
<name>XIP_CTRL_BURST_EN</name>
|
|
<bitRange>[29:29]</bitRange>
|
|
<access>read-only</access>
|
|
<description>Busr mode enabled (when cache is implemented)</description>
|
|
</field>
|
|
<field>
|
|
<name>XIP_CTRL_PHY_BUSY</name>
|
|
<bitRange>[30:30]</bitRange>
|
|
<access>read-only</access>
|
|
<description>SPI PHY busy</description>
|
|
</field>
|
|
<field>
|
|
<name>XIP_CTRL_XIP_BUSY</name>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-only</access>
|
|
<description>XIP access in progress</description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA_LO</name>
|
|
<description>Direct SPI access - data register low</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>DATA_HI</name>
|
|
<description>Direct SPI access - data register high</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<!-- GPTMR ----------------------------------------------------------------------------------->
|
|
<!-------------------------------------------------------------------------------------------->
|
|
<peripheral>
|
|
<name>GPTMR</name>
|
|
<description>General purpose timer</description>
|
|
<groupName>GPTMR</groupName>
|
|
<baseAddress>0xFFFFF100</baseAddress>
|
|
|
|
<interrupt><name>GPTMR_FIRQ</name><value>12</value></interrupt>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>GPTMR_CTRL_EN</name>
|
|
<bitRange>[0:0]</bitRange>
|
|
<description>Timer enable flag</description>
|
|
</field>
|
|
<field>
|
|
<name>GPTMR_CTRL_PRSC</name>
|
|
<bitRange>[3:1]</bitRange>
|
|
<description>Clock prescaler select</description>
|
|
</field>
|
|
<field>
|
|
<name>GPTMR_CTRL_IRQM</name>
|
|
<bitRange>[4:4]</bitRange>
|
|
<description>Enable interrupt on timer match</description>
|
|
</field>
|
|
<field>
|
|
<name>GPTMR_CTRL_IRQC</name>
|
|
<bitRange>[5:5]</bitRange>
|
|
<description>Enable interrupt on capture trigger</description>
|
|
</field>
|
|
<field>
|
|
<name>GPTMR_CTRL_RISE</name>
|
|
<bitRange>[6:6]</bitRange>
|
|
<description>Capture on rising edge; capture-mode only</description>
|
|
</field>
|
|
<field>
|
|
<name>GPTMR_CTRL_FALL</name>
|
|
<bitRange>[7:7]</bitRange>
|
|
<description>Capture on falling edge; capture-mode only</description>
|
|
</field>
|
|
<field>
|
|
<name>GPTMR_CTRL_FILTER</name>
|
|
<bitRange>[8:8]</bitRange>
|
|
<description>Filter capture input; capture-mode only</description>
|
|
</field>
|
|
<field>
|
|
<name>GPTMR_CTRL_TRIGM</name>
|
|
<bitRange>[30:30]</bitRange>
|
|
<description>Timer-match has fired, cleared by writing 0</description>
|
|
</field>
|
|
<field>
|
|
<name>GPTMR_CTRL_TRIGC</name>
|
|
<bitRange>[31:31]</bitRange>
|
|
<description>Capture-trigger has fired, cleared by writing</description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>THRES</name>
|
|
<description>Threshold register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>COUNT</name>
|
|
<description>Counter register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>CAPTURE</name>
|
|
<description>Capture register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<access>read-only</access>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<!-- ONEWIRE --------------------------------------------------------------------------------->
|
|
<!-------------------------------------------------------------------------------------------->
|
|
<peripheral>
|
|
<name>ONEWIRE</name>
|
|
<description>1-Wire Interface Controller</description>
|
|
<groupName>ONEWIRE</groupName>
|
|
<baseAddress>0xFFFFF200</baseAddress>
|
|
|
|
<interrupt><name>ONEWIRE_FIRQ</name><value>13</value></interrupt>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x08</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ONEWIRE_CTRL_EN</name>
|
|
<bitRange>[0:0]</bitRange>
|
|
<description>ONEWIRE controller enable</description>
|
|
</field>
|
|
<field>
|
|
<name>ONEWIRE_CTRL_PRSC</name>
|
|
<bitRange>[2:1]</bitRange>
|
|
<description>Clock prescaler select</description>
|
|
</field>
|
|
<field>
|
|
<name>ONEWIRE_CTRL_CLKDIV</name>
|
|
<bitRange>[10:3]</bitRange>
|
|
<description>Clock divider</description>
|
|
</field>
|
|
<field>
|
|
<name>ONEWIRE_CTRL_TRIG_RST</name>
|
|
<bitRange>[11:11]</bitRange>
|
|
<description>Trigger reset pulse and presence detect operation, auto-clears</description>
|
|
</field>
|
|
<field>
|
|
<name>ONEWIRE_CTRL_TRIG_BIT</name>
|
|
<bitRange>[12:12]</bitRange>
|
|
<description>Trigger single-bit transmission operation, auto-clears</description>
|
|
</field>
|
|
<field>
|
|
<name>ONEWIRE_CTRL_TRIG_BYTE</name>
|
|
<bitRange>[13:13]</bitRange>
|
|
<description>Trigger full-byte transmission operation, auto-clears</description>
|
|
</field>
|
|
<field>
|
|
<name>ONEWIRE_CTRL_SENSE</name>
|
|
<bitRange>[29:29]</bitRange>
|
|
<access>read-only</access>
|
|
<description>Current state of the 1-wire bus line</description>
|
|
</field>
|
|
<field>
|
|
<name>ONEWIRE_CTRL_PRESENCE</name>
|
|
<bitRange>[30:30]</bitRange>
|
|
<access>read-only</access>
|
|
<description>Set if device(s) found during presence detect phase</description>
|
|
</field>
|
|
<field>
|
|
<name>ONEWIRE_CTRL_BUSY</name>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-only</access>
|
|
<description>Operation in progress when set</description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>Read/write transmission data register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ONEWIRE_DATA</name>
|
|
<bitRange>[7:0]</bitRange>
|
|
<description>RTX data, transmitted LSB-first</description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<!-- XIRQ ------------------------------------------------------------------------------------>
|
|
<!-------------------------------------------------------------------------------------------->
|
|
<peripheral>
|
|
<name>XIRQ</name>
|
|
<description>External interrupts controller</description>
|
|
<groupName>XIRQ</groupName>
|
|
<baseAddress>0xFFFFF300</baseAddress>
|
|
|
|
<interrupt><name>XIRQ_FIRQ</name><value>8</value></interrupt>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>IRQ input enable register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>IPR</name>
|
|
<description>IRQ pending/ack/clear register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>SCR</name>
|
|
<description>IRQ source register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<!-- MTIME ----------------------------------------------------------------------------------->
|
|
<!-------------------------------------------------------------------------------------------->
|
|
<peripheral>
|
|
<name>MTIME</name>
|
|
<description>Machine timer</description>
|
|
<groupName>MTIME</groupName>
|
|
<baseAddress>0xFFFFF400</baseAddress>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>TIME_LO</name>
|
|
<description>System time register - low</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>TIME_HI</name>
|
|
<description>System time register - high</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>TIMECMP_LO</name>
|
|
<description>Time compare register - low</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>TIMECMP_HI</name>
|
|
<description>Time compare register - high</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<!-- UART0 ----------------------------------------------------------------------------------->
|
|
<!-------------------------------------------------------------------------------------------->
|
|
<peripheral>
|
|
<name>UART0</name>
|
|
<description>Primary universal asynchronous receiver and transmitter</description>
|
|
<groupName>UART0</groupName>
|
|
<baseAddress>0xFFFFF500</baseAddress>
|
|
|
|
<interrupt><name>UART0_RX_FIRQ</name><value>2</value></interrupt>
|
|
<interrupt><name>UART0_TX_FIRQ</name><value>3</value></interrupt>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x08</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_CTRL_EN</name>
|
|
<bitRange>[0:0]</bitRange>
|
|
<description>UART enable flag</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_SIM_MODE</name>
|
|
<bitRange>[1:1]</bitRange>
|
|
<description>Simulation output override enable, for use in simulation only</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_HWFC_EN</name>
|
|
<bitRange>[2:2]</bitRange>
|
|
<description>Enable RTS/CTS hardware flow-control</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_PRSC</name>
|
|
<bitRange>[5:3]</bitRange>
|
|
<description>CLock prescaler select</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_BAUD</name>
|
|
<bitRange>[15:6]</bitRange>
|
|
<description>BAUD rate divisor</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_RX_NEMPTY</name>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-only</access>
|
|
<description>RX FIFO not empty</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_RX_HALF</name>
|
|
<bitRange>[17:17]</bitRange>
|
|
<access>read-only</access>
|
|
<description>RX FIFO at least half full</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_RX_FULL</name>
|
|
<bitRange>[18:18]</bitRange>
|
|
<access>read-only</access>
|
|
<description>RX FIFO full</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_TX_EMPTY</name>
|
|
<bitRange>[19:19]</bitRange>
|
|
<access>read-only</access>
|
|
<description>TX FIFO empty</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_TX_NHALF</name>
|
|
<bitRange>[20:20]</bitRange>
|
|
<access>read-only</access>
|
|
<description>TX FIFO not at least half full</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_TX_FULL</name>
|
|
<bitRange>[21:21]</bitRange>
|
|
<access>read-only</access>
|
|
<description>TX FIFO full</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_IRQ_RX_NEMPTY</name>
|
|
<bitRange>[22:22]</bitRange>
|
|
<description>Fire IRQ if RX FIFO not empty</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_IRQ_RX_HALF</name>
|
|
<bitRange>[23:23]</bitRange>
|
|
<description>Fire IRQ if RX FIFO at least half-full</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_IRQ_RX_FULL</name>
|
|
<bitRange>[24:24]</bitRange>
|
|
<description>Fire IRQ if RX FIFO full</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_IRQ_TX_EMPTY</name>
|
|
<bitRange>[25:25]</bitRange>
|
|
<description>Fire IRQ if TX FIFO empty</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_IRQ_TX_NHALF</name>
|
|
<bitRange>[26:26]</bitRange>
|
|
<description>Fire IRQ if TX FIFO not at least half-full</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_RX_OVER</name>
|
|
<bitRange>[30:30]</bitRange>
|
|
<access>read-only</access>
|
|
<description>RX FIFO overflow</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_TX_BUSY</name>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-only</access>
|
|
<description>Transmitter busy or TX FIFO not empty</description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>RTX data register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<!-- UART1 ----------------------------------------------------------------------------------->
|
|
<!-------------------------------------------------------------------------------------------->
|
|
<peripheral derivedFrom="UART0">
|
|
<name>UART1</name>
|
|
<description>Secondary universal asynchronous receiver and transmitter</description>
|
|
<groupName>UART1</groupName>
|
|
<baseAddress>0xFFFFF600</baseAddress>
|
|
|
|
<interrupt><name>UART1_RX_FIRQ</name><value>4</value></interrupt>
|
|
<interrupt><name>UART1_TX_FIRQ</name><value>5</value></interrupt>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x08</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
</peripheral>
|
|
|
|
<!-- SPI ------------------------------------------------------------------------------------->
|
|
<!-------------------------------------------------------------------------------------------->
|
|
<peripheral>
|
|
<name>SPI</name>
|
|
<description>Serial peripheral interface controller</description>
|
|
<groupName>SPI</groupName>
|
|
<baseAddress>0xFFFFF800</baseAddress>
|
|
|
|
<interrupt><name>SPI_FIRQ</name><value>6</value></interrupt>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x08</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SPI_CTRL_EN</name>
|
|
<bitRange>[0:0]</bitRange>
|
|
<description>SPI enable flag</description>
|
|
</field>
|
|
<field>
|
|
<name>SPI_CTRL_CPHA</name>
|
|
<bitRange>[1:1]</bitRange>
|
|
<description>Clock phase</description>
|
|
</field>
|
|
<field>
|
|
<name>SPI_CTRL_CPOL</name>
|
|
<bitRange>[2:2]</bitRange>
|
|
<description>Clock polarity</description>
|
|
</field>
|
|
<field>
|
|
<name>SPI_CTRL_CS_SEL</name>
|
|
<bitRange>[5:3]</bitRange>
|
|
<description>CS select</description>
|
|
</field>
|
|
<field>
|
|
<name>SPI_CTRL_CS_EN</name>
|
|
<bitRange>[6:6]</bitRange>
|
|
<description>Enable selected CS line</description>
|
|
</field>
|
|
<field>
|
|
<name>SPI_CTRL_PRSC</name>
|
|
<bitRange>[9:7]</bitRange>
|
|
<description>Clock prescaler select</description>
|
|
</field>
|
|
<field>
|
|
<name>SPI_CTRL_CDIV</name>
|
|
<bitRange>[13:10]</bitRange>
|
|
<description>SPI clock divider</description>
|
|
</field>
|
|
<field>
|
|
<name>SPI_CTRL_HIGHSPEED</name>
|
|
<bitRange>[14:14]</bitRange>
|
|
<description>SPI high-speed mode</description>
|
|
</field>
|
|
<field>
|
|
<name>SPI_CTRL_RX_AVAIL</name>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-only</access>
|
|
<description>RX FIFO data available (RX FIFO not empty)</description>
|
|
</field>
|
|
<field>
|
|
<name>SPI_CTRL_TX_EMPTY</name>
|
|
<bitRange>[17:17]</bitRange>
|
|
<access>read-only</access>
|
|
<description>TX FIFO is empty</description>
|
|
</field>
|
|
<field>
|
|
<name>SPI_CTRL_TX_NHALF</name>
|
|
<bitRange>[18:18]</bitRange>
|
|
<access>read-only</access>
|
|
<description>TX FIFO not at least half full</description>
|
|
</field>
|
|
<field>
|
|
<name>SPI_CTRL_TX_FULL</name>
|
|
<bitRange>[19:19]</bitRange>
|
|
<access>read-only</access>
|
|
<description>TX FIFO is full</description>
|
|
</field>
|
|
<field>
|
|
<name>SPI_CTRL_IRQ_RX_AVAIL</name>
|
|
<bitRange>[20:20]</bitRange>
|
|
<description>Fire interrupt if RX FIFO is not empty</description>
|
|
</field>
|
|
<field>
|
|
<name>SPI_CTRL_IRQ_TX_EMPTY</name>
|
|
<bitRange>[21:21]</bitRange>
|
|
<description>Fire interrupt if TX FIFO is empty</description>
|
|
</field>
|
|
<field>
|
|
<name>SPI_CTRL_IRQ_TX_NHALF</name>
|
|
<bitRange>[22:22]</bitRange>
|
|
<description>Fire interrupt if TX FIFO is not at least half full</description>
|
|
</field>
|
|
<field>
|
|
<name>SPI_CTRL_FIFO</name>
|
|
<bitRange>[26:23]</bitRange>
|
|
<access>read-only</access>
|
|
<description>log2(FIFO size)</description>
|
|
</field>
|
|
<field>
|
|
<name>SPI_CTRL_BUSY</name>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-only</access>
|
|
<description>SPI busy flag</description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>Data register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<!-- TWI ------------------------------------------------------------------------------------->
|
|
<!-------------------------------------------------------------------------------------------->
|
|
<peripheral>
|
|
<name>TWI</name>
|
|
<description>Two-wire interface controller</description>
|
|
<groupName>SPI</groupName>
|
|
<baseAddress>0xFFFFF900</baseAddress>
|
|
|
|
<interrupt><name>TWI_FIRQ</name><value>7</value></interrupt>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x08</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TWI_CTRL_EN</name>
|
|
<bitRange>[0:0]</bitRange>
|
|
<description>TWI enable flag</description>
|
|
</field>
|
|
<field>
|
|
<name>TWI_CTRL_START</name>
|
|
<bitRange>[1:1]</bitRange>
|
|
<description>Generate START condition, auto-clears</description>
|
|
</field>
|
|
<field>
|
|
<name>TWI_CTRL_STOP</name>
|
|
<bitRange>[2:2]</bitRange>
|
|
<description>Generate STOP condition, auto-clears</description>
|
|
</field>
|
|
<field>
|
|
<name>TWI_CTRL_MACK</name>
|
|
<bitRange>[3:3]</bitRange>
|
|
<description>Generate ACK by controller for each transmission</description>
|
|
</field>
|
|
<field>
|
|
<name>TWI_CTRL_CSEN</name>
|
|
<bitRange>[4:4]</bitRange>
|
|
<description>Allow clock stretching when set</description>
|
|
</field>
|
|
<field>
|
|
<name>TWI_CTRL_PRSC</name>
|
|
<bitRange>[7:5]</bitRange>
|
|
<description>Clock prescaler select</description>
|
|
</field>
|
|
<field>
|
|
<name>TWI_CTRL_CDIV</name>
|
|
<bitRange>[11:8]</bitRange>
|
|
<description>TWI clock divider</description>
|
|
</field>
|
|
<field>
|
|
<name>TWI_CTRL_CLAIMED</name>
|
|
<bitRange>[29:29]</bitRange>
|
|
<access>read-only</access>
|
|
<description>Set if the TWI bus is currently claimed by any controller</description>
|
|
</field>
|
|
<field>
|
|
<name>TWI_CTRL_ACK</name>
|
|
<bitRange>[30:30]</bitRange>
|
|
<access>read-only</access>
|
|
<description>ACK received when set</description>
|
|
</field>
|
|
<field>
|
|
<name>TWI_CTRL_BUSY</name>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-only</access>
|
|
<description>Transfer in progress, busy flag</description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>RX/TX data register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TWI_DATA</name>
|
|
<bitRange>[7:0]</bitRange>
|
|
<description>RX/TX data</description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<!-- TRNG ------------------------------------------------------------------------------------>
|
|
<!-------------------------------------------------------------------------------------------->
|
|
<peripheral>
|
|
<name>TRNG</name>
|
|
<description>True random number generator</description>
|
|
<groupName>TRNG</groupName>
|
|
<baseAddress>0xFFFFFA00</baseAddress>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x04</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control and data register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TRNG_CTRL_DATA</name>
|
|
<bitRange>[7:0]</bitRange>
|
|
<access>read-only</access>
|
|
<description>Random data</description>
|
|
</field>
|
|
<field>
|
|
<name>TRNG_CTRL_FIFO</name>
|
|
<bitRange>[19:16]</bitRange>
|
|
<access>read-only</access>
|
|
<description>Log2(FIFO size)</description>
|
|
</field>
|
|
<field>
|
|
<name>TRNG_CTRL_IRQ_FIFO_NEMPTY</name>
|
|
<bitRange>[25:25]</bitRange>
|
|
<description>IRQ if FIFO is not empty</description>
|
|
</field>
|
|
<field>
|
|
<name>TRNG_CTRL_IRQ_FIFO_HALF</name>
|
|
<bitRange>[26:26]</bitRange>
|
|
<description>IRQ if FIFO is at least half full</description>
|
|
</field>
|
|
<field>
|
|
<name>TRNG_CTRL_IRQ_FIFO_FULL</name>
|
|
<bitRange>[27:27]</bitRange>
|
|
<description>IRQ if FIFO is full</description>
|
|
</field>
|
|
<field>
|
|
<name>TRNG_CTRL_FIFO_CLR</name>
|
|
<bitRange>[28:28]</bitRange>
|
|
<description>Clear data FIFO when set (auto clears)</description>
|
|
</field>
|
|
<field>
|
|
<name>TRNG_CTRL_SIM_MODE</name>
|
|
<bitRange>[29:29]</bitRange>
|
|
<access>read-only</access>
|
|
<description>TRNG simulation mode (PRNG!) active</description>
|
|
</field>
|
|
<field>
|
|
<name>TRNG_CTRL_EN</name>
|
|
<bitRange>[30:30]</bitRange>
|
|
<description>TRNG enable flag</description>
|
|
</field>
|
|
<field>
|
|
<name>TRNG_CTRL_VALID</name>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-only</access>
|
|
<description>Random data output valid</description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<!-- WDT ------------------------------------------------------------------------------------->
|
|
<!-------------------------------------------------------------------------------------------->
|
|
<peripheral>
|
|
<name>WDT</name>
|
|
<description>Watchdog timer</description>
|
|
<groupName>WDT</groupName>
|
|
<baseAddress>0xFFFFFB00</baseAddress>
|
|
|
|
<interrupt><name>WDT_FIRQ</name><value>0</value></interrupt>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x08</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>WDT_CTRL_EN</name>
|
|
<bitRange>[0:0]</bitRange>
|
|
<description>WDT enable flag</description>
|
|
</field>
|
|
<field>
|
|
<name>WDT_CTRL_LOCK</name>
|
|
<bitRange>[1:1]</bitRange>
|
|
<description>Lock write access to control register, clears on reset (HW or WDT) only</description>
|
|
</field>
|
|
<field>
|
|
<name>WDT_CTRL_DBEN</name>
|
|
<bitRange>[2:2]</bitRange>
|
|
<description>Allow WDT to continue operation even when in debug mode</description>
|
|
</field>
|
|
<field>
|
|
<name>WDT_CTRL_SEN</name>
|
|
<bitRange>[3:3]</bitRange>
|
|
<description>Allow WDT to continue operation even when in sleep mode</description>
|
|
</field>
|
|
<field>
|
|
<name>WDT_CTRL_STRICT</name>
|
|
<bitRange>[4:4]</bitRange>
|
|
<description>Force hardware reset if reset password is incorrect or if write attempt to locked CTRL register</description>
|
|
</field>
|
|
<field>
|
|
<name>WDT_CTRL_RCAUSE</name>
|
|
<bitRange>[6:5]</bitRange>
|
|
<access>read-only</access>
|
|
<description>Cause of last system reset: 0=external reset, 1=OCD reset, 2=WDT reset</description>
|
|
</field>
|
|
<field>
|
|
<name>WDT_CTRL_TIMEOUT</name>
|
|
<bitRange>[31:8]</bitRange>
|
|
<description>Timeout value</description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>RESET</name>
|
|
<description>Watchdog reset register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>WDT_RESET</name>
|
|
<bitRange>[31:0]</bitRange>
|
|
<description>Write password to reset/feed the watchdog (0x709D1AB3)</description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<!-- GPIO ------------------------------------------------------------------------------------->
|
|
<!-------------------------------------------------------------------------------------------->
|
|
<peripheral>
|
|
<name>GPIO</name>
|
|
<description>General purpose input/output port</description>
|
|
<groupName>GPIO</groupName>
|
|
<baseAddress>0xFFFFFC00</baseAddress>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>INPUT_LO</name>
|
|
<description>Parallel input register - low</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<access>read-only</access>
|
|
</register>
|
|
<register>
|
|
<name>INPUT_HI</name>
|
|
<description>Parallel input register - high</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<access>read-only</access>
|
|
</register>
|
|
<register>
|
|
<name>OUTPUT_LO</name>
|
|
<description>Parallel output register - low</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>OUTPUT_HI</name>
|
|
<description>Parallel output register - high</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<!-- NEOLED ---------------------------------------------------------------------------------->
|
|
<!-------------------------------------------------------------------------------------------->
|
|
<peripheral>
|
|
<name>NEOLED</name>
|
|
<description>Smart LED hardware interface</description>
|
|
<groupName>NEOLED</groupName>
|
|
<baseAddress>0xFFFFFD00</baseAddress>
|
|
|
|
<interrupt><name>NEOLED_FIRQ</name><value>9</value></interrupt>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x08</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NEOLED_CTRL_EN</name>
|
|
<bitRange>[0:0]</bitRange>
|
|
<description>NEOLED enable flag</description>
|
|
</field>
|
|
<field>
|
|
<name>NEOLED_CTRL_MODE</name>
|
|
<bitRange>[1:1]</bitRange>
|
|
<description>TX mode (0=24-bit, 1=32-bit)</description>
|
|
</field>
|
|
<field>
|
|
<name>NEOLED_CTRL_STROBE</name>
|
|
<bitRange>[2:2]</bitRange>
|
|
<description>Strobe (0=send normal data, 1=send RESET command on data write)</description>
|
|
</field>
|
|
<field>
|
|
<name>NEOLED_CTRL_PRSC</name>
|
|
<bitRange>[5:3]</bitRange>
|
|
<description>Clock prescaler select</description>
|
|
</field>
|
|
<field>
|
|
<name>NEOLED_CTRL_BUFS</name>
|
|
<bitRange>[9:6]</bitRange>
|
|
<access>read-only</access>
|
|
<description>log2(tx buffer size)</description>
|
|
</field>
|
|
<field>
|
|
<name>NEOLED_CTRL_T_TOT</name>
|
|
<bitRange>[14:10]</bitRange>
|
|
<description>pulse-clock ticks per total period bit</description>
|
|
</field>
|
|
<field>
|
|
<name>NEOLED_CTRL_T_ZERO_H</name>
|
|
<bitRange>[19:15]</bitRange>
|
|
<description>pulse-clock ticks per ZERO high-time</description>
|
|
</field>
|
|
<field>
|
|
<name>NEOLED_CTRL_T_ONE_H</name>
|
|
<bitRange>[24:20]</bitRange>
|
|
<description>pulse-clock ticks per ONE high-time</description>
|
|
</field>
|
|
<field>
|
|
<name>NEOLED_CTRL_IRQ_CONF</name>
|
|
<bitRange>[27:27]</bitRange>
|
|
<description>TX FIFO interrupt: 0=IRQ if FIFO is less than half-full, 1=IRQ if FIFO is empty</description>
|
|
</field>
|
|
<field>
|
|
<name>NEOLED_CTRL_TX_EMPTY</name>
|
|
<bitRange>[28:28]</bitRange>
|
|
<access>read-only</access>
|
|
<description>TX FIFO is empty</description>
|
|
</field>
|
|
<field>
|
|
<name>NEOLED_CTRL_TX_HALF</name>
|
|
<bitRange>[29:29]</bitRange>
|
|
<access>read-only</access>
|
|
<description>TX FIFO is at least half-full</description>
|
|
</field>
|
|
<field>
|
|
<name>NEOLED_CTRL_TX_FULL</name>
|
|
<bitRange>[30:30]</bitRange>
|
|
<access>read-only</access>
|
|
<description>TX FIFO is full</description>
|
|
</field>
|
|
<field>
|
|
<name>NEOLED_CTRL_TX_BUSY</name>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-only</access>
|
|
<description>busy flag</description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>Data register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<!-- SYSINFO --------------------------------------------------------------------------------->
|
|
<!-------------------------------------------------------------------------------------------->
|
|
<peripheral>
|
|
<name>SYSINFO</name>
|
|
<description>System configuration information memory</description>
|
|
<groupName>SYSINFO</groupName>
|
|
<baseAddress>0xFFFFFE00</baseAddress>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>CLK</name>
|
|
<description>Clock speed in Hz</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<access>read-only</access>
|
|
</register>
|
|
<register>
|
|
<name>MEM</name>
|
|
<description>Memory configuration (sizes)</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field><name>SYSINFO_MEM_0</name><bitRange>[7:0]</bitRange><description>log2(IMEM size in bytes)</description></field>
|
|
<field><name>SYSINFO_MEM_1</name><bitRange>[15:8]</bitRange><description>log2(DMEM size in bytes)</description></field>
|
|
<field><name>SYSINFO_MEM_2</name><bitRange>[23:16]</bitRange><description>reserved</description></field>
|
|
<field><name>SYSINFO_MEM_3</name><bitRange>[31:24]</bitRange><description>log2(reservation set granulartiy in bytes)</description></field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOC</name>
|
|
<description>SoC configuration</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field><name>SYSINFO_SOC_BOOTLOADER</name><bitRange>[0:0]</bitRange><description>Bootloader implemented</description></field>
|
|
<field><name>SYSINFO_SOC_MEM_EXT</name><bitRange>[1:1]</bitRange><description>External bus interface implemented</description></field>
|
|
<field><name>SYSINFO_SOC_MEM_INT_IMEM</name><bitRange>[2:2]</bitRange><description>Processor-internal instruction memory implemented</description></field>
|
|
<field><name>SYSINFO_SOC_MEM_INT_DMEM</name><bitRange>[3:3]</bitRange><description>Processor-internal data memory implemented</description></field>
|
|
<field><name>SYSINFO_SOC_MEM_EXT_ENDIAN</name><bitRange>[4:4]</bitRange><description>External bus interface uses BIG-endian byte-order</description></field>
|
|
<field><name>SYSINFO_SOC_ICACHE</name><bitRange>[5:5]</bitRange><description>Processor-internal instruction cache implemented</description></field>
|
|
<field><name>SYSINFO_SOC_DCACHE</name><bitRange>[6:6]</bitRange><description>Processor-internal data cache implemented</description></field>
|
|
<field><name>SYSINFO_SOC_CLOCK_GATING</name><bitRange>[7:7]</bitRange><description>Clock gating implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IO_CRC</name><bitRange>[12:12]</bitRange><description>Cyclic redundancy check unit implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IO_SLINK</name><bitRange>[13:13]</bitRange><description>Stream link interface implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IO_DMA</name><bitRange>[14:14]</bitRange><description>Direct memory access controller implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IO_GPIO</name><bitRange>[15:15]</bitRange><description>General purpose input/output port unit implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IO_MTIME</name><bitRange>[16:16]</bitRange><description>Machine system timer implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IO_UART0</name><bitRange>[17:17]</bitRange><description>Primary universal asynchronous receiver/transmitter 0 implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IO_SPI</name><bitRange>[18:18]</bitRange><description>Serial peripheral interface implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IO_TWI</name><bitRange>[19:19]</bitRange><description>Two-wire interface implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IO_PWM</name><bitRange>[20:20]</bitRange><description>Pulse-width modulation unit implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IO_WDT</name><bitRange>[21:21]</bitRange><description>Watchdog timer implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IO_CFS</name><bitRange>[22:22]</bitRange><description>Custom functions subsystem implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IO_TRNG</name><bitRange>[23:23]</bitRange><description>True random number generator implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IO_SDI</name><bitRange>[24:24]</bitRange><description>Serial data interface implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IO_UART1</name><bitRange>[25:25]</bitRange><description>Secondary universal asynchronous receiver/transmitter 1 implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IO_NEOLED</name><bitRange>[26:26]</bitRange><description>NeoPixel-compatible smart LED interface implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IO_XIRQ</name><bitRange>[27:27]</bitRange><description>External interrupt controller implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IO_GPTMR</name><bitRange>[28:28]</bitRange><description>General purpose timer implemented</description></field>
|
|
<field><name>SYSINFO_SOC_XIP</name><bitRange>[29:29]</bitRange><description>Execute in place module implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IO_ONEWIRE</name><bitRange>[30:30]</bitRange><description>1-wire interface controller implemented</description></field>
|
|
<field><name>SYSINFO_SOC_OCD</name><bitRange>[31:31]</bitRange><description>On-chip debugger implemented</description></field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CACHE</name>
|
|
<description>Cache configuration</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field><name>SYSINFO_CACHE_IC_BLOCK_SIZE</name><bitRange>[3:0]</bitRange><description>i-cache: log2(Block size in bytes)</description></field>
|
|
<field><name>SYSINFO_CACHE_IC_NUM_BLOCKS</name><bitRange>[7:4]</bitRange><description>i-cache: log2(Number of cache blocks/pages/lines)</description></field>
|
|
<field><name>SYSINFO_CACHE_IC_ASSOCIATIVITY</name><bitRange>[11:8]</bitRange><description>i-cache: log2(associativity)</description></field>
|
|
<field><name>SYSINFO_CACHE_IC_REPLACEMENT</name><bitRange>[15:12]</bitRange><description>i-cache: replacement policy (0001 = LRU if associativity > 0)</description></field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
</peripherals>
|
|
</device>
|