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PYNQ-Z2_demos/hdmi-out-test/hdmi-out-test.xpr

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added hdmi-out demo
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2021.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="56" Path="/home/neyko/DEV/git/PYNQ-Z2_demos/hdmi-out-test/hdmi-out-test.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
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<Option Name="Id" Val="d6151e6a6d144952893a332e45aaf36e"/>
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<Option Name="Part" Val="xc7z020clg400-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="SimulatorInstallDirModelSim" Val=""/>
<Option Name="SimulatorInstallDirQuesta" Val=""/>
<Option Name="SimulatorInstallDirXcelium" Val=""/>
<Option Name="SimulatorInstallDirVCS" Val=""/>
<Option Name="SimulatorInstallDirRiviera" Val=""/>
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorVersionXsim" Val="2021.2"/>
<Option Name="SimulatorVersionModelSim" Val="2020.4"/>
<Option Name="SimulatorVersionQuesta" Val="2020.4"/>
<Option Name="SimulatorVersionXcelium" Val="20.09.006"/>
<Option Name="SimulatorVersionVCS" Val="R-2020.12"/>
<Option Name="SimulatorVersionRiviera" Val="2020.10"/>
<Option Name="SimulatorVersionActiveHdl" Val="12.0"/>
<Option Name="SimulatorGccVersionXsim" Val="6.2.0"/>
<Option Name="SimulatorGccVersionModelSim" Val="5.3.0"/>
<Option Name="SimulatorGccVersionQuesta" Val="5.3.0"/>
<Option Name="SimulatorGccVersionXcelium" Val="6.3"/>
<Option Name="SimulatorGccVersionVCS" Val="6.2.0"/>
<Option Name="SimulatorGccVersionRiviera" Val="6.2.0"/>
<Option Name="SimulatorGccVersionActiveHdl" Val="6.2.0"/>
<Option Name="BoardPart" Val="tul.com.tw:pynq-z2:part0:1.0"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPRepoPath" Val="$PPRDIR/digilent.ipdefs"/>
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<Option Name="IPRepoPath" Val="$PPRDIR/hdmi-out-test.ipdefs"/>
added hdmi-out demo
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<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="pynq-z2"/>
hdmi-out-test: bd based -> hdl based changed hdmi-out-test to hdl based using projectF dvi output instead of digilent ip cores seems simpler to understand and use
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<Option Name="WTXSimLaunchSim" Val="58"/>
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<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="2"/>
<Option Name="WTModelSimExportSim" Val="2"/>
<Option Name="WTQuestaExportSim" Val="2"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="2"/>
<Option Name="WTRivieraExportSim" Val="2"/>
<Option Name="WTActivehdlExportSim" Val="2"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
<Option Name="DcpsUptoDate" Val="TRUE"/>
<Option Name="ClassicSocBoot" Val="FALSE"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
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<File Path="$PSRCDIR/sources_1/bd/blinki_bd/blinki_bd.bd">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../hdmi-thru/hdmi-thru.srcs/sources_1/bd/blinki_bd/blinki_bd.bd"/>
<Attr Name="ImportTime" Val="1723725422"/>
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<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
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<CompFileExtendedInfo CompFileName="blinki_bd.bd" FileRelPathName="ip/blinki_bd_axi_gpio_0_0/blinki_bd_axi_gpio_0_0.xci">
<Proxy FileSetName="blinki_bd_axi_gpio_0_0"/>
added hdmi-out demo
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</CompFileExtendedInfo>
hdmi-out-test: bd based -> hdl based changed hdmi-out-test to hdl based using projectF dvi output instead of digilent ip cores seems simpler to understand and use
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<CompFileExtendedInfo CompFileName="blinki_bd.bd" FileRelPathName="ip/blinki_bd_rst_ps7_0_100M_0/blinki_bd_rst_ps7_0_100M_0.xci">
<Proxy FileSetName="blinki_bd_rst_ps7_0_100M_0"/>
added hdmi-out demo
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</CompFileExtendedInfo>
</File>
hdmi-out-test: bd based -> hdl based changed hdmi-out-test to hdl based using projectF dvi output instead of digilent ip cores seems simpler to understand and use
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<File Path="$PPRDIR/v/async_reset.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PGENDIR/sources_1/bd/blinki_bd/hdl/blinki_bd_wrapper.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/v/display_clocks.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/v/display_demo_dvi.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/v/display_timings.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/v/dvi_generator.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/v/serializer_10to1.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/v/test_card_simple.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/v/tmds_encoder_dvi.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/v/dvi_top.v">
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<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
hdmi-out-test: bd based -> hdl based changed hdmi-out-test to hdl based using projectF dvi output instead of digilent ip cores seems simpler to understand and use
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<Option Name="TopModule" Val="dvi_top"/>
added hdmi-out demo
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</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PPRDIR/xdc/pynqz2.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
hdmi-out-test: bd based -> hdl based changed hdmi-out-test to hdl based using projectF dvi output instead of digilent ip cores seems simpler to understand and use
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<File Path="$PPRDIR/xdc/timing.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
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<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
hdmi-out-test: bd based -> hdl based changed hdmi-out-test to hdl based using projectF dvi output instead of digilent ip cores seems simpler to understand and use
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<Option Name="TopModule" Val="dvi_top"/>
added hdmi-out demo
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<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SelectedSimModel" Val="rtl"/>
<Option Name="PamDesignTestbench" Val=""/>
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<File Path="$PSRCDIR/utils_1/imports/synth_1/design_1_wrapper.dcp">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedInSteps" Val="synth_1"/>
<Attr Name="AutoDcp" Val="1"/>
</FileInfo>
</File>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
hdmi-out-test: bd based -> hdl based changed hdmi-out-test to hdl based using projectF dvi output instead of digilent ip cores seems simpler to understand and use
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<FileSet Name="blinki_bd_axi_gpio_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/blinki_bd_axi_gpio_0_0" RelGenDir="$PGENDIR/blinki_bd_axi_gpio_0_0">
added hdmi-out demo
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<Config>
hdmi-out-test: bd based -> hdl based changed hdmi-out-test to hdl based using projectF dvi output instead of digilent ip cores seems simpler to understand and use
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<Option Name="TopModule" Val="blinki_bd_axi_gpio_0_0"/>
added hdmi-out demo
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<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
hdmi-out-test: bd based -> hdl based changed hdmi-out-test to hdl based using projectF dvi output instead of digilent ip cores seems simpler to understand and use
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<FileSet Name="blinki_bd_rst_ps7_0_100M_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/blinki_bd_rst_ps7_0_100M_0" RelGenDir="$PGENDIR/blinki_bd_rst_ps7_0_100M_0">
added hdmi-out demo
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<Config>
hdmi-out-test: bd based -> hdl based changed hdmi-out-test to hdl based using projectF dvi output instead of digilent ip cores seems simpler to understand and use
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<Option Name="TopModule" Val="blinki_bd_rst_ps7_0_100M_0"/>
added hdmi-out demo
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<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Xcelium">
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="15">
hdmi-out-test: bd based -> hdl based changed hdmi-out-test to hdl based using projectF dvi output instead of digilent ip cores seems simpler to understand and use
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<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/design_1_wrapper.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
added hdmi-out demo
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<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2021"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
hdmi-out-test: bd based -> hdl based changed hdmi-out-test to hdl based using projectF dvi output instead of digilent ip cores seems simpler to understand and use
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<Run Id="synth_2" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" Dir="$PRUNDIR/synth_2" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_2">
added hdmi-out demo
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<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/>
<Step Id="synth_design"/>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2021"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
hdmi-out-test: bd based -> hdl based changed hdmi-out-test to hdl based using projectF dvi output instead of digilent ip cores seems simpler to understand and use
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<Run Id="blinki_bd_axi_gpio_0_0_synth_1" Type="Ft3:Synth" SrcSet="blinki_bd_axi_gpio_0_0" Part="xc7z020clg400-1" ConstrsSet="blinki_bd_axi_gpio_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/blinki_bd_axi_gpio_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/blinki_bd_axi_gpio_0_0_synth_1">
added hdmi-out demo
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<Strategy Version="1" Minor="2">
hdmi-out-test: bd based -> hdl based changed hdmi-out-test to hdl based using projectF dvi output instead of digilent ip cores seems simpler to understand and use
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
added hdmi-out demo
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<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2021"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
hdmi-out-test: bd based -> hdl based changed hdmi-out-test to hdl based using projectF dvi output instead of digilent ip cores seems simpler to understand and use
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<Run Id="blinki_bd_rst_ps7_0_100M_0_synth_1" Type="Ft3:Synth" SrcSet="blinki_bd_rst_ps7_0_100M_0" Part="xc7z020clg400-1" ConstrsSet="blinki_bd_rst_ps7_0_100M_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/blinki_bd_rst_ps7_0_100M_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/blinki_bd_rst_ps7_0_100M_0_synth_1">
added hdmi-out demo
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<Strategy Version="1" Minor="2">
hdmi-out-test: bd based -> hdl based changed hdmi-out-test to hdl based using projectF dvi output instead of digilent ip cores seems simpler to understand and use
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
added hdmi-out demo
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<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2021"/>
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<RQSFiles/>
</Run>
hdmi-out-test: bd based -> hdl based changed hdmi-out-test to hdl based using projectF dvi output instead of digilent ip cores seems simpler to understand and use
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<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../hdmi-thru/hdmi-thru.srcs/utils_1/imports/impl_1">
added hdmi-out demo
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<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/>
<Step Id="init_design"/>
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<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2021"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
hdmi-out-test: bd based -> hdl based changed hdmi-out-test to hdl based using projectF dvi output instead of digilent ip cores seems simpler to understand and use
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<Run Id="impl_2" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/impl_2" SynthRun="synth_2" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../hdmi-thru/hdmi-thru.srcs/utils_1/imports/impl_2">
added hdmi-out demo
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<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
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<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2021"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
hdmi-out-test: bd based -> hdl based changed hdmi-out-test to hdl based using projectF dvi output instead of digilent ip cores seems simpler to understand and use
2024-08-16 12:59:34 +00:00
<Run Id="blinki_bd_axi_gpio_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="blinki_bd_axi_gpio_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="blinki_bd_axi_gpio_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/blinki_bd_axi_gpio_0_0_impl_1">
added hdmi-out demo
2024-04-24 01:27:46 +00:00
<Strategy Version="1" Minor="2">
hdmi-out-test: bd based -> hdl based changed hdmi-out-test to hdl based using projectF dvi output instead of digilent ip cores seems simpler to understand and use
2024-08-16 12:59:34 +00:00
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
added hdmi-out demo
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<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2021"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
hdmi-out-test: bd based -> hdl based changed hdmi-out-test to hdl based using projectF dvi output instead of digilent ip cores seems simpler to understand and use
2024-08-16 12:59:34 +00:00
<Run Id="blinki_bd_rst_ps7_0_100M_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="blinki_bd_rst_ps7_0_100M_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="blinki_bd_rst_ps7_0_100M_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/blinki_bd_rst_ps7_0_100M_0_impl_1">
added hdmi-out demo
2024-04-24 01:27:46 +00:00
<Strategy Version="1" Minor="2">
hdmi-out-test: bd based -> hdl based changed hdmi-out-test to hdl based using projectF dvi output instead of digilent ip cores seems simpler to understand and use
2024-08-16 12:59:34 +00:00
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
added hdmi-out demo
2024-04-24 01:27:46 +00:00
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2021"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
<Board>
<Jumpers/>
</Board>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
hdmi-out-test: bd based -> hdl based changed hdmi-out-test to hdl based using projectF dvi output instead of digilent ip cores seems simpler to understand and use
2024-08-16 12:59:34 +00:00
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
added hdmi-out demo
2024-04-24 01:27:46 +00:00
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
hdmi-out-test: bd based -> hdl based changed hdmi-out-test to hdl based using projectF dvi output instead of digilent ip cores seems simpler to understand and use
2024-08-16 12:59:34 +00:00
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
added hdmi-out demo
2024-04-24 01:27:46 +00:00
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
hdmi-out-test: bd based -> hdl based changed hdmi-out-test to hdl based using projectF dvi output instead of digilent ip cores seems simpler to understand and use
2024-08-16 12:59:34 +00:00
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
added hdmi-out demo
2024-04-24 01:27:46 +00:00
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>