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PYNQ-Z2_demos/hdmi-thru/hdmi-thru.xpr

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added hdmi-thru (without buffering) basically connected HDMI_IN -> dvi2rgb -> rgb_op0 -> rgb2dvi -> HDMI_OUT rgb_op0 operation: SW0[0] | Description 0 | Normal color 1 | inverted color can get image correctly from my laptop This demo only needs the FPGA bit file to run (no need for vitis apparently)
2024-05-20 07:40:30 +00:00
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2021.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="56" Path="/home/neyko/DEV/git/PYNQ-Z2_demos/hdmi-thru/hdmi-thru.xpr">
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hdmi-thru geneal cleanup commented out all unnecessary zynq code cleaned rgb_opmodule, and added counters to verify active,hsync,vsync for some reason, vsync lasts only 5 lines. i suspect this is wrong, but since dvi2rgb and rgb2dvi probably use the same convention, hdmi thru is possible however i find it confusing. so, maybe i will focus on dvi2rgb only. Starting with simulation
2024-08-08 08:38:04 +00:00
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added hdmi-thru (without buffering) basically connected HDMI_IN -> dvi2rgb -> rgb_op0 -> rgb2dvi -> HDMI_OUT rgb_op0 operation: SW0[0] | Description 0 | Normal color 1 | inverted color can get image correctly from my laptop This demo only needs the FPGA bit file to run (no need for vitis apparently)
2024-05-20 07:40:30 +00:00
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hdmi-thru geneal cleanup commented out all unnecessary zynq code cleaned rgb_opmodule, and added counters to verify active,hsync,vsync for some reason, vsync lasts only 5 lines. i suspect this is wrong, but since dvi2rgb and rgb2dvi probably use the same convention, hdmi thru is possible however i find it confusing. so, maybe i will focus on dvi2rgb only. Starting with simulation
2024-08-08 08:38:04 +00:00
<Option Name="WTXSimExportSim" Val="1"/>
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added hdmi-thru (without buffering) basically connected HDMI_IN -> dvi2rgb -> rgb_op0 -> rgb2dvi -> HDMI_OUT rgb_op0 operation: SW0[0] | Description 0 | Normal color 1 | inverted color can get image correctly from my laptop This demo only needs the FPGA bit file to run (no need for vitis apparently)
2024-05-20 07:40:30 +00:00
<Option Name="WTIesExportSim" Val="0"/>
hdmi-thru geneal cleanup commented out all unnecessary zynq code cleaned rgb_opmodule, and added counters to verify active,hsync,vsync for some reason, vsync lasts only 5 lines. i suspect this is wrong, but since dvi2rgb and rgb2dvi probably use the same convention, hdmi thru is possible however i find it confusing. so, maybe i will focus on dvi2rgb only. Starting with simulation
2024-08-08 08:38:04 +00:00
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added hdmi-thru (without buffering) basically connected HDMI_IN -> dvi2rgb -> rgb_op0 -> rgb2dvi -> HDMI_OUT rgb_op0 operation: SW0[0] | Description 0 | Normal color 1 | inverted color can get image correctly from my laptop This demo only needs the FPGA bit file to run (no need for vitis apparently)
2024-05-20 07:40:30 +00:00
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hdmi-thru geneal cleanup commented out all unnecessary zynq code cleaned rgb_opmodule, and added counters to verify active,hsync,vsync for some reason, vsync lasts only 5 lines. i suspect this is wrong, but since dvi2rgb and rgb2dvi probably use the same convention, hdmi thru is possible however i find it confusing. so, maybe i will focus on dvi2rgb only. Starting with simulation
2024-08-08 08:38:04 +00:00
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added hdmi-thru (without buffering) basically connected HDMI_IN -> dvi2rgb -> rgb_op0 -> rgb2dvi -> HDMI_OUT rgb_op0 operation: SW0[0] | Description 0 | Normal color 1 | inverted color can get image correctly from my laptop This demo only needs the FPGA bit file to run (no need for vitis apparently)
2024-05-20 07:40:30 +00:00
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_dvi2rgb_0_0/design_1_dvi2rgb_0_0.xci">
<Proxy FileSetName="design_1_dvi2rgb_0_0"/>
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improved hpd added hpd fsm. not sure if compliant with the standard. hdmi_in is the only allowed to srst the fsm. on lock loss (e.g. resolution change) hdmi_out is checked only after hdmi_in is locked, just once so, if hdmi_out is disconnected, design will continue tx design requires both FPGA .bit and PS7 .elf, to work correctly previous commit needs both FPGA and PS7 as well.
2024-05-24 09:11:21 +00:00
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<Proxy FileSetName="design_1_rgb2dvi_0_0"/>
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added hdmi-thru (without buffering) basically connected HDMI_IN -> dvi2rgb -> rgb_op0 -> rgb2dvi -> HDMI_OUT rgb_op0 operation: SW0[0] | Description 0 | Normal color 1 | inverted color can get image correctly from my laptop This demo only needs the FPGA bit file to run (no need for vitis apparently)
2024-05-20 07:40:30 +00:00
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_rgb_op0_0_0/design_1_rgb_op0_0_0.xci">
<Proxy FileSetName="design_1_rgb_op0_0_0"/>
</CompFileExtendedInfo>
hdmi-thru geneal cleanup commented out all unnecessary zynq code cleaned rgb_opmodule, and added counters to verify active,hsync,vsync for some reason, vsync lasts only 5 lines. i suspect this is wrong, but since dvi2rgb and rgb2dvi probably use the same convention, hdmi thru is possible however i find it confusing. so, maybe i will focus on dvi2rgb only. Starting with simulation
2024-08-08 08:38:04 +00:00
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<Proxy FileSetName="design_1_system_ila_0_0"/>
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added hdmi-thru (without buffering) basically connected HDMI_IN -> dvi2rgb -> rgb_op0 -> rgb2dvi -> HDMI_OUT rgb_op0 operation: SW0[0] | Description 0 | Normal color 1 | inverted color can get image correctly from my laptop This demo only needs the FPGA bit file to run (no need for vitis apparently)
2024-05-20 07:40:30 +00:00
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hdmi-thru geneal cleanup commented out all unnecessary zynq code cleaned rgb_opmodule, and added counters to verify active,hsync,vsync for some reason, vsync lasts only 5 lines. i suspect this is wrong, but since dvi2rgb and rgb2dvi probably use the same convention, hdmi thru is possible however i find it confusing. so, maybe i will focus on dvi2rgb only. Starting with simulation
2024-08-08 08:38:04 +00:00
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added hdmi-thru (without buffering) basically connected HDMI_IN -> dvi2rgb -> rgb_op0 -> rgb2dvi -> HDMI_OUT rgb_op0 operation: SW0[0] | Description 0 | Normal color 1 | inverted color can get image correctly from my laptop This demo only needs the FPGA bit file to run (no need for vitis apparently)
2024-05-20 07:40:30 +00:00
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hdmi-thru geneal cleanup commented out all unnecessary zynq code cleaned rgb_opmodule, and added counters to verify active,hsync,vsync for some reason, vsync lasts only 5 lines. i suspect this is wrong, but since dvi2rgb and rgb2dvi probably use the same convention, hdmi thru is possible however i find it confusing. so, maybe i will focus on dvi2rgb only. Starting with simulation
2024-08-08 08:38:04 +00:00
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added hdmi-thru (without buffering) basically connected HDMI_IN -> dvi2rgb -> rgb_op0 -> rgb2dvi -> HDMI_OUT rgb_op0 operation: SW0[0] | Description 0 | Normal color 1 | inverted color can get image correctly from my laptop This demo only needs the FPGA bit file to run (no need for vitis apparently)
2024-05-20 07:40:30 +00:00
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hdmi-thru geneal cleanup commented out all unnecessary zynq code cleaned rgb_opmodule, and added counters to verify active,hsync,vsync for some reason, vsync lasts only 5 lines. i suspect this is wrong, but since dvi2rgb and rgb2dvi probably use the same convention, hdmi thru is possible however i find it confusing. so, maybe i will focus on dvi2rgb only. Starting with simulation
2024-08-08 08:38:04 +00:00
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added hdmi-thru (without buffering) basically connected HDMI_IN -> dvi2rgb -> rgb_op0 -> rgb2dvi -> HDMI_OUT rgb_op0 operation: SW0[0] | Description 0 | Normal color 1 | inverted color can get image correctly from my laptop This demo only needs the FPGA bit file to run (no need for vitis apparently)
2024-05-20 07:40:30 +00:00
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hdmi-thru geneal cleanup commented out all unnecessary zynq code cleaned rgb_opmodule, and added counters to verify active,hsync,vsync for some reason, vsync lasts only 5 lines. i suspect this is wrong, but since dvi2rgb and rgb2dvi probably use the same convention, hdmi thru is possible however i find it confusing. so, maybe i will focus on dvi2rgb only. Starting with simulation
2024-08-08 08:38:04 +00:00
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added hdmi-thru (without buffering) basically connected HDMI_IN -> dvi2rgb -> rgb_op0 -> rgb2dvi -> HDMI_OUT rgb_op0 operation: SW0[0] | Description 0 | Normal color 1 | inverted color can get image correctly from my laptop This demo only needs the FPGA bit file to run (no need for vitis apparently)
2024-05-20 07:40:30 +00:00
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hdmi-thru geneal cleanup commented out all unnecessary zynq code cleaned rgb_opmodule, and added counters to verify active,hsync,vsync for some reason, vsync lasts only 5 lines. i suspect this is wrong, but since dvi2rgb and rgb2dvi probably use the same convention, hdmi thru is possible however i find it confusing. so, maybe i will focus on dvi2rgb only. Starting with simulation
2024-08-08 08:38:04 +00:00
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added hdmi-thru (without buffering) basically connected HDMI_IN -> dvi2rgb -> rgb_op0 -> rgb2dvi -> HDMI_OUT rgb_op0 operation: SW0[0] | Description 0 | Normal color 1 | inverted color can get image correctly from my laptop This demo only needs the FPGA bit file to run (no need for vitis apparently)
2024-05-20 07:40:30 +00:00
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hdmi-thru geneal cleanup commented out all unnecessary zynq code cleaned rgb_opmodule, and added counters to verify active,hsync,vsync for some reason, vsync lasts only 5 lines. i suspect this is wrong, but since dvi2rgb and rgb2dvi probably use the same convention, hdmi thru is possible however i find it confusing. so, maybe i will focus on dvi2rgb only. Starting with simulation
2024-08-08 08:38:04 +00:00
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added hdmi-thru (without buffering) basically connected HDMI_IN -> dvi2rgb -> rgb_op0 -> rgb2dvi -> HDMI_OUT rgb_op0 operation: SW0[0] | Description 0 | Normal color 1 | inverted color can get image correctly from my laptop This demo only needs the FPGA bit file to run (no need for vitis apparently)
2024-05-20 07:40:30 +00:00
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
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