hdmi-thru-test: rebased from hdmi-out-test
discarded old version (bd based). worked but difficult to reusemaster
parent
75d0481279
commit
39ceebf074
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@ -3,10 +3,10 @@
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<!-- -->
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<!-- -->
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||||||
<!-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. -->
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<!-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. -->
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<Project Version="7" Minor="56" Path="/home/neyko/DEV/git/PYNQ-Z2_demos/hdmi-thru/hdmi-thru.xpr">
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<Project Version="7" Minor="56" Path="/home/neyko/DEV/git/PYNQ-Z2_demos/hdmi-thru-test/hdmi-thru-test.xpr">
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||||||
<DefaultLaunch Dir="$PRUNDIR"/>
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<DefaultLaunch Dir="$PRUNDIR"/>
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||||||
<Configuration>
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<Configuration>
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||||||
<Option Name="Id" Val="612fcba52a1e45ada3aa1dfa400a32df"/>
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<Option Name="Id" Val="8c381d892ab54e20ad9532ef61549cdb"/>
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||||||
<Option Name="Part" Val="xc7z020clg400-1"/>
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<Option Name="Part" Val="xc7z020clg400-1"/>
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||||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
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<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
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||||||
<Option Name="CompiledLibDirXSim" Val=""/>
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<Option Name="CompiledLibDirXSim" Val=""/>
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@ -58,20 +58,20 @@
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<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
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<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
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||||||
<Option Name="EnableBDX" Val="FALSE"/>
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<Option Name="EnableBDX" Val="FALSE"/>
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||||||
<Option Name="DSABoardId" Val="pynq-z2"/>
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<Option Name="DSABoardId" Val="pynq-z2"/>
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||||||
<Option Name="WTXSimLaunchSim" Val="2"/>
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<Option Name="WTXSimLaunchSim" Val="58"/>
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||||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
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<Option Name="WTModelSimLaunchSim" Val="0"/>
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||||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
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<Option Name="WTQuestaLaunchSim" Val="0"/>
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||||||
<Option Name="WTIesLaunchSim" Val="0"/>
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<Option Name="WTIesLaunchSim" Val="0"/>
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||||||
<Option Name="WTVcsLaunchSim" Val="0"/>
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<Option Name="WTVcsLaunchSim" Val="0"/>
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||||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
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<Option Name="WTRivieraLaunchSim" Val="0"/>
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||||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
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<Option Name="WTActivehdlLaunchSim" Val="0"/>
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||||||
<Option Name="WTXSimExportSim" Val="1"/>
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<Option Name="WTXSimExportSim" Val="2"/>
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||||||
<Option Name="WTModelSimExportSim" Val="1"/>
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<Option Name="WTModelSimExportSim" Val="2"/>
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||||||
<Option Name="WTQuestaExportSim" Val="1"/>
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<Option Name="WTQuestaExportSim" Val="2"/>
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||||||
<Option Name="WTIesExportSim" Val="0"/>
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<Option Name="WTIesExportSim" Val="0"/>
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<Option Name="WTVcsExportSim" Val="1"/>
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<Option Name="WTVcsExportSim" Val="2"/>
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<Option Name="WTRivieraExportSim" Val="1"/>
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<Option Name="WTRivieraExportSim" Val="2"/>
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||||||
<Option Name="WTActivehdlExportSim" Val="1"/>
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<Option Name="WTActivehdlExportSim" Val="2"/>
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||||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
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<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
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<Option Name="XSimRadix" Val="hex"/>
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<Option Name="XSimRadix" Val="hex"/>
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<Option Name="XSimTimeUnit" Val="ns"/>
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<Option Name="XSimTimeUnit" Val="ns"/>
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@ -88,49 +88,96 @@
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<FileSets Version="1" Minor="31">
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<FileSets Version="1" Minor="31">
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<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
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<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
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<Filter Type="Srcs"/>
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<Filter Type="Srcs"/>
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<File Path="$PPRDIR/v/rgb_op0.v">
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<File Path="$PSRCDIR/sources_1/bd/blinki_bd/blinki_bd.bd">
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<FileInfo>
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../hdmi-thru/hdmi-thru.srcs/sources_1/bd/blinki_bd/blinki_bd.bd"/>
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<Attr Name="ImportTime" Val="1723725422"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</FileInfo>
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</File>
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<CompFileExtendedInfo CompFileName="blinki_bd.bd" FileRelPathName="ip/blinki_bd_axi_gpio_0_0/blinki_bd_axi_gpio_0_0.xci">
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<File Path="$PSRCDIR/sources_1/bd/design_1/design_1.bd">
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<Proxy FileSetName="blinki_bd_axi_gpio_0_0"/>
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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</FileInfo>
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<CompFileExtendedInfo CompFileName="design_1_axi_gpio_0_0.xci" FileRelPathName="/home/neyko/DEV/git/PYNQ-Z2_demos/hdmi-thru/hdmi-thru.gen/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/synth/design_1_axi_gpio_0_0.vhd">
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<Attr Name="UsedInSimulation" Val="1"/>
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</CompFileExtendedInfo>
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</CompFileExtendedInfo>
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<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_xbar_0/design_1_xbar_0.xci">
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<CompFileExtendedInfo CompFileName="blinki_bd.bd" FileRelPathName="ip/blinki_bd_rst_ps7_0_100M_0/blinki_bd_rst_ps7_0_100M_0.xci">
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<Proxy FileSetName="design_1_xbar_0"/>
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<Proxy FileSetName="blinki_bd_rst_ps7_0_100M_0"/>
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</CompFileExtendedInfo>
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<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_dvi2rgb_0_0/design_1_dvi2rgb_0_0.xci">
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<Proxy FileSetName="design_1_dvi2rgb_0_0"/>
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</CompFileExtendedInfo>
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<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_rgb2dvi_0_0/design_1_rgb2dvi_0_0.xci">
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<Proxy FileSetName="design_1_rgb2dvi_0_0"/>
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</CompFileExtendedInfo>
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<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_rgb_op0_0_0/design_1_rgb_op0_0_0.xci">
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<Proxy FileSetName="design_1_rgb_op0_0_0"/>
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</CompFileExtendedInfo>
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<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_xbar_1/design_1_xbar_1.xci">
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<Proxy FileSetName="design_1_xbar_1"/>
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</CompFileExtendedInfo>
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<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_system_ila_0_0/design_1_system_ila_0_0.xci">
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<Proxy FileSetName="design_1_system_ila_0_0"/>
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</CompFileExtendedInfo>
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</CompFileExtendedInfo>
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</File>
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</File>
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<File Path="$PGENDIR/sources_1/bd/design_1/hdl/design_1_wrapper.v">
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<File Path="$PPRDIR/v/async_reset.v">
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<FileInfo>
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/imports/blinki_bd_wrapper.v">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../hdmi-out-test/hdmi-out-test.gen/sources_1/bd/blinki_bd/hdl/blinki_bd_wrapper.v"/>
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<Attr Name="ImportTime" Val="1723727226"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/v/display_clocks.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/v/display_demo_dvi.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/v/display_timings.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/v/dvi_generator.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/v/serializer_10to1.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/v/test_card_simple.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/v/tmds_encoder_dvi.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/v/dvi_top.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</FileInfo>
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</File>
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</File>
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<Config>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="design_1_wrapper"/>
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<Option Name="TopModule" Val="dvi_top"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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</Config>
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</Config>
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</FileSet>
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</FileSet>
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<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
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<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
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@ -155,6 +202,8 @@
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<Filter Type="Srcs"/>
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<Filter Type="Srcs"/>
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<Config>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="dvi_top"/>
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<Option Name="TopLib" Val="xil_defaultlib"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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<Option Name="TransportPathDelay" Val="0"/>
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<Option Name="TransportPathDelay" Val="0"/>
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<Option Name="TransportIntDelay" Val="0"/>
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<Option Name="TransportIntDelay" Val="0"/>
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@ -168,59 +217,19 @@
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</FileSet>
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</FileSet>
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<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
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<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
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<Filter Type="Utils"/>
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<Filter Type="Utils"/>
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<File Path="$PSRCDIR/utils_1/imports/synth_1/design_1_wrapper.dcp">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedInSteps" Val="synth_1"/>
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<Attr Name="AutoDcp" Val="1"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/utils_1/imports/synth_2/design_1_wrapper.dcp">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedInSteps" Val="synth_2"/>
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<Attr Name="AutoDcp" Val="1"/>
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</FileInfo>
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</File>
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<Config>
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<Config>
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<Option Name="TopAutoSet" Val="TRUE"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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</Config>
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</Config>
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</FileSet>
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</FileSet>
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<FileSet Name="design_1_rgb2dvi_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_rgb2dvi_0_0" RelGenDir="$PGENDIR/design_1_rgb2dvi_0_0">
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<FileSet Name="blinki_bd_axi_gpio_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/blinki_bd_axi_gpio_0_0" RelGenDir="$PGENDIR/blinki_bd_axi_gpio_0_0">
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<Config>
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<Config>
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<Option Name="TopModule" Val="design_1_rgb2dvi_0_0"/>
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<Option Name="TopModule" Val="blinki_bd_axi_gpio_0_0"/>
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<Option Name="UseBlackboxStub" Val="1"/>
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<Option Name="UseBlackboxStub" Val="1"/>
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</Config>
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</Config>
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</FileSet>
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</FileSet>
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<FileSet Name="design_1_dvi2rgb_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_dvi2rgb_0_0" RelGenDir="$PGENDIR/design_1_dvi2rgb_0_0">
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<FileSet Name="blinki_bd_rst_ps7_0_100M_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/blinki_bd_rst_ps7_0_100M_0" RelGenDir="$PGENDIR/blinki_bd_rst_ps7_0_100M_0">
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<Config>
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<Config>
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<Option Name="TopModule" Val="design_1_dvi2rgb_0_0"/>
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<Option Name="TopModule" Val="blinki_bd_rst_ps7_0_100M_0"/>
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<Option Name="UseBlackboxStub" Val="1"/>
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</Config>
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</FileSet>
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<FileSet Name="design_1_xbar_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_xbar_0" RelGenDir="$PGENDIR/design_1_xbar_0">
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<Config>
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<Option Name="TopModule" Val="design_1_xbar_0"/>
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<Option Name="UseBlackboxStub" Val="1"/>
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</Config>
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</FileSet>
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<FileSet Name="design_1_xbar_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_xbar_1" RelGenDir="$PGENDIR/design_1_xbar_1">
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<Config>
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<Option Name="TopModule" Val="design_1_xbar_1"/>
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<Option Name="UseBlackboxStub" Val="1"/>
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</Config>
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</FileSet>
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<FileSet Name="design_1_system_ila_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_system_ila_0_0" RelGenDir="$PGENDIR/design_1_system_ila_0_0">
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<Config>
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<Option Name="TopModule" Val="design_1_system_ila_0_0"/>
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<Option Name="UseBlackboxStub" Val="1"/>
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</Config>
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</FileSet>
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<FileSet Name="design_1_rgb_op0_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_rgb_op0_0_0" RelGenDir="$PGENDIR/design_1_rgb_op0_0_0">
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<Config>
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<Option Name="TopModule" Val="design_1_rgb_op0_0_0"/>
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<Option Name="UseBlackboxStub" Val="1"/>
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<Option Name="UseBlackboxStub" Val="1"/>
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</Config>
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</Config>
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</FileSet>
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</FileSet>
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@ -247,7 +256,7 @@
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</Simulator>
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</Simulator>
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</Simulators>
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</Simulators>
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<Runs Version="1" Minor="15">
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<Runs Version="1" Minor="15">
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<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/design_1_wrapper.dcp" WriteIncrSynthDcp="false" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
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<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
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<Strategy Version="1" Minor="2">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/>
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/>
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<Step Id="synth_design"/>
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<Step Id="synth_design"/>
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@ -257,7 +266,16 @@
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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<RQSFiles/>
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</Run>
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</Run>
|
||||||
<Run Id="design_1_rgb2dvi_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_rgb2dvi_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_rgb2dvi_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_rgb2dvi_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_rgb2dvi_0_0_synth_1">
|
<Run Id="synth_2" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PPRDIR/../hdmi-out-test/hdmi-out-test.srcs/utils_1/imports/synth_2">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/>
|
||||||
|
<Step Id="synth_design"/>
|
||||||
|
</Strategy>
|
||||||
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2021"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="blinki_bd_axi_gpio_0_0_synth_1" Type="Ft3:Synth" SrcSet="blinki_bd_axi_gpio_0_0" Part="xc7z020clg400-1" ConstrsSet="blinki_bd_axi_gpio_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/blinki_bd_axi_gpio_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PPRDIR/../hdmi-out-test/hdmi-out-test.srcs/utils_1/imports/blinki_bd_axi_gpio_0_0_synth_1">
|
||||||
<Strategy Version="1" Minor="2">
|
<Strategy Version="1" Minor="2">
|
||||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/>
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/>
|
||||||
<Step Id="synth_design"/>
|
<Step Id="synth_design"/>
|
||||||
|
|
@ -267,7 +285,7 @@
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
<RQSFiles/>
|
<RQSFiles/>
|
||||||
</Run>
|
</Run>
|
||||||
<Run Id="design_1_dvi2rgb_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_dvi2rgb_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_dvi2rgb_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_dvi2rgb_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_dvi2rgb_0_0_synth_1">
|
<Run Id="blinki_bd_rst_ps7_0_100M_0_synth_1" Type="Ft3:Synth" SrcSet="blinki_bd_rst_ps7_0_100M_0" Part="xc7z020clg400-1" ConstrsSet="blinki_bd_rst_ps7_0_100M_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/blinki_bd_rst_ps7_0_100M_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PPRDIR/../hdmi-out-test/hdmi-out-test.srcs/utils_1/imports/blinki_bd_rst_ps7_0_100M_0_synth_1">
|
||||||
<Strategy Version="1" Minor="2">
|
<Strategy Version="1" Minor="2">
|
||||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/>
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/>
|
||||||
<Step Id="synth_design"/>
|
<Step Id="synth_design"/>
|
||||||
|
|
@ -277,59 +295,7 @@
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
<RQSFiles/>
|
<RQSFiles/>
|
||||||
</Run>
|
</Run>
|
||||||
<Run Id="synth_2" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_2/design_1_wrapper.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_2" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_2">
|
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../hdmi-thru/hdmi-thru.srcs/utils_1/imports/impl_1">
|
||||||
<Strategy Version="1" Minor="2">
|
|
||||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/>
|
|
||||||
<Step Id="synth_design"/>
|
|
||||||
</Strategy>
|
|
||||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
||||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2021"/>
|
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
||||||
<RQSFiles/>
|
|
||||||
</Run>
|
|
||||||
<Run Id="design_1_xbar_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_xbar_0" Part="xc7z020clg400-1" ConstrsSet="design_1_xbar_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_xbar_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_xbar_0_synth_1">
|
|
||||||
<Strategy Version="1" Minor="2">
|
|
||||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/>
|
|
||||||
<Step Id="synth_design"/>
|
|
||||||
</Strategy>
|
|
||||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
||||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2021"/>
|
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
||||||
<RQSFiles/>
|
|
||||||
</Run>
|
|
||||||
<Run Id="design_1_xbar_1_synth_1" Type="Ft3:Synth" SrcSet="design_1_xbar_1" Part="xc7z020clg400-1" ConstrsSet="design_1_xbar_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_xbar_1_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_xbar_1_synth_1">
|
|
||||||
<Strategy Version="1" Minor="2">
|
|
||||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/>
|
|
||||||
<Step Id="synth_design"/>
|
|
||||||
</Strategy>
|
|
||||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
||||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2021"/>
|
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
||||||
<RQSFiles/>
|
|
||||||
</Run>
|
|
||||||
<Run Id="design_1_system_ila_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_system_ila_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_system_ila_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_system_ila_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_system_ila_0_0_synth_1">
|
|
||||||
<Strategy Version="1" Minor="2">
|
|
||||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/>
|
|
||||||
<Step Id="synth_design"/>
|
|
||||||
</Strategy>
|
|
||||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
||||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2021"/>
|
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
||||||
<RQSFiles/>
|
|
||||||
</Run>
|
|
||||||
<Run Id="design_1_rgb_op0_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_rgb_op0_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_rgb_op0_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_rgb_op0_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_rgb_op0_0_0_synth_1">
|
|
||||||
<Strategy Version="1" Minor="2">
|
|
||||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021">
|
|
||||||
<Desc>Vivado Synthesis Defaults</Desc>
|
|
||||||
</StratHandle>
|
|
||||||
<Step Id="synth_design"/>
|
|
||||||
</Strategy>
|
|
||||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
||||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2021"/>
|
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
||||||
<RQSFiles/>
|
|
||||||
</Run>
|
|
||||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
|
|
||||||
<Strategy Version="1" Minor="2">
|
<Strategy Version="1" Minor="2">
|
||||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/>
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/>
|
||||||
<Step Id="init_design"/>
|
<Step Id="init_design"/>
|
||||||
|
|
@ -347,7 +313,7 @@
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
<RQSFiles/>
|
<RQSFiles/>
|
||||||
</Run>
|
</Run>
|
||||||
<Run Id="design_1_rgb2dvi_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_rgb2dvi_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_rgb2dvi_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_rgb2dvi_0_0_impl_1">
|
<Run Id="impl_2" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="synth_2" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../hdmi-thru/hdmi-thru.srcs/utils_1/imports/impl_2">
|
||||||
<Strategy Version="1" Minor="2">
|
<Strategy Version="1" Minor="2">
|
||||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/>
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/>
|
||||||
<Step Id="init_design"/>
|
<Step Id="init_design"/>
|
||||||
|
|
@ -364,7 +330,7 @@
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
<RQSFiles/>
|
<RQSFiles/>
|
||||||
</Run>
|
</Run>
|
||||||
<Run Id="design_1_dvi2rgb_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_dvi2rgb_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_dvi2rgb_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_dvi2rgb_0_0_impl_1">
|
<Run Id="blinki_bd_axi_gpio_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="blinki_bd_axi_gpio_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="blinki_bd_axi_gpio_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../hdmi-out-test/hdmi-out-test.srcs/utils_1/imports/blinki_bd_axi_gpio_0_0_impl_1">
|
||||||
<Strategy Version="1" Minor="2">
|
<Strategy Version="1" Minor="2">
|
||||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/>
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/>
|
||||||
<Step Id="init_design"/>
|
<Step Id="init_design"/>
|
||||||
|
|
@ -381,7 +347,7 @@
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
<RQSFiles/>
|
<RQSFiles/>
|
||||||
</Run>
|
</Run>
|
||||||
<Run Id="impl_2" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_2" SynthRun="synth_2" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_2">
|
<Run Id="blinki_bd_rst_ps7_0_100M_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="blinki_bd_rst_ps7_0_100M_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="blinki_bd_rst_ps7_0_100M_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../hdmi-out-test/hdmi-out-test.srcs/utils_1/imports/blinki_bd_rst_ps7_0_100M_0_impl_1">
|
||||||
<Strategy Version="1" Minor="2">
|
<Strategy Version="1" Minor="2">
|
||||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/>
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/>
|
||||||
<Step Id="init_design"/>
|
<Step Id="init_design"/>
|
||||||
|
|
@ -394,77 +360,6 @@
|
||||||
<Step Id="post_route_phys_opt_design"/>
|
<Step Id="post_route_phys_opt_design"/>
|
||||||
<Step Id="write_bitstream"/>
|
<Step Id="write_bitstream"/>
|
||||||
</Strategy>
|
</Strategy>
|
||||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
||||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2021"/>
|
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
||||||
<RQSFiles/>
|
|
||||||
</Run>
|
|
||||||
<Run Id="design_1_xbar_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_xbar_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_xbar_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_xbar_0_impl_1">
|
|
||||||
<Strategy Version="1" Minor="2">
|
|
||||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/>
|
|
||||||
<Step Id="init_design"/>
|
|
||||||
<Step Id="opt_design"/>
|
|
||||||
<Step Id="power_opt_design"/>
|
|
||||||
<Step Id="place_design"/>
|
|
||||||
<Step Id="post_place_power_opt_design"/>
|
|
||||||
<Step Id="phys_opt_design"/>
|
|
||||||
<Step Id="route_design"/>
|
|
||||||
<Step Id="post_route_phys_opt_design"/>
|
|
||||||
<Step Id="write_bitstream"/>
|
|
||||||
</Strategy>
|
|
||||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2021"/>
|
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
||||||
<RQSFiles/>
|
|
||||||
</Run>
|
|
||||||
<Run Id="design_1_xbar_1_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_xbar_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_xbar_1_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_xbar_1_impl_1">
|
|
||||||
<Strategy Version="1" Minor="2">
|
|
||||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/>
|
|
||||||
<Step Id="init_design"/>
|
|
||||||
<Step Id="opt_design"/>
|
|
||||||
<Step Id="power_opt_design"/>
|
|
||||||
<Step Id="place_design"/>
|
|
||||||
<Step Id="post_place_power_opt_design"/>
|
|
||||||
<Step Id="phys_opt_design"/>
|
|
||||||
<Step Id="route_design"/>
|
|
||||||
<Step Id="post_route_phys_opt_design"/>
|
|
||||||
<Step Id="write_bitstream"/>
|
|
||||||
</Strategy>
|
|
||||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2021"/>
|
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
||||||
<RQSFiles/>
|
|
||||||
</Run>
|
|
||||||
<Run Id="design_1_system_ila_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_system_ila_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_system_ila_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_system_ila_0_0_impl_1">
|
|
||||||
<Strategy Version="1" Minor="2">
|
|
||||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/>
|
|
||||||
<Step Id="init_design"/>
|
|
||||||
<Step Id="opt_design"/>
|
|
||||||
<Step Id="power_opt_design"/>
|
|
||||||
<Step Id="place_design"/>
|
|
||||||
<Step Id="post_place_power_opt_design"/>
|
|
||||||
<Step Id="phys_opt_design"/>
|
|
||||||
<Step Id="route_design"/>
|
|
||||||
<Step Id="post_route_phys_opt_design"/>
|
|
||||||
<Step Id="write_bitstream"/>
|
|
||||||
</Strategy>
|
|
||||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2021"/>
|
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
||||||
<RQSFiles/>
|
|
||||||
</Run>
|
|
||||||
<Run Id="design_1_rgb_op0_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_rgb_op0_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_rgb_op0_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_rgb_op0_0_0_impl_1">
|
|
||||||
<Strategy Version="1" Minor="2">
|
|
||||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021">
|
|
||||||
<Desc>Default settings for Implementation.</Desc>
|
|
||||||
</StratHandle>
|
|
||||||
<Step Id="init_design"/>
|
|
||||||
<Step Id="opt_design"/>
|
|
||||||
<Step Id="power_opt_design"/>
|
|
||||||
<Step Id="place_design"/>
|
|
||||||
<Step Id="post_place_power_opt_design"/>
|
|
||||||
<Step Id="phys_opt_design"/>
|
|
||||||
<Step Id="route_design"/>
|
|
||||||
<Step Id="post_route_phys_opt_design"/>
|
|
||||||
<Step Id="write_bitstream"/>
|
|
||||||
</Strategy>
|
|
||||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2021"/>
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2021"/>
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
<RQSFiles/>
|
<RQSFiles/>
|
||||||
|
|
@ -0,0 +1,25 @@
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
`default_nettype none
|
||||||
|
|
||||||
|
// Project F: Async Reset
|
||||||
|
// (C)2019 Will Green, Open source hardware released under the MIT License
|
||||||
|
// Learn more at https://projectf.io
|
||||||
|
|
||||||
|
module async_reset(
|
||||||
|
input wire i_clk, // clock
|
||||||
|
input wire i_rst, // reset (active high)
|
||||||
|
output reg o_rst // output reset
|
||||||
|
);
|
||||||
|
|
||||||
|
(* ASYNC_REG = "TRUE" *) reg [1:0] rst_shf; // reset shift reg
|
||||||
|
|
||||||
|
initial o_rst = 1'b1; // start off with reset asserted
|
||||||
|
initial rst_shf = 2'b11; // and reset shift reg populated
|
||||||
|
|
||||||
|
always @(posedge i_clk or posedge i_rst)
|
||||||
|
if (i_rst)
|
||||||
|
{o_rst, rst_shf} <= 3'b111;
|
||||||
|
else
|
||||||
|
{o_rst, rst_shf} <= {rst_shf, 1'b0};
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,96 @@
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
`default_nettype none
|
||||||
|
|
||||||
|
// Project F: Display Clocks
|
||||||
|
// (C)2019 Will Green, Open source hardware released under the MIT License
|
||||||
|
// Learn more at https://projectf.io
|
||||||
|
|
||||||
|
// Defaults to 25.2 and 126 MHz for 640x480 at 60 Hz
|
||||||
|
|
||||||
|
module display_clocks #(
|
||||||
|
MULT_MASTER=31.5, // master clock multiplier (2.000-64.000)
|
||||||
|
DIV_MASTER=5, // master clock divider (1-106)
|
||||||
|
DIV_5X=5.0, // 5x clock divider (1-128)
|
||||||
|
DIV_1X=25, // 1x clock divider (1-128)
|
||||||
|
IN_PERIOD=10.0 // period of i_clk in ns (100 MHz = 10.0 ns)
|
||||||
|
)
|
||||||
|
(
|
||||||
|
input wire i_clk, // input clock
|
||||||
|
input wire i_rst, // reset (active high)
|
||||||
|
output wire o_clk_1x, // pixel clock
|
||||||
|
output wire o_clk_5x, // 5x clock for 10:1 DDR SerDes
|
||||||
|
output wire o_locked // clock locked? (active high)
|
||||||
|
);
|
||||||
|
|
||||||
|
wire clk_fb; // internal clock feedback
|
||||||
|
wire clk_1x_pre;
|
||||||
|
wire clk_5x_pre;
|
||||||
|
|
||||||
|
MMCME2_BASE #(
|
||||||
|
.BANDWIDTH("OPTIMIZED"), // Jitter programming (OPTIMIZED, HIGH, LOW)
|
||||||
|
.CLKFBOUT_MULT_F(MULT_MASTER), // Multiply value for all CLKOUT (2.000-64.000).
|
||||||
|
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB (-360.000-360.000).
|
||||||
|
.CLKIN1_PERIOD(IN_PERIOD), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
|
||||||
|
// CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128)
|
||||||
|
.CLKOUT0_DIVIDE_F(DIV_5X), // Divide amount for CLKOUT0 (1.000-128.000).
|
||||||
|
.CLKOUT1_DIVIDE(DIV_1X),
|
||||||
|
.CLKOUT2_DIVIDE(1),
|
||||||
|
.CLKOUT3_DIVIDE(1),
|
||||||
|
.CLKOUT4_DIVIDE(1),
|
||||||
|
.CLKOUT5_DIVIDE(1),
|
||||||
|
.CLKOUT6_DIVIDE(1),
|
||||||
|
// CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99).
|
||||||
|
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||||
|
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||||
|
.CLKOUT2_DUTY_CYCLE(0.5),
|
||||||
|
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||||
|
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||||
|
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||||
|
.CLKOUT6_DUTY_CYCLE(0.5),
|
||||||
|
// CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
|
||||||
|
.CLKOUT0_PHASE(0.0),
|
||||||
|
.CLKOUT1_PHASE(0.0),
|
||||||
|
.CLKOUT2_PHASE(0.0),
|
||||||
|
.CLKOUT3_PHASE(0.0),
|
||||||
|
.CLKOUT4_PHASE(0.0),
|
||||||
|
.CLKOUT5_PHASE(0.0),
|
||||||
|
.CLKOUT6_PHASE(0.0),
|
||||||
|
.CLKOUT4_CASCADE("FALSE"), // Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE)
|
||||||
|
.DIVCLK_DIVIDE(DIV_MASTER), // Master division value (1-106)
|
||||||
|
.REF_JITTER1(0.010), // Reference input jitter in UI (0.000-0.999).
|
||||||
|
.STARTUP_WAIT("FALSE") // Delays DONE until MMCM is locked (FALSE, TRUE)
|
||||||
|
)
|
||||||
|
MMCME2_BASE_inst (
|
||||||
|
/* verilator lint_off PINCONNECTEMPTY */
|
||||||
|
// Clock Outputs: 1-bit (each) output: User configurable clock outputs
|
||||||
|
.CLKOUT0(clk_5x_pre), // 1-bit output: CLKOUT0
|
||||||
|
.CLKOUT0B(), // 1-bit output: Inverted CLKOUT0
|
||||||
|
.CLKOUT1(clk_1x_pre), // 1-bit output: CLKOUT1
|
||||||
|
.CLKOUT1B(), // 1-bit output: Inverted CLKOUT1
|
||||||
|
.CLKOUT2(), // 1-bit output: CLKOUT2
|
||||||
|
.CLKOUT2B(), // 1-bit output: Inverted CLKOUT2
|
||||||
|
.CLKOUT3(), // 1-bit output: CLKOUT3
|
||||||
|
.CLKOUT3B(), // 1-bit output: Inverted CLKOUT3
|
||||||
|
.CLKOUT4(), // 1-bit output: CLKOUT4
|
||||||
|
.CLKOUT5(), // 1-bit output: CLKOUT5
|
||||||
|
.CLKOUT6(), // 1-bit output: CLKOUT6
|
||||||
|
// Feedback Clocks: 1-bit (each) output: Clock feedback ports
|
||||||
|
.CLKFBOUT(clk_fb), // 1-bit output: Feedback clock
|
||||||
|
.CLKFBOUTB(), // 1-bit output: Inverted CLKFBOUT
|
||||||
|
// Status Ports: 1-bit (each) output: MMCM status ports
|
||||||
|
.LOCKED(o_locked), // 1-bit output: LOCK
|
||||||
|
// Clock Inputs: 1-bit (each) input: Clock input
|
||||||
|
.CLKIN1(i_clk), // 1-bit input: Clock
|
||||||
|
// Control Ports: 1-bit (each) input: MMCM control ports
|
||||||
|
.PWRDWN(), // 1-bit input: Power-down
|
||||||
|
/* verilator lint_on PINCONNECTEMPTY */
|
||||||
|
.RST(i_rst), // 1-bit input: Reset
|
||||||
|
// Feedback Clocks: 1-bit (each) input: Clock feedback ports
|
||||||
|
.CLKFBIN(clk_fb) // 1-bit input: Feedback clock
|
||||||
|
);
|
||||||
|
|
||||||
|
// explicitly buffer output clocks
|
||||||
|
BUFG bufg_clk_pix(.I(clk_1x_pre), .O(o_clk_1x));
|
||||||
|
BUFG bufg_clk_pix_5x(.I(clk_5x_pre), .O(o_clk_5x));
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,157 @@
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
//`default_nettype none
|
||||||
|
|
||||||
|
// Project F: Display Controller DVI Demo
|
||||||
|
// (C)2020 Will Green, Open source hardware released under the MIT License
|
||||||
|
// Learn more at https://projectf.io
|
||||||
|
|
||||||
|
// This demo requires the following Verilog modules:
|
||||||
|
// * display_clocks
|
||||||
|
// * display_timings
|
||||||
|
// * dvi_generator
|
||||||
|
// * serializer_10to1
|
||||||
|
// * async_reset
|
||||||
|
// * tmds_encoder_dvi
|
||||||
|
// * test_card_simple or another test card
|
||||||
|
|
||||||
|
module display_demo_dvi(
|
||||||
|
input wire [1:0] sel, // test card modifier. original output = 0
|
||||||
|
input wire CLK, // board clock: 100 MHz on Arty/Basys3/Nexys
|
||||||
|
input wire RST_BTN, // reset button
|
||||||
|
inout wire hdmi_tx_cec, // CE control bidirectional
|
||||||
|
input wire hdmi_tx_hpd, // hot-plug detect
|
||||||
|
inout wire hdmi_tx_rscl, // DDC bidirectional
|
||||||
|
inout wire hdmi_tx_rsda, // DDC bidirectional
|
||||||
|
output wire hdmi_tx_clk_n, // HDMI clock differential negative
|
||||||
|
output wire hdmi_tx_clk_p, // HDMI clock differential positive
|
||||||
|
output wire [2:0] hdmi_tx_n, // Three HDMI channels differential negative
|
||||||
|
output wire [2:0] hdmi_tx_p // Three HDMI channels differential positive
|
||||||
|
);
|
||||||
|
|
||||||
|
// Display Clocks
|
||||||
|
wire pix_clk; // pixel clock
|
||||||
|
wire pix_clk_5x; // 5x clock for 10:1 DDR SerDes
|
||||||
|
wire clk_lock; // clock locked?
|
||||||
|
|
||||||
|
display_clocks #( // 640x480 800x600 1280x720 1920x1080
|
||||||
|
.MULT_MASTER(37.125), // 31.5 10.0 37.125 37.125
|
||||||
|
.DIV_MASTER(5), // 5 1 5 5
|
||||||
|
.DIV_5X(2.0), // 5.0 5.0 2.0 1.0
|
||||||
|
.DIV_1X(10), // 25 25 10 5
|
||||||
|
.IN_PERIOD(10.0) // 100 MHz = 10 ns
|
||||||
|
)
|
||||||
|
display_clocks_inst
|
||||||
|
(
|
||||||
|
.i_clk(CLK),
|
||||||
|
.i_rst(~RST_BTN), // reset is active low on Arty & Nexys Video
|
||||||
|
.o_clk_1x(pix_clk),
|
||||||
|
.o_clk_5x(pix_clk_5x),
|
||||||
|
.o_locked(clk_lock)
|
||||||
|
);
|
||||||
|
|
||||||
|
// Display Timings
|
||||||
|
wire signed [15:0] sx; // horizontal screen position (signed)
|
||||||
|
wire signed [15:0] sy; // vertical screen position (signed)
|
||||||
|
wire h_sync; // horizontal sync
|
||||||
|
wire v_sync; // vertical sync
|
||||||
|
wire de; // display enable
|
||||||
|
wire frame; // frame start
|
||||||
|
|
||||||
|
display_timings #( // 640x480 800x600 1280x720 1920x1080
|
||||||
|
.H_RES(1280), // 640 800 1280 1920
|
||||||
|
.V_RES(720), // 480 600 720 1080
|
||||||
|
.H_FP(110), // 16 40 110 88
|
||||||
|
.H_SYNC(40), // 96 128 40 44
|
||||||
|
.H_BP(220), // 48 88 220 148
|
||||||
|
.V_FP(5), // 10 1 5 4
|
||||||
|
.V_SYNC(5), // 2 4 5 5
|
||||||
|
.V_BP(20), // 33 23 20 36
|
||||||
|
.H_POL(1), // 0 1 1 1
|
||||||
|
.V_POL(1) // 0 1 1 1
|
||||||
|
)
|
||||||
|
display_timings_inst (
|
||||||
|
.i_pix_clk(pix_clk),
|
||||||
|
.i_rst(!clk_lock),
|
||||||
|
.o_hs(h_sync),
|
||||||
|
.o_vs(v_sync),
|
||||||
|
.o_de(de),
|
||||||
|
.o_frame(frame),
|
||||||
|
.o_sx(sx),
|
||||||
|
.o_sy(sy)
|
||||||
|
);
|
||||||
|
|
||||||
|
// test card colour output
|
||||||
|
wire [7:0] w_red ,red ;
|
||||||
|
wire [7:0] w_green,green;
|
||||||
|
wire [7:0] w_blue ,blue ;
|
||||||
|
|
||||||
|
// Test Card: Simple - ENABLE ONE TEST CARD INSTANCE ONLY
|
||||||
|
test_card_simple #(
|
||||||
|
.H_RES(1280) // horizontal resolution
|
||||||
|
) test_card_inst (
|
||||||
|
.i_x (sx ),
|
||||||
|
.o_red (w_red ),
|
||||||
|
.o_green(w_green),
|
||||||
|
.o_blue (w_blue )
|
||||||
|
);
|
||||||
|
|
||||||
|
assign red = ( sel[0] )? ~w_red : w_red ;
|
||||||
|
assign green = ( sel[0] )? ~w_green: w_green;
|
||||||
|
assign blue = ( sel[0] )? ~w_blue : w_blue ;
|
||||||
|
|
||||||
|
// // Test Card: Squares - ENABLE ONE TEST CARD INSTANCE ONLY
|
||||||
|
// test_card_squares #(
|
||||||
|
// .H_RES(1280), // horizontal resolution
|
||||||
|
// .V_RES(720) // vertical resolution
|
||||||
|
// )
|
||||||
|
// test_card_inst (
|
||||||
|
// .i_x(sx),
|
||||||
|
// .i_y(sy),
|
||||||
|
// .o_red(red),
|
||||||
|
// .o_green(green),
|
||||||
|
// .o_blue(blue)
|
||||||
|
// );
|
||||||
|
|
||||||
|
// // Test Card: Gradient - ENABLE ONE TEST CARD INSTANCE ONLY
|
||||||
|
// localparam GRAD_STEP = 2; // step right shift: 480=2, 720=2, 1080=3
|
||||||
|
// test_card_gradient test_card_inst (
|
||||||
|
// .i_y(sy[GRAD_STEP+7:GRAD_STEP]),
|
||||||
|
// .i_x(sx[5:0]),
|
||||||
|
// .o_red(red),
|
||||||
|
// .o_green(green),
|
||||||
|
// .o_blue(blue)
|
||||||
|
// );
|
||||||
|
|
||||||
|
// TMDS Encoding and Serialization
|
||||||
|
wire tmds_ch0_serial, tmds_ch1_serial, tmds_ch2_serial, tmds_chc_serial;
|
||||||
|
dvi_generator dvi_out (
|
||||||
|
.i_pix_clk(pix_clk),
|
||||||
|
.i_pix_clk_5x(pix_clk_5x),
|
||||||
|
.i_rst(!clk_lock),
|
||||||
|
.i_de(de),
|
||||||
|
.i_data_ch0(blue),
|
||||||
|
.i_data_ch1(green),
|
||||||
|
.i_data_ch2(red),
|
||||||
|
.i_ctrl_ch0({v_sync, h_sync}),
|
||||||
|
.i_ctrl_ch1(2'b00),
|
||||||
|
.i_ctrl_ch2(2'b00),
|
||||||
|
.o_tmds_ch0_serial(tmds_ch0_serial),
|
||||||
|
.o_tmds_ch1_serial(tmds_ch1_serial),
|
||||||
|
.o_tmds_ch2_serial(tmds_ch2_serial),
|
||||||
|
.o_tmds_chc_serial(tmds_chc_serial) // encode pixel clock via same path
|
||||||
|
);
|
||||||
|
|
||||||
|
// TMDS Buffered Output
|
||||||
|
OBUFDS #(.IOSTANDARD("TMDS_33"))
|
||||||
|
tmds_buf_ch0 (.I(tmds_ch0_serial), .O(hdmi_tx_p[0]), .OB(hdmi_tx_n[0]));
|
||||||
|
OBUFDS #(.IOSTANDARD("TMDS_33"))
|
||||||
|
tmds_buf_ch1 (.I(tmds_ch1_serial), .O(hdmi_tx_p[1]), .OB(hdmi_tx_n[1]));
|
||||||
|
OBUFDS #(.IOSTANDARD("TMDS_33"))
|
||||||
|
tmds_buf_ch2 (.I(tmds_ch2_serial), .O(hdmi_tx_p[2]), .OB(hdmi_tx_n[2]));
|
||||||
|
OBUFDS #(.IOSTANDARD("TMDS_33"))
|
||||||
|
tmds_buf_chc (.I(tmds_chc_serial), .O(hdmi_tx_clk_p), .OB(hdmi_tx_clk_n));
|
||||||
|
|
||||||
|
assign hdmi_tx_cec = 1'bz;
|
||||||
|
assign hdmi_tx_rsda = 1'bz;
|
||||||
|
assign hdmi_tx_rscl = 1'b1;
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,80 @@
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
`default_nettype none
|
||||||
|
|
||||||
|
// Project F: Display Timings
|
||||||
|
// (C)2019 Will Green, Open Source Hardware released under the MIT License
|
||||||
|
// Learn more at https://projectf.io
|
||||||
|
|
||||||
|
// Defaults to 640x480 at 60 Hz
|
||||||
|
|
||||||
|
module display_timings #(
|
||||||
|
H_RES=640, // horizontal resolution (pixels)
|
||||||
|
V_RES=480, // vertical resolution (lines)
|
||||||
|
H_FP=16, // horizontal front porch
|
||||||
|
H_SYNC=96, // horizontal sync
|
||||||
|
H_BP=48, // horizontal back porch
|
||||||
|
V_FP=10, // vertical front porch
|
||||||
|
V_SYNC=2, // vertical sync
|
||||||
|
V_BP=33, // vertical back porch
|
||||||
|
H_POL=0, // horizontal sync polarity (0:neg, 1:pos)
|
||||||
|
V_POL=0 // vertical sync polarity (0:neg, 1:pos)
|
||||||
|
)
|
||||||
|
(
|
||||||
|
input wire i_pix_clk, // pixel clock
|
||||||
|
input wire i_rst, // reset: restarts frame (active high)
|
||||||
|
output wire o_hs, // horizontal sync
|
||||||
|
output wire o_vs, // vertical sync
|
||||||
|
output wire o_de, // display enable: high during active video
|
||||||
|
output wire o_frame, // high for one tick at the start of each frame
|
||||||
|
output reg signed [15:0] o_sx, // horizontal beam position (including blanking)
|
||||||
|
output reg signed [15:0] o_sy // vertical beam position (including blanking)
|
||||||
|
);
|
||||||
|
|
||||||
|
// Horizontal: sync, active, and pixels
|
||||||
|
localparam signed H_STA = 0 - H_FP - H_SYNC - H_BP; // horizontal start
|
||||||
|
localparam signed HS_STA = H_STA + H_FP; // sync start
|
||||||
|
localparam signed HS_END = HS_STA + H_SYNC; // sync end
|
||||||
|
localparam signed HA_STA = 0; // active start
|
||||||
|
localparam signed HA_END = H_RES - 1; // active end
|
||||||
|
|
||||||
|
// Vertical: sync, active, and pixels
|
||||||
|
localparam signed V_STA = 0 - V_FP - V_SYNC - V_BP; // vertical start
|
||||||
|
localparam signed VS_STA = V_STA + V_FP; // sync start
|
||||||
|
localparam signed VS_END = VS_STA + V_SYNC; // sync end
|
||||||
|
localparam signed VA_STA = 0; // active start
|
||||||
|
localparam signed VA_END = V_RES - 1; // active end
|
||||||
|
|
||||||
|
// generate sync signals with correct polarity
|
||||||
|
assign o_hs = H_POL ? (o_sx > HS_STA && o_sx <= HS_END)
|
||||||
|
: ~(o_sx > HS_STA && o_sx <= HS_END);
|
||||||
|
assign o_vs = V_POL ? (o_sy > VS_STA && o_sy <= VS_END)
|
||||||
|
: ~(o_sy > VS_STA && o_sy <= VS_END);
|
||||||
|
|
||||||
|
// display enable: high during active period
|
||||||
|
assign o_de = (o_sx >= 0 && o_sy >= 0);
|
||||||
|
|
||||||
|
// o_frame: high for one tick at the start of each frame
|
||||||
|
assign o_frame = (o_sy == V_STA && o_sx == H_STA);
|
||||||
|
|
||||||
|
always @ (posedge i_pix_clk)
|
||||||
|
begin
|
||||||
|
if (i_rst) // reset to start of frame
|
||||||
|
begin
|
||||||
|
o_sx <= H_STA;
|
||||||
|
o_sy <= V_STA;
|
||||||
|
end
|
||||||
|
else
|
||||||
|
begin
|
||||||
|
if (o_sx == HA_END) // end of line
|
||||||
|
begin
|
||||||
|
o_sx <= H_STA;
|
||||||
|
if (o_sy == VA_END) // end of frame
|
||||||
|
o_sy <= V_STA;
|
||||||
|
else
|
||||||
|
o_sy <= o_sy + 16'sh1;
|
||||||
|
end
|
||||||
|
else
|
||||||
|
o_sx <= o_sx + 16'sh1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,94 @@
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
`default_nettype none
|
||||||
|
|
||||||
|
// Project F: Display DVI Generator
|
||||||
|
// (C)2019 Will Green, Open Source Hardware released under the MIT License
|
||||||
|
// Learn more at https://projectf.io
|
||||||
|
|
||||||
|
module dvi_generator(
|
||||||
|
input wire i_pix_clk, // pixel clock
|
||||||
|
input wire i_pix_clk_5x, // 5 x pixel clock for DDR serialization
|
||||||
|
input wire i_rst, // reset (active high)
|
||||||
|
input wire i_de, // display enable (draw video)
|
||||||
|
input wire [7:0] i_data_ch0, // channel 0 - 8-bit colour data
|
||||||
|
input wire [7:0] i_data_ch1, // channel 1 - 8-bit colour data
|
||||||
|
input wire [7:0] i_data_ch2, // channel 2 - 8-bit colour data
|
||||||
|
input wire [1:0] i_ctrl_ch0, // channel 0 - 2-bit control data
|
||||||
|
input wire [1:0] i_ctrl_ch1, // channel 1 - 2-bit control data
|
||||||
|
input wire [1:0] i_ctrl_ch2, // channel 2 - 2-bit control data
|
||||||
|
output wire o_tmds_ch0_serial, // channel 0 - serial TMDS
|
||||||
|
output wire o_tmds_ch1_serial, // channel 1 - serial TMDS
|
||||||
|
output wire o_tmds_ch2_serial, // channel 2 - serial TMDS
|
||||||
|
output wire o_tmds_chc_serial // channel clock - serial TMDS
|
||||||
|
);
|
||||||
|
|
||||||
|
wire [9:0] tmds_ch0, tmds_ch1, tmds_ch2;
|
||||||
|
|
||||||
|
tmds_encoder_dvi encode_ch0 (
|
||||||
|
.i_clk(i_pix_clk),
|
||||||
|
.i_rst(i_rst),
|
||||||
|
.i_data(i_data_ch0),
|
||||||
|
.i_ctrl(i_ctrl_ch0),
|
||||||
|
.i_de(i_de),
|
||||||
|
.o_tmds(tmds_ch0)
|
||||||
|
);
|
||||||
|
|
||||||
|
tmds_encoder_dvi encode_ch1 (
|
||||||
|
.i_clk(i_pix_clk),
|
||||||
|
.i_rst(i_rst),
|
||||||
|
.i_data(i_data_ch1),
|
||||||
|
.i_ctrl(i_ctrl_ch1),
|
||||||
|
.i_de(i_de),
|
||||||
|
.o_tmds(tmds_ch1)
|
||||||
|
);
|
||||||
|
|
||||||
|
tmds_encoder_dvi encode_ch2 (
|
||||||
|
.i_clk(i_pix_clk),
|
||||||
|
.i_rst(i_rst),
|
||||||
|
.i_data(i_data_ch2),
|
||||||
|
.i_ctrl(i_ctrl_ch2),
|
||||||
|
.i_de(i_de),
|
||||||
|
.o_tmds(tmds_ch2)
|
||||||
|
);
|
||||||
|
|
||||||
|
// common async reset for serdes
|
||||||
|
wire rst_oserdes;
|
||||||
|
async_reset async_reset_instance (
|
||||||
|
.i_clk(i_pix_clk),
|
||||||
|
.i_rst(i_rst),
|
||||||
|
.o_rst(rst_oserdes)
|
||||||
|
);
|
||||||
|
|
||||||
|
serializer_10to1 serialize_ch0 (
|
||||||
|
.i_clk(i_pix_clk),
|
||||||
|
.i_clk_hs(i_pix_clk_5x),
|
||||||
|
.i_rst_oserdes(rst_oserdes),
|
||||||
|
.i_data(tmds_ch0),
|
||||||
|
.o_data(o_tmds_ch0_serial)
|
||||||
|
);
|
||||||
|
|
||||||
|
serializer_10to1 serialize_ch1 (
|
||||||
|
.i_clk(i_pix_clk),
|
||||||
|
.i_clk_hs(i_pix_clk_5x),
|
||||||
|
.i_rst_oserdes(rst_oserdes),
|
||||||
|
.i_data(tmds_ch1),
|
||||||
|
.o_data(o_tmds_ch1_serial)
|
||||||
|
);
|
||||||
|
|
||||||
|
serializer_10to1 serialize_ch2 (
|
||||||
|
.i_clk(i_pix_clk),
|
||||||
|
.i_clk_hs(i_pix_clk_5x),
|
||||||
|
.i_rst_oserdes(rst_oserdes),
|
||||||
|
.i_data(tmds_ch2),
|
||||||
|
.o_data(o_tmds_ch2_serial)
|
||||||
|
);
|
||||||
|
|
||||||
|
serializer_10to1 serialize_chc (
|
||||||
|
.i_clk(i_pix_clk),
|
||||||
|
.i_clk_hs(i_pix_clk_5x),
|
||||||
|
.i_rst_oserdes(rst_oserdes),
|
||||||
|
.i_data(10'b0000011111),
|
||||||
|
.o_data(o_tmds_chc_serial)
|
||||||
|
);
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,99 @@
|
||||||
|
`default_nettype wire
|
||||||
|
|
||||||
|
module dvi_top(
|
||||||
|
|
||||||
|
output wire BCLK_O,
|
||||||
|
inout wire [14:0] DDR_addr,
|
||||||
|
inout wire [ 2:0] DDR_ba,
|
||||||
|
inout wire DDR_cas_n,
|
||||||
|
inout wire DDR_ck_n,
|
||||||
|
inout wire DDR_ck_p,
|
||||||
|
inout wire DDR_cke,
|
||||||
|
inout wire DDR_cs_n,
|
||||||
|
inout wire [ 3:0] DDR_dm,
|
||||||
|
inout wire [31:0] DDR_dq,
|
||||||
|
inout wire [ 3:0] DDR_dqs_n,
|
||||||
|
inout wire [ 3:0] DDR_dqs_p,
|
||||||
|
inout wire DDR_odt,
|
||||||
|
inout wire DDR_ras_n,
|
||||||
|
inout wire DDR_reset_n,
|
||||||
|
inout wire DDR_we_n,
|
||||||
|
inout wire FIXED_IO_ddr_vrn,
|
||||||
|
inout wire FIXED_IO_ddr_vrp,
|
||||||
|
inout wire [53:0] FIXED_IO_mio,
|
||||||
|
inout wire FIXED_IO_ps_clk,
|
||||||
|
inout wire FIXED_IO_ps_porb,
|
||||||
|
inout wire FIXED_IO_ps_srstb,
|
||||||
|
output wire LRCLK_O,
|
||||||
|
output wire MCLK_O,
|
||||||
|
input wire SDATA_I,
|
||||||
|
output wire SDATA_O,
|
||||||
|
input wire TMDS_Clk_n_1,
|
||||||
|
input wire TMDS_Clk_p_1,
|
||||||
|
input wire [2:0] TMDS_Data_n_1,
|
||||||
|
input wire [2:0] TMDS_Data_p_1,
|
||||||
|
output wire TMDS_Clk_n_0 ,
|
||||||
|
output wire TMDS_Clk_p_0 ,
|
||||||
|
output wire [2:0] TMDS_Data_n_0,
|
||||||
|
output wire [2:0] TMDS_Data_p_0,
|
||||||
|
input wire [3:0] btns_4bits_tri_i,
|
||||||
|
inout wire hdmi_in_ddc_scl_io,
|
||||||
|
inout wire hdmi_in_ddc_sda_io,
|
||||||
|
output wire [0:0] hdmi_rx_hpd ,
|
||||||
|
input wire hdmi_tx_hpd ,
|
||||||
|
inout wire iic_rtl_scl_io,
|
||||||
|
inout wire iic_rtl_sda_io,
|
||||||
|
output wire leds_4bits_tri_o_3,
|
||||||
|
output wire leds_4bits_tri_o_2,
|
||||||
|
output wire leds_4bits_tri_o_1,
|
||||||
|
output wire leds_4bits_tri_o_0,
|
||||||
|
input wire sws_2bits_tri_i_1,
|
||||||
|
input wire sws_2bits_tri_i_0
|
||||||
|
);
|
||||||
|
|
||||||
|
wire CLK ;
|
||||||
|
// wire RST_BTN ;
|
||||||
|
// wire hdmi_tx_cec ;
|
||||||
|
// wire hdmi_tx_hpd ;
|
||||||
|
// wire hdmi_tx_rscl ;
|
||||||
|
// wire hdmi_tx_rsda ;
|
||||||
|
// wire hdmi_tx_clk_n ;
|
||||||
|
// wire hdmi_tx_clk_p ;
|
||||||
|
// wire [2:0] hdmi_tx_n ;
|
||||||
|
// wire [2:0] hdmi_tx_p ;
|
||||||
|
|
||||||
|
blinki_bd_wrapper bd0 (
|
||||||
|
.FCLK_CLK0_0 (CLK),
|
||||||
|
.FCLK_CLK1_0 (),
|
||||||
|
|
||||||
|
//.leds_4bits_tri_io ({
|
||||||
|
.gpio_io_o_0 ({
|
||||||
|
//leds_4bits_tri_o_3,
|
||||||
|
1'bz,
|
||||||
|
leds_4bits_tri_o_2,
|
||||||
|
leds_4bits_tri_o_1,
|
||||||
|
leds_4bits_tri_o_0
|
||||||
|
})
|
||||||
|
|
||||||
|
);
|
||||||
|
|
||||||
|
assign leds_4bits_tri_o_3 = hdmi_tx_hpd;
|
||||||
|
|
||||||
|
display_demo_dvi u_demoDVI(
|
||||||
|
.CLK (CLK), // board clock: 100 MHz on Arty/Basys3/Nexys
|
||||||
|
.RST_BTN (~btns_4bits_tri_i[0]), // reset button
|
||||||
|
.hdmi_tx_cec (), // CE control bidirectional
|
||||||
|
.hdmi_tx_hpd (hdmi_tx_hpd ), // hot-plug detect
|
||||||
|
.hdmi_tx_rscl (hdmi_in_ddc_scl_io), // DDC bidirectional
|
||||||
|
.hdmi_tx_rsda (hdmi_in_ddc_sda_io), // DDC bidirectional
|
||||||
|
.hdmi_tx_clk_n(TMDS_Clk_n_0 ), // HDMI clock differential negative
|
||||||
|
.hdmi_tx_clk_p(TMDS_Clk_p_0 ), // HDMI clock differential positive
|
||||||
|
.hdmi_tx_n (TMDS_Data_n_0 ), // Three HDMI channels differential negative
|
||||||
|
.hdmi_tx_p (TMDS_Data_p_0 ), // Three HDMI channels differential positive
|
||||||
|
.sel ({ sws_2bits_tri_i_1,
|
||||||
|
sws_2bits_tri_i_0
|
||||||
|
}) // Three HDMI channels differential positive
|
||||||
|
);
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
|
@ -0,0 +1,117 @@
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
`default_nettype none
|
||||||
|
|
||||||
|
// Project F: Display 10:1 Serializer
|
||||||
|
// (C)2019 Will Green, Open source hardware released under the MIT License
|
||||||
|
// Learn more at https://projectf.io
|
||||||
|
|
||||||
|
module serializer_10to1(
|
||||||
|
input wire i_clk, // parallel clock
|
||||||
|
input wire i_clk_hs, // high-speed clock (5 x i_clk when using DDR)
|
||||||
|
input wire i_rst_oserdes, // reset from async reset (active high)
|
||||||
|
input wire [9:0] i_data, // input parallel data
|
||||||
|
output wire o_data // output serial data
|
||||||
|
);
|
||||||
|
|
||||||
|
// use two OSERDES2 to serialize 10-bit TMDS data
|
||||||
|
wire shift1, shift2; // wires between oserdes master and slave
|
||||||
|
|
||||||
|
OSERDESE2 #(
|
||||||
|
.DATA_RATE_OQ("DDR"), // DDR, SDR
|
||||||
|
.DATA_RATE_TQ("SDR"), // DDR, BUF, SDR
|
||||||
|
.DATA_WIDTH(10), // Parallel data width (2-8,10,14)
|
||||||
|
.INIT_OQ(1'b1), // Initial value of OQ output (1'b0,1'b1)
|
||||||
|
.INIT_TQ(1'b1), // Initial value of TQ output (1'b0,1'b1)
|
||||||
|
.SERDES_MODE("MASTER"), // MASTER, SLAVE
|
||||||
|
.SRVAL_OQ(1'b0), // OQ output value when SR is used (1'b0,1'b1)
|
||||||
|
.SRVAL_TQ(1'b0), // TQ output value when SR is used (1'b0,1'b1)
|
||||||
|
.TBYTE_CTL("FALSE"), // Enable tristate byte operation (FALSE, TRUE)
|
||||||
|
.TBYTE_SRC("FALSE"), // Tristate byte source (FALSE, TRUE)
|
||||||
|
.TRISTATE_WIDTH(1) // 3-state converter width (1,4)
|
||||||
|
)
|
||||||
|
master10 (
|
||||||
|
/* verilator lint_off PINCONNECTEMPTY */
|
||||||
|
.OFB(), // 1-bit output: Feedback path for data
|
||||||
|
.OQ(o_data), // 1-bit output: Data path output
|
||||||
|
// SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
|
||||||
|
.SHIFTOUT1(),
|
||||||
|
.SHIFTOUT2(),
|
||||||
|
.TBYTEOUT(), // 1-bit output: Byte group tristate
|
||||||
|
.TFB(), // 1-bit output: 3-state control
|
||||||
|
.TQ(), // 1-bit output: 3-state control
|
||||||
|
.CLK(i_clk_hs), // 1-bit input: High speed clock
|
||||||
|
.CLKDIV(i_clk), // 1-bit input: Divided clock
|
||||||
|
/* verilator lint_on PINCONNECTEMPTY */
|
||||||
|
// D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
|
||||||
|
.D1(i_data[0]),
|
||||||
|
.D2(i_data[1]),
|
||||||
|
.D3(i_data[2]),
|
||||||
|
.D4(i_data[3]),
|
||||||
|
.D5(i_data[4]),
|
||||||
|
.D6(i_data[5]),
|
||||||
|
.D7(i_data[6]),
|
||||||
|
.D8(i_data[7]),
|
||||||
|
.OCE(1'b1), // 1-bit input: Output data clock enable
|
||||||
|
.RST(i_rst_oserdes), // 1-bit input: Reset
|
||||||
|
// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
|
||||||
|
.SHIFTIN1(shift1),
|
||||||
|
.SHIFTIN2(shift2),
|
||||||
|
// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
|
||||||
|
.T1(1'b0),
|
||||||
|
.T2(1'b0),
|
||||||
|
.T3(1'b0),
|
||||||
|
.T4(1'b0),
|
||||||
|
.TBYTEIN(1'b0), // 1-bit input: Byte group tristate
|
||||||
|
.TCE(1'b0) // 1-bit input: 3-state clock enable
|
||||||
|
);
|
||||||
|
|
||||||
|
OSERDESE2 #(
|
||||||
|
.DATA_RATE_OQ("DDR"), // DDR, SDR
|
||||||
|
.DATA_RATE_TQ("SDR"), // DDR, BUF, SDR
|
||||||
|
.DATA_WIDTH(10), // Parallel data width (2-8,10,14)
|
||||||
|
.INIT_OQ(1'b1), // Initial value of OQ output (1'b0,1'b1)
|
||||||
|
.INIT_TQ(1'b1), // Initial value of TQ output (1'b0,1'b1)
|
||||||
|
.SERDES_MODE("SLAVE"), // MASTER, SLAVE
|
||||||
|
.SRVAL_OQ(1'b0), // OQ output value when SR is used (1'b0,1'b1)
|
||||||
|
.SRVAL_TQ(1'b0), // TQ output value when SR is used (1'b0,1'b1)
|
||||||
|
.TBYTE_CTL("FALSE"), // Enable tristate byte operation (FALSE, TRUE)
|
||||||
|
.TBYTE_SRC("FALSE"), // Tristate byte source (FALSE, TRUE)
|
||||||
|
.TRISTATE_WIDTH(1) // 3-state converter width (1,4)
|
||||||
|
)
|
||||||
|
slave10 (
|
||||||
|
/* verilator lint_off PINCONNECTEMPTY */
|
||||||
|
.OFB(), // 1-bit output: Feedback path for data
|
||||||
|
.OQ(), // 1-bit output: Data path output
|
||||||
|
// SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
|
||||||
|
.SHIFTOUT1(shift1),
|
||||||
|
.SHIFTOUT2(shift2),
|
||||||
|
.TBYTEOUT(), // 1-bit output: Byte group tristate
|
||||||
|
.TFB(), // 1-bit output: 3-state control
|
||||||
|
.TQ(), // 1-bit output: 3-state control
|
||||||
|
.CLK(i_clk_hs), // 1-bit input: High speed clock
|
||||||
|
.CLKDIV(i_clk), // 1-bit input: Divided clock
|
||||||
|
/* verilator lint_on PINCONNECTEMPTY */
|
||||||
|
// D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
|
||||||
|
.D1(1'b0),
|
||||||
|
.D2(1'b0),
|
||||||
|
.D3(i_data[8]),
|
||||||
|
.D4(i_data[9]),
|
||||||
|
.D5(1'b0),
|
||||||
|
.D6(1'b0),
|
||||||
|
.D7(1'b0),
|
||||||
|
.D8(1'b0),
|
||||||
|
.OCE(1'b1), // 1-bit input: Output data clock enable
|
||||||
|
.RST(i_rst_oserdes), // 1-bit input: Reset
|
||||||
|
// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
|
||||||
|
.SHIFTIN1(1'b0),
|
||||||
|
.SHIFTIN2(1'b0),
|
||||||
|
// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
|
||||||
|
.T1(1'b0),
|
||||||
|
.T2(1'b0),
|
||||||
|
.T3(1'b0),
|
||||||
|
.T4(1'b0),
|
||||||
|
.TBYTEIN(1'b0), // 1-bit input: Byte group tristate
|
||||||
|
.TCE(1'b0) // 1-bit input: 3-state clock enable
|
||||||
|
);
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,31 @@
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
`default_nettype none
|
||||||
|
|
||||||
|
// Project F: Display Controller Simple Test Card
|
||||||
|
// (C)2019 Will Green, Open Source Hardware released under the MIT License
|
||||||
|
// Learn more at https://projectf.io
|
||||||
|
|
||||||
|
module test_card_simple #(H_RES=640) (
|
||||||
|
input wire signed [15:0] i_x,
|
||||||
|
output wire [7:0] o_red,
|
||||||
|
output wire [7:0] o_green,
|
||||||
|
output wire [7:0] o_blue
|
||||||
|
);
|
||||||
|
|
||||||
|
localparam HW = H_RES >> 3; // horizontal colour width = H_RES / 8
|
||||||
|
|
||||||
|
// Bands
|
||||||
|
wire b0 = (i_x >= 0 ) & (i_x < HW );
|
||||||
|
wire b1 = (i_x >= HW ) & (i_x < HW * 2);
|
||||||
|
wire b2 = (i_x >= HW * 2) & (i_x < HW * 3);
|
||||||
|
wire b3 = (i_x >= HW * 3) & (i_x < HW * 4);
|
||||||
|
wire b4 = (i_x >= HW * 4) & (i_x < HW * 5);
|
||||||
|
wire b5 = (i_x >= HW * 5) & (i_x < HW * 6);
|
||||||
|
wire b6 = (i_x >= HW * 6) & (i_x < HW * 7);
|
||||||
|
wire b7 = (i_x >= HW * 7) & (i_x < HW * 8);
|
||||||
|
|
||||||
|
// Colour Output
|
||||||
|
assign o_red = {8{b0 | b1 | b5}} + {2'b0,{6{b6}}} + {b7, 7'b0};
|
||||||
|
assign o_green = {8{b1 | b2 | b3}} + {2'b0,{6{b6}}} + {b7, 7'b0};
|
||||||
|
assign o_blue = {8{b3 | b4 | b5}} + {2'b0,{6{b6}}} + {b7, 7'b0};
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,95 @@
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
`default_nettype none
|
||||||
|
|
||||||
|
// Project F: Display TMDS Encoder for DVI
|
||||||
|
// (C)2019 Will Green, Open source hardware released under the MIT License
|
||||||
|
// Learn more at https://projectf.io
|
||||||
|
|
||||||
|
module tmds_encoder_dvi(
|
||||||
|
input wire i_clk, // clock
|
||||||
|
input wire i_rst, // reset (active high)
|
||||||
|
input wire [7:0] i_data, // colour data
|
||||||
|
input wire [1:0] i_ctrl, // control data
|
||||||
|
input wire i_de, // display enable (active high)
|
||||||
|
output reg [9:0] o_tmds // encoded TMDS data
|
||||||
|
);
|
||||||
|
|
||||||
|
// select basic encoding based on the ones in the input data
|
||||||
|
wire [3:0] d_ones = {3'b0,i_data[0]} + {3'b0,i_data[1]} + {3'b0,i_data[2]}
|
||||||
|
+ {3'b0,i_data[3]} + {3'b0,i_data[4]} + {3'b0,i_data[5]}
|
||||||
|
+ {3'b0,i_data[6]} + {3'b0,i_data[7]};
|
||||||
|
wire use_xnor = (d_ones > 4'd4) || ((d_ones == 4'd4) && (i_data[0] == 0));
|
||||||
|
|
||||||
|
// encode colour data with xor/xnor
|
||||||
|
/* verilator lint_off UNOPTFLAT */
|
||||||
|
wire [8:0] enc_qm;
|
||||||
|
assign enc_qm[0] = i_data[0];
|
||||||
|
assign enc_qm[1] = (use_xnor) ? (enc_qm[0] ~^ i_data[1]) : (enc_qm[0] ^ i_data[1]);
|
||||||
|
assign enc_qm[2] = (use_xnor) ? (enc_qm[1] ~^ i_data[2]) : (enc_qm[1] ^ i_data[2]);
|
||||||
|
assign enc_qm[3] = (use_xnor) ? (enc_qm[2] ~^ i_data[3]) : (enc_qm[2] ^ i_data[3]);
|
||||||
|
assign enc_qm[4] = (use_xnor) ? (enc_qm[3] ~^ i_data[4]) : (enc_qm[3] ^ i_data[4]);
|
||||||
|
assign enc_qm[5] = (use_xnor) ? (enc_qm[4] ~^ i_data[5]) : (enc_qm[4] ^ i_data[5]);
|
||||||
|
assign enc_qm[6] = (use_xnor) ? (enc_qm[5] ~^ i_data[6]) : (enc_qm[5] ^ i_data[6]);
|
||||||
|
assign enc_qm[7] = (use_xnor) ? (enc_qm[6] ~^ i_data[7]) : (enc_qm[6] ^ i_data[7]);
|
||||||
|
assign enc_qm[8] = (use_xnor) ? 0 : 1;
|
||||||
|
/* verilator lint_on UNOPTFLAT */
|
||||||
|
|
||||||
|
// disparity in encoded data for DC balancing: needs to cover -8 to +8
|
||||||
|
wire signed [4:0] ones = {4'b0,enc_qm[0]} + {4'b0,enc_qm[1]}
|
||||||
|
+ {4'b0,enc_qm[2]} + {4'b0,enc_qm[3]} + {4'b0,enc_qm[4]}
|
||||||
|
+ {4'b0,enc_qm[5]} + {4'b0,enc_qm[6]} + {4'b0,enc_qm[7]};
|
||||||
|
|
||||||
|
wire signed [4:0] zeros = 5'b01000 - ones;
|
||||||
|
wire signed [4:0] balance = ones - zeros;
|
||||||
|
|
||||||
|
// record ongoing DC bias
|
||||||
|
reg signed [4:0] bias;
|
||||||
|
|
||||||
|
always @ (posedge i_clk)
|
||||||
|
begin
|
||||||
|
if (i_rst)
|
||||||
|
begin
|
||||||
|
o_tmds <= 10'b1101010100; // equivalent to ctrl 2'b00
|
||||||
|
bias <= 5'sb00000;
|
||||||
|
end
|
||||||
|
else if (i_de == 0) // send control data in blanking interval
|
||||||
|
begin
|
||||||
|
case (i_ctrl) // ctrl sequences (always have 7 transitions)
|
||||||
|
2'b00: o_tmds <= 10'b1101010100;
|
||||||
|
2'b01: o_tmds <= 10'b0010101011;
|
||||||
|
2'b10: o_tmds <= 10'b0101010100;
|
||||||
|
default: o_tmds <= 10'b1010101011;
|
||||||
|
endcase
|
||||||
|
bias <= 5'sb00000;
|
||||||
|
end
|
||||||
|
else // send pixel colour data (at most 5 transitions)
|
||||||
|
begin
|
||||||
|
if (bias == 0 || balance == 0) // no prior bias or disparity
|
||||||
|
begin
|
||||||
|
if (enc_qm[8] == 0)
|
||||||
|
begin
|
||||||
|
$display("\t%d %b %d, %d, A1", i_data, enc_qm, ones, bias);
|
||||||
|
o_tmds[9:0] <= {2'b10, ~enc_qm[7:0]};
|
||||||
|
bias <= bias - balance;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
$display("\t%d %b %d, %d, A0", i_data, enc_qm, ones, bias);
|
||||||
|
o_tmds[9:0] <= {2'b01, enc_qm[7:0]};
|
||||||
|
bias <= bias + balance;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
else if ((bias > 0 && balance > 0) || (bias < 0 && balance < 0))
|
||||||
|
begin
|
||||||
|
$display("\t%d %b %d, %d, B1", i_data, enc_qm, ones, bias);
|
||||||
|
o_tmds[9:0] <= {1'b1, enc_qm[8], ~enc_qm[7:0]};
|
||||||
|
bias <= bias + {3'b0, enc_qm[8], 1'b0} - balance;
|
||||||
|
end
|
||||||
|
else
|
||||||
|
begin
|
||||||
|
$display("\t%d %b %d, %d, B0", i_data, enc_qm, ones, bias);
|
||||||
|
o_tmds[9:0] <= {1'b0, enc_qm[8], enc_qm[7:0]};
|
||||||
|
bias <= bias - {3'b0, ~enc_qm[8], 1'b0} + balance;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
endmodule
|
||||||
|
|
@ -1,7 +1,7 @@
|
||||||
#set_property IOSTANDARD LVCMOS33 [get_ports {btns_4bits_tri_i_0}]
|
set_property IOSTANDARD LVCMOS33 [get_ports {btns_4bits_tri_i[0]}]
|
||||||
#set_property IOSTANDARD LVCMOS33 [get_ports {btns_4bits_tri_i_1}]
|
set_property IOSTANDARD LVCMOS33 [get_ports {btns_4bits_tri_i[1]}]
|
||||||
#set_property IOSTANDARD LVCMOS33 [get_ports {btns_4bits_tri_i_2}]
|
set_property IOSTANDARD LVCMOS33 [get_ports {btns_4bits_tri_i[2]}]
|
||||||
#set_property IOSTANDARD LVCMOS33 [get_ports {btns_4bits_tri_i_3}]
|
set_property IOSTANDARD LVCMOS33 [get_ports {btns_4bits_tri_i[3]}]
|
||||||
set_property IOSTANDARD LVCMOS33 [get_ports {leds_4bits_tri_o_0}]
|
set_property IOSTANDARD LVCMOS33 [get_ports {leds_4bits_tri_o_0}]
|
||||||
set_property IOSTANDARD LVCMOS33 [get_ports {leds_4bits_tri_o_1}]
|
set_property IOSTANDARD LVCMOS33 [get_ports {leds_4bits_tri_o_1}]
|
||||||
set_property IOSTANDARD LVCMOS33 [get_ports {leds_4bits_tri_o_2}]
|
set_property IOSTANDARD LVCMOS33 [get_ports {leds_4bits_tri_o_2}]
|
||||||
|
|
@ -117,10 +117,10 @@ set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_in_ddc_sda_io}]
|
||||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sdada_out_i}]
|
#set_property IOSTANDARD LVCMOS33 [get_ports {sdada_out_i}]
|
||||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sdata_in_i}]
|
#set_property IOSTANDARD LVCMOS33 [get_ports {sdata_in_i}]
|
||||||
|
|
||||||
#set_property PACKAGE_PIN D19 [get_ports {btns_4bits_tri_i_0}]
|
set_property PACKAGE_PIN D19 [get_ports {btns_4bits_tri_i[0]}]
|
||||||
#set_property PACKAGE_PIN D20 [get_ports {btns_4bits_tri_i_1}]
|
set_property PACKAGE_PIN D20 [get_ports {btns_4bits_tri_i[1]}]
|
||||||
#set_property PACKAGE_PIN L20 [get_ports {btns_4bits_tri_i_2}]
|
set_property PACKAGE_PIN L20 [get_ports {btns_4bits_tri_i[2]}]
|
||||||
#set_property PACKAGE_PIN L19 [get_ports {btns_4bits_tri_i_3}]
|
set_property PACKAGE_PIN L19 [get_ports {btns_4bits_tri_i[3]}]
|
||||||
set_property PACKAGE_PIN R14 [get_ports {leds_4bits_tri_o_0}]
|
set_property PACKAGE_PIN R14 [get_ports {leds_4bits_tri_o_0}]
|
||||||
set_property PACKAGE_PIN P14 [get_ports {leds_4bits_tri_o_1}]
|
set_property PACKAGE_PIN P14 [get_ports {leds_4bits_tri_o_1}]
|
||||||
set_property PACKAGE_PIN N16 [get_ports {leds_4bits_tri_o_2}]
|
set_property PACKAGE_PIN N16 [get_ports {leds_4bits_tri_o_2}]
|
||||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
Binary file not shown.
|
|
@ -1,93 +0,0 @@
|
||||||
module rgb_op0(
|
|
||||||
|
|
||||||
(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 iV ACTIVE_VIDEO" *) input wire iRGB_ACTIVE,
|
|
||||||
(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 iV DATA" *) input wire [23:0]iRGB_DATA ,
|
|
||||||
(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 iV HSYNC" *) input wire iRGB_HSYNC ,
|
|
||||||
(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 iV VSYNC" *) input wire iRGB_VSYNC ,
|
|
||||||
|
|
||||||
|
|
||||||
(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 oV ACTIVE_VIDEO" *) output wire oRGB_ACTIVE,
|
|
||||||
(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 oV DATA" *) output wire [23:0]oRGB_DATA ,
|
|
||||||
(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 oV HSYNC" *) output wire oRGB_HSYNC ,
|
|
||||||
(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 oV VSYNC" *) output wire oRGB_VSYNC ,
|
|
||||||
|
|
||||||
output wire [15:0] cnt_iac,
|
|
||||||
output wire [15:0] cnt_ihs,
|
|
||||||
output wire [15:0] cnt_ivs,
|
|
||||||
|
|
||||||
input wire [1:0] isel ,
|
|
||||||
input wire hdmi_in_aPixelClkLckd ,
|
|
||||||
input wire hdmi_out_aPixelClkLckd ,
|
|
||||||
output wire hdmi_in_arst ,
|
|
||||||
output wire hdmi_out_arst ,
|
|
||||||
input wire clk ,
|
|
||||||
input wire PixelClk ,
|
|
||||||
input wire tx_hpd ,
|
|
||||||
output wire rx_hpd
|
|
||||||
|
|
||||||
|
|
||||||
);
|
|
||||||
|
|
||||||
|
|
||||||
reg [ 7:0] r_hpd_fsm0=0;
|
|
||||||
|
|
||||||
reg [15:0] r_cnt_iac;
|
|
||||||
reg [15:0] r_cnt_ihs;
|
|
||||||
reg [15:0] r_cnt_ivs;
|
|
||||||
|
|
||||||
reg r_iRGB_ACTIVE;
|
|
||||||
reg r_iRGB_HSYNC ;
|
|
||||||
reg r_iRGB_VSYNC ;
|
|
||||||
|
|
||||||
assign cnt_iac = r_cnt_iac;
|
|
||||||
assign cnt_ihs = r_cnt_ihs;
|
|
||||||
assign cnt_ivs = r_cnt_ivs;
|
|
||||||
|
|
||||||
always@(posedge PixelClk ) begin
|
|
||||||
|
|
||||||
r_iRGB_ACTIVE <= iRGB_ACTIVE;
|
|
||||||
r_iRGB_HSYNC <= iRGB_HSYNC ;
|
|
||||||
r_iRGB_VSYNC <= iRGB_VSYNC ;
|
|
||||||
|
|
||||||
r_cnt_iac <= (~iRGB_ACTIVE)? 0: (&r_cnt_iac)? r_cnt_iac: r_cnt_iac+1;
|
|
||||||
r_cnt_ihs <= (~iRGB_HSYNC )? 0: (&r_cnt_ihs)? r_cnt_ihs: r_cnt_ihs+1;
|
|
||||||
r_cnt_ivs <= (~iRGB_VSYNC )? 0: (&r_cnt_ivs)? r_cnt_ivs: ( {r_iRGB_HSYNC,iRGB_HSYNC}==2'b01 )? r_cnt_ivs+1: r_cnt_ivs;
|
|
||||||
|
|
||||||
end
|
|
||||||
|
|
||||||
always@(posedge clk) begin
|
|
||||||
r_hpd_fsm0 <=
|
|
||||||
|
|
||||||
//delay done. check if hdmi_in is still locked
|
|
||||||
(&r_hpd_fsm0 && hdmi_in_aPixelClkLckd )? r_hpd_fsm0:
|
|
||||||
//if not locked goto 0 (retry)
|
|
||||||
(&r_hpd_fsm0 )? 0:
|
|
||||||
|
|
||||||
//start
|
|
||||||
(r_hpd_fsm0==0 )? 1:
|
|
||||||
|
|
||||||
//waits for hdmi_in
|
|
||||||
(r_hpd_fsm0==1 && hdmi_in_aPixelClkLckd )? 2:
|
|
||||||
|
|
||||||
//waits for hdmi_out
|
|
||||||
(r_hpd_fsm0==2 && hdmi_out_aPixelClkLckd && tx_hpd)? 3:
|
|
||||||
|
|
||||||
//delay, so that retry is not so quick
|
|
||||||
(r_hpd_fsm0>=3 )? r_hpd_fsm0+1:
|
|
||||||
|
|
||||||
r_hpd_fsm0;
|
|
||||||
|
|
||||||
end
|
|
||||||
|
|
||||||
assign hdmi_in_arst = (r_hpd_fsm0>=1)? 0: 1;
|
|
||||||
assign rx_hpd = (r_hpd_fsm0>=1)? 1: 0;
|
|
||||||
assign hdmi_out_arst = (r_hpd_fsm0>=2)? 0: 1;
|
|
||||||
|
|
||||||
assign oRGB_ACTIVE = iRGB_ACTIVE;
|
|
||||||
assign oRGB_DATA[8*0+:8] =(isel[0])? ~iRGB_DATA[8*0+:8] : iRGB_DATA[8*0+:8];
|
|
||||||
assign oRGB_DATA[8*1+:8] =(isel[0])? ~iRGB_DATA[8*1+:8] : iRGB_DATA[8*1+:8];
|
|
||||||
assign oRGB_DATA[8*2+:8] =(isel[0])? ~iRGB_DATA[8*2+:8] : iRGB_DATA[8*2+:8];
|
|
||||||
assign oRGB_HSYNC = iRGB_HSYNC ;
|
|
||||||
assign oRGB_VSYNC = iRGB_VSYNC ;
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
Loading…
Reference in New Issue