diff --git a/hdmi-out-test/digilent.ipdefs b/hdmi-out-test/digilent.ipdefs deleted file mode 160000 index 7a5edbe..0000000 --- a/hdmi-out-test/digilent.ipdefs +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 7a5edbe128009522608a67c76e5346edbcf95d95 diff --git a/hdmi-out-test/docs/pg016_v_tc.pdf b/hdmi-out-test/docs/pg016_v_tc.pdf deleted file mode 100644 index 58cc8e5..0000000 Binary files a/hdmi-out-test/docs/pg016_v_tc.pdf and /dev/null differ diff --git a/hdmi-out-test/docs/pg044_v_axis_vid_out.pdf b/hdmi-out-test/docs/pg044_v_axis_vid_out.pdf deleted file mode 100644 index 876163a..0000000 Binary files a/hdmi-out-test/docs/pg044_v_axis_vid_out.pdf and /dev/null differ diff --git a/hdmi-out-test/docs/pg103-v-tpg-en-us-8.2.pdf b/hdmi-out-test/docs/pg103-v-tpg-en-us-8.2.pdf deleted file mode 100644 index e5ee102..0000000 Binary files a/hdmi-out-test/docs/pg103-v-tpg-en-us-8.2.pdf and /dev/null differ diff --git a/hdmi-out-test/design_1_wrapper.xsa b/hdmi-out-test/dvi_top.xsa similarity index 79% rename from hdmi-out-test/design_1_wrapper.xsa rename to hdmi-out-test/dvi_top.xsa index f0e7116..cb183fc 100644 Binary files a/hdmi-out-test/design_1_wrapper.xsa and b/hdmi-out-test/dvi_top.xsa differ diff --git a/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/component.xml b/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/component.xml deleted file mode 100644 index 51b1553..0000000 --- a/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/component.xml +++ /dev/null @@ -1,1498 +0,0 @@ - - - digilentinc.com - user - d_axi_i2s_audio - 2.0 - - - AXI_L - - - - - - - - - AWADDR - - - AXI_L_awaddr - - - - - AWPROT - - - AXI_L_awprot - - - - - AWVALID - - - AXI_L_awvalid - - - - - AWREADY - - - AXI_L_awready - - - - - WDATA - - - AXI_L_wdata - - - - - WSTRB - - - AXI_L_wstrb - - - - - WVALID - - - AXI_L_wvalid - - - - - WREADY - - - AXI_L_wready - - - - - BRESP - - - AXI_L_bresp - - - - - BVALID - - - AXI_L_bvalid - - - - - BREADY - - - AXI_L_bready - - - - - ARADDR - - - AXI_L_araddr - - - - - ARPROT - - - AXI_L_arprot - - - - - ARVALID - - - AXI_L_arvalid - - - - - ARREADY - - - AXI_L_arready - - - - - RDATA - - - AXI_L_rdata - - - - - RRESP - - - AXI_L_rresp - - - - - RVALID - - - AXI_L_rvalid - - - - - RREADY - - - AXI_L_rready - - - - - - WIZ.DATA_WIDTH - 32 - - - WIZ.NUM_REG - 10 - - - SUPPORTS_NARROW_BURST - 0 - - - - - AXI_L_RST - - - - - - - RST - - - AXI_L_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - AXI_L_CLK - - - - - - - CLK - - - AXI_L_aclk - - - - - - ASSOCIATED_BUSIF - AXI_L - - - ASSOCIATED_RESET - axi_l_aresetn - - - - - AXI_MM2S - AXI_MM2S - - - - - - - TKEEP - - - S_AXIS_MM2S_TKEEP - - - - - TLAST - - - S_AXIS_MM2S_TLAST - - - - - TREADY - - - S_AXIS_MM2S_TREADY - - - - - TDATA - - - S_AXIS_MM2S_TDATA - - - - - TVALID - - - S_AXIS_MM2S_TVALID - - - - - - - false - - - - - - AXI_S2MM - AXI_S2MM - - - - - - - TVALID - - - M_AXIS_S2MM_TVALID - - - - - TKEEP - - - M_AXIS_S2MM_TKEEP - - - - - TREADY - - - M_AXIS_S2MM_TREADY - - - - - TLAST - - - M_AXIS_S2MM_TLAST - - - - - TDATA - - - M_AXIS_S2MM_TDATA - - - - - - - false - - - - - - AXI_S2MM_CLK - AXI_S2MM_CLK - - - - - - - CLK - - - M_AXIS_S2MM_ACLK - - - - - - ASSOCIATED_BUSIF - AXI_S2MM - - - ASSOCIATED_RESET - M_AXIS_S2MM_ARESETN - - - - - - false - - - - - - AXI_MM2S_CLK - - - - - - - CLK - - - S_AXIS_MM2S_ACLK - - - - - - ASSOCIATED_BUSIF - AXI_MM2S - - - ASSOCIATED_RESET - S_AXIS_MM2S_ARESETN - - - - - - false - - - - - - AXI_MM2S_RST - - - - - - - RST - - - S_AXIS_MM2S_ARESETN - - - - - - POLARITY - ACTIVE_LOW - - - - - - false - - - - - - AXI_S2MM_RST - - - - - - - RST - - - M_AXIS_S2MM_ARESETN - - - - - - POLARITY - ACTIVE_LOW - - - - - - false - - - - - - - - AXI_L - - AXI_L_reg - 0 - 4096 - 32 - register - - - OFFSET_BASE_PARAM - C_AXI_L_BASEADDR - - - OFFSET_HIGH_PARAM - C_AXI_L_HIGHADDR - - - - - - - - - xilinx_vhdlsynthesis - VHDL Synthesis - vhdlSource:vivado.xilinx.com:synthesis - vhdl - d_axi_i2s_audio_v2_0 - - xilinx_vhdlsynthesis_view_fileset - - - - viewChecksum - 85e9db01 - - - - - xilinx_vhdlbehavioralsimulation - VHDL Simulation - vhdlSource:vivado.xilinx.com:simulation - vhdl - d_axi_i2s_audio_v2_0 - - xilinx_vhdlbehavioralsimulation_view_fileset - - - - viewChecksum - 3c33b810 - - - - - xilinx_xpgui - UI Layout - :vivado.xilinx.com:xgui.ui - - xilinx_xpgui_view_fileset - - - - viewChecksum - 8ebd6a31 - - - - - - - BCLK_O - - out - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - BCLK_I - - in - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0 - - - - - - false - - - - - - BCLK_T - - out - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - - false - - - - - - LRCLK_O - - out - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - LRCLK_I - - in - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0 - - - - - - false - - - - - - LRCLK_T - - out - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - - false - - - - - - MCLK_O - - out - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - SDATA_I - - in - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - SDATA_O - - out - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - CLK_100MHZ_I - - in - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - S_AXIS_MM2S_ACLK - - in - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0 - - - - - S_AXIS_MM2S_ARESETN - - in - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 1 - - - - - S_AXIS_MM2S_TREADY - - out - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - S_AXIS_MM2S_TDATA - - in - - 31 - 0 - - - - std_logic_vector - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - S_AXIS_MM2S_TKEEP - - in - - 3 - 0 - - - - std_logic_vector - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - S_AXIS_MM2S_TLAST - - in - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - S_AXIS_MM2S_TVALID - - in - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - M_AXIS_S2MM_ACLK - - in - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0 - - - - - M_AXIS_S2MM_ARESETN - - in - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 1 - - - - - M_AXIS_S2MM_TVALID - - out - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - M_AXIS_S2MM_TDATA - - out - - 31 - 0 - - - - std_logic_vector - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - M_AXIS_S2MM_TKEEP - - out - - 3 - 0 - - - - std_logic_vector - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - M_AXIS_S2MM_TLAST - - out - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - M_AXIS_S2MM_TREADY - - in - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - AXI_L_aclk - - in - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - AXI_L_aresetn - - in - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - AXI_L_awaddr - - in - - 5 - 0 - - - - std_logic_vector - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0 - - - - - AXI_L_awprot - - in - - 2 - 0 - - - - std_logic_vector - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0 - - - - - AXI_L_awvalid - - in - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0 - - - - - AXI_L_awready - - out - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - AXI_L_wdata - - in - - 31 - 0 - - - - std_logic_vector - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0 - - - - - AXI_L_wstrb - - in - - 3 - 0 - - - - std_logic_vector - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - AXI_L_wvalid - - in - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0 - - - - - AXI_L_wready - - out - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - AXI_L_bresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - AXI_L_bvalid - - out - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - AXI_L_bready - - in - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0 - - - - - AXI_L_araddr - - in - - 5 - 0 - - - - std_logic_vector - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0 - - - - - AXI_L_arprot - - in - - 2 - 0 - - - - std_logic_vector - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0 - - - - - AXI_L_arvalid - - in - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0 - - - - - AXI_L_arready - - out - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - AXI_L_rdata - - out - - 31 - 0 - - - - std_logic_vector - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - AXI_L_rresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - AXI_L_rvalid - - out - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - AXI_L_rready - - in - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0 - - - - - - - C_DATA_WIDTH - C Data Width - 24 - - - C_AXI_STREAM_DATA_WIDTH - C Axi Stream Data Width - 32 - - - C_AXI_L_DATA_WIDTH - C Axi L Data Width - 32 - - - C_AXI_L_ADDR_WIDTH - C Axi L Addr Width - 6 - - - - - - choice_list_6fc15197 - 32 - - - choice_list_9d8b0d81 - ACTIVE_HIGH - ACTIVE_LOW - - - choice_pairs_ce1226b1 - 1 - 0 - - - - - xilinx_vhdlsynthesis_view_fileset - - src/d_axi_i2s_audio.xdc - xdc - USED_IN_implementation - USED_IN_synthesis - - - src/rst_sync.vhd - vhdlSource - - - src/i2s_ctl.vhd - vhdlSource - - - src/DCM.vhd - vhdlSource - - - src/Sync_ff.vhd - vhdlSource - - - src/i2s_stream.vhd - vhdlSource - - - src/i2s_rx_tx.vhd - vhdlSource - - - src/d_axi_i2s_audio_v2_0_AXI_L.vhd - vhdlSource - - - src/d_axi_i2s_audio_v2_0.vhd - vhdlSource - - - src/fifo_32/fifo_32.xci - xci - - - src/fifo_4/fifo_4.xci - xci - - - - xilinx_vhdlbehavioralsimulation_view_fileset - - src/fifo_32/fifo_32.xci - xci - - - src/fifo_4/fifo_4.xci - xci - - - src/rst_sync.vhd - vhdlSource - USED_IN_ipstatic - - - src/i2s_ctl.vhd - vhdlSource - USED_IN_ipstatic - - - src/DCM.vhd - vhdlSource - USED_IN_ipstatic - - - src/Sync_ff.vhd - vhdlSource - USED_IN_ipstatic - - - src/i2s_stream.vhd - vhdlSource - USED_IN_ipstatic - - - src/i2s_rx_tx.vhd - vhdlSource - USED_IN_ipstatic - - - src/d_axi_i2s_audio_v2_0_AXI_L.vhd - vhdlSource - USED_IN_ipstatic - - - src/d_axi_i2s_audio_v2_0.vhd - vhdlSource - USED_IN_ipstatic - - - - xilinx_xpgui_view_fileset - - xgui/d_axi_i2s_audio_v2_0.tcl - tclSource - CHECKSUM_33752f34 - XGUI_VERSION_2 - - - - I2S Controller AXI_Lite AXI-Stream - - - C_AXI_L_BASEADDR - C AXI_L BASEADDR - 0xFFFFFFFF - - - - false - - - - - - C_AXI_L_HIGHADDR - C AXI_L HIGHADDR - 0x00000000 - - - - false - - - - - - Component_Name - Component Name - d_axi_i2s_audio_v2_0 - - - C_DATA_WIDTH - C Data Width - 24 - - - C_AXI_STREAM_DATA_WIDTH - C Axi Stream Data Width - 32 - - - C_AXI_L_DATA_WIDTH - C Axi L Data Width - 32 - - - C_AXI_L_ADDR_WIDTH - C Axi L Addr Width - 6 - - - ENABLE_STREAM - Enable Stream - false - - - BIDIRECTIONAL_CLK - Enable Bidirectional Clock - false - - - - - - zynq - artix7{c7a200tsbg484-1} - kintex7 - - - AXI_Peripheral - - d_axi_i2s_audio_v2_0 - Digilent, Inc. - http://www.digilentinc.com - 52 - 2016-08-09T18:41:44Z - - C:/Users/nagy/Work/Atlys2/atlys2bist/proj - C:/Work/Github/NexysVideo/Projects/dma/repo/local/ip/d_axi_i2s_audio_v2_0 - - - - 2015.4 - - - - - - - - - diff --git a/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/DCM.vhd b/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/DCM.vhd deleted file mode 100644 index 666bc4e..0000000 --- a/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/DCM.vhd +++ /dev/null @@ -1,189 +0,0 @@ --- file: DCM.vhd --- --- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- ------------------------------------------------------------------------------- --- User entered comments ------------------------------------------------------------------------------- --- None --- ------------------------------------------------------------------------------- --- "Output Output Phase Duty Pk-to-Pk Phase" --- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" ------------------------------------------------------------------------------- --- CLK_OUT1____12.289______0.000______50.0______335.213____300.046 --- ------------------------------------------------------------------------------- --- "Input Clock Freq (MHz) Input Jitter (UI)" ------------------------------------------------------------------------------- --- __primary_________100.000____________0.010 - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; -use ieee.numeric_std.all; - -library unisim; -use unisim.vcomponents.all; - -entity DCM is -port - (-- Clock in ports - CLK_100 : in std_logic; - -- Clock out ports - CLK_12_288 : out std_logic; - -- Status and control signals - RESET : in std_logic; - LOCKED : out std_logic - ); -end DCM; - -architecture xilinx of DCM is - attribute CORE_GENERATION_INFO : string; - attribute CORE_GENERATION_INFO of xilinx : architecture is "DCM,clk_wiz_v3_6,{component_name=DCM,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}"; - -- Input clock buffering / unused connectors - signal clkin1 : std_logic; - -- Output clock buffering / unused connectors - signal clkfbout : std_logic; - signal clkfbout_buf : std_logic; - signal clkfboutb_unused : std_logic; - signal clkout0 : std_logic; - signal clkout0b_unused : std_logic; - signal clkout1_unused : std_logic; - signal clkout1b_unused : std_logic; - signal clkout2_unused : std_logic; - signal clkout2b_unused : std_logic; - signal clkout3_unused : std_logic; - signal clkout3b_unused : std_logic; - signal clkout4_unused : std_logic; - signal clkout5_unused : std_logic; - signal clkout6_unused : std_logic; - -- Dynamic programming unused signals - signal do_unused : std_logic_vector(15 downto 0); - signal drdy_unused : std_logic; - -- Dynamic phase shift unused signals - signal psdone_unused : std_logic; - -- Unused status signals - signal clkfbstopped_unused : std_logic; - signal clkinstopped_unused : std_logic; -begin - - - -- Input buffering - -------------------------------------- - clkin1 <= CLK_100; - - - -- Clocking primitive - -------------------------------------- - -- Instantiation of the MMCM primitive - -- * Unused inputs are tied off - -- * Unused outputs are labeled unused - plle2_adv_inst : PLLE2_ADV - generic map - (BANDWIDTH => "OPTIMIZED", - COMPENSATION => "ZHOLD", - DIVCLK_DIVIDE => 5, - CLKFBOUT_MULT => 51, - CLKFBOUT_PHASE => 0.000, - CLKOUT0_DIVIDE => 83, - CLKOUT0_PHASE => 0.000, - CLKOUT0_DUTY_CYCLE => 0.500, - CLKIN1_PERIOD => 10.000, - REF_JITTER1 => 0.010) - port map - -- Output clocks - (CLKFBOUT => clkfbout, - CLKOUT0 => clkout0, - CLKOUT1 => clkout1_unused, - CLKOUT2 => clkout2_unused, - CLKOUT3 => clkout3_unused, - CLKOUT4 => clkout4_unused, - CLKOUT5 => clkout5_unused, - -- Input clock control - CLKFBIN => clkfbout, - CLKIN1 => clkin1, - CLKIN2 => '0', - -- Tied to always select the primary input clock - CLKINSEL => '1', - -- Ports for dynamic reconfiguration - DADDR => (others => '0'), - DCLK => '0', - DEN => '0', - DI => (others => '0'), - DO => do_unused, - DRDY => drdy_unused, - DWE => '0', - -- Other control and status signals - LOCKED => LOCKED, - PWRDWN => '0', - RST => RESET); - - -- Output buffering - ------------------------------------- - - --- -- Output buffering --- ------------------------------------- --- clkf_buf : BUFG --- port map --- (O => clkfbout_buf, --- I => clkfbout); --- --- - clkout1_buf : BUFG - port map - (O => CLK_12_288, - I => clkout0); - ---clkfbout_buf <= clkfbout; ---CLK_12_288 <= clkout0; - - - -end xilinx; diff --git a/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/Div_by_4.vhd b/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/Div_by_4.vhd deleted file mode 100644 index 06ad645..0000000 --- a/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/Div_by_4.vhd +++ /dev/null @@ -1,66 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 15:49:17 04/02/2014 --- Design Name: --- Module Name: Div_by_4 - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity Div_by_4 is - Port - ( - CE_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - DIV_O : out STD_LOGIC - ); -end Div_by_4; - -architecture Behavioral of Div_by_4 is - -signal cnt : integer range 0 to 2 :=0; -signal clk_div : STD_LOGIC := '0'; - -begin - -process (CLK_I) -begin - if (CLK_I'event and CLK_I = '1') then - if (CE_I = '1') then - cnt <= cnt + 1; - if cnt = 2 then - cnt <= 0; - clk_div <= not clk_div; - end if; - else - cnt <= 0; - end if; - end if; -end process; - -DIV_O <= clk_div; - -end Behavioral; - diff --git a/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/Sync_ff.vhd b/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/Sync_ff.vhd deleted file mode 100644 index 24ac540..0000000 --- a/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/Sync_ff.vhd +++ /dev/null @@ -1,61 +0,0 @@ -------------------------------------------------------------------------------- --- --- COPYRIGHT (C) 2012, Digilent RO. All rights reserved --- -------------------------------------------------------------------------------- --- FILE NAME : Sync_ff.vhd --- MODULE NAME : Synchornisation Flip-Flops --- AUTHOR : Hegbeli Ciprian --- AUTHOR'S EMAIL : ciprian.hegbeli@digilent.ro -------------------------------------------------------------------------------- --- REVISION HISTORY --- VERSION DATE AUTHOR DESCRIPTION --- 1.0 2014-04-02 CiprianH Created -------------------------------------------------------------------------------- --- KEYWORDS : Sync -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - ------------------------------------------------------------------------- --- Module Declaration ------------------------------------------------------------------------- -entity Sync_ff is - Port ( - -- Input Clock - CLK : in STD_LOGIC; - -- Asynchorn signal - D_I : in STD_LOGIC; - -- Sync signal - Q_O : out STD_LOGIC - ); -end Sync_ff; - -architecture Behavioral of Sync_ff is - ------------------------------------------------------------------------- --- Signal Declarations ------------------------------------------------------------------------- -signal sreg : std_logic_vector(1 downto 0); - -attribute ASYNC_REG : string; -attribute ASYNC_REG of sreg : signal is "TRUE"; - -attribute TIG : string; -attribute TIG of D_I: signal is "TRUE"; - -begin - ------------------------------------------------------------------------- --- Output synchro with second CLK ------------------------------------------------------------------------- -sync_b_proc_2: process(CLK) -begin - if rising_edge(CLK) then - Q_O <= sreg(1); - sreg <= sreg(0) & D_I; - end if; -end process; - -end Behavioral; - diff --git a/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/d_axi_i2s_audio.xdc b/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/d_axi_i2s_audio.xdc deleted file mode 100644 index a06ec94..0000000 --- a/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/d_axi_i2s_audio.xdc +++ /dev/null @@ -1,6 +0,0 @@ -set_false_path -through [get_pins -filter {NAME =~ */Inst_I2sCtl/Inst_SyncBit_*/sreg_reg[0]/D} -hier] -set_false_path -through [get_pins -filter {NAME =~ */Inst_I2sCtl/Inst_Rst_Sync*/FDRE_inst_*/PRE} -hier] - -set_property ASYNC_REG true [get_cells -filter {NAME =~ */Inst_I2sCtl/Inst_Rst_Sync*} -hier] - - diff --git a/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/d_axi_i2s_audio_v2_0.vhd b/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/d_axi_i2s_audio_v2_0.vhd deleted file mode 100644 index 6997460..0000000 --- a/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/d_axi_i2s_audio_v2_0.vhd +++ /dev/null @@ -1,204 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -entity d_axi_i2s_audio_v2_0 is - generic ( - C_DATA_WIDTH : integer := 24; - - -- AXI4-Stream parameter - C_AXI_STREAM_DATA_WIDTH : integer := 32; - - -- Parameters of Axi Slave Bus Interface AXI_L - C_AXI_L_DATA_WIDTH : integer := 32; - C_AXI_L_ADDR_WIDTH : integer := 6 - ); - port ( - -- I2S - BCLK_O : out std_logic; - BCLK_I : in std_logic; - BCLK_T : out std_logic; - LRCLK_O : out std_logic; - LRCLK_I : in std_logic; - LRCLK_T : out std_logic; - MCLK_O : out std_logic; - SDATA_I : in std_logic; - SDATA_O : out std_logic; - CLK_100MHZ_I : in std_logic; - - -- AXI4-Stream - S_AXIS_MM2S_ACLK : in std_logic; - S_AXIS_MM2S_ARESETN : in std_logic; - S_AXIS_MM2S_TREADY : out std_logic; - S_AXIS_MM2S_TDATA : in std_logic_vector(C_AXI_STREAM_DATA_WIDTH-1 downto 0); - S_AXIS_MM2S_TKEEP : in std_logic_vector((C_AXI_STREAM_DATA_WIDTH/8)-1 downto 0); - S_AXIS_MM2S_TLAST : in std_logic; - S_AXIS_MM2S_TVALID : in std_logic; - - M_AXIS_S2MM_ACLK : in std_logic; - M_AXIS_S2MM_ARESETN : in std_logic; - M_AXIS_S2MM_TVALID : out std_logic; - M_AXIS_S2MM_TDATA : out std_logic_vector(C_AXI_STREAM_DATA_WIDTH-1 downto 0); - M_AXIS_S2MM_TKEEP : out std_logic_vector((C_AXI_STREAM_DATA_WIDTH/8)-1 downto 0); - M_AXIS_S2MM_TLAST : out std_logic; - M_AXIS_S2MM_TREADY : in std_logic; - - - -- Ports of Axi Slave Bus Interface AXI_L - AXI_L_aclk : in std_logic; - AXI_L_aresetn : in std_logic; - AXI_L_awaddr : in std_logic_vector(C_AXI_L_ADDR_WIDTH-1 downto 0); - AXI_L_awprot : in std_logic_vector(2 downto 0); - AXI_L_awvalid : in std_logic; - AXI_L_awready : out std_logic; - AXI_L_wdata : in std_logic_vector(C_AXI_L_DATA_WIDTH-1 downto 0); - AXI_L_wstrb : in std_logic_vector((C_AXI_L_DATA_WIDTH/8)-1 downto 0); - AXI_L_wvalid : in std_logic; - AXI_L_wready : out std_logic; - AXI_L_bresp : out std_logic_vector(1 downto 0); - AXI_L_bvalid : out std_logic; - AXI_L_bready : in std_logic; - AXI_L_araddr : in std_logic_vector(C_AXI_L_ADDR_WIDTH-1 downto 0); - AXI_L_arprot : in std_logic_vector(2 downto 0); - AXI_L_arvalid : in std_logic; - AXI_L_arready : out std_logic; - AXI_L_rdata : out std_logic_vector(C_AXI_L_DATA_WIDTH-1 downto 0); - AXI_L_rresp : out std_logic_vector(1 downto 0); - AXI_L_rvalid : out std_logic; - AXI_L_rready : in std_logic - ); -end d_axi_i2s_audio_v2_0; - -architecture arch_imp of d_axi_i2s_audio_v2_0 is - - -- component declaration - component d_axi_i2s_audio_v2_0_AXI_L is - generic ( - -- Stream width constant - C_AXI_STREAM_DATA_WIDTH : integer := 32; - -- audio data width constant - C_DATA_WIDTH : integer := 24; - C_S_AXI_DATA_WIDTH : integer := 32; - C_S_AXI_ADDR_WIDTH : integer := 6 - ); - port ( - -- I2S - BCLK_O : out std_logic; - BCLK_I : in std_logic; - BCLK_T : out std_logic; - LRCLK_O : out std_logic; - LRCLK_I : in std_logic; - LRCLK_T : out std_logic; - MCLK_O : out std_logic; - SDATA_I : in std_logic; - SDATA_O : out std_logic; - CLK_100MHZ_I : in std_logic; - - -- AXI4-Stream - S_AXIS_MM2S_ACLK : in std_logic; - S_AXIS_MM2S_ARESETN : in std_logic; - S_AXIS_MM2S_TREADY : out std_logic; - S_AXIS_MM2S_TDATA : in std_logic_vector(C_AXI_STREAM_DATA_WIDTH-1 downto 0); - S_AXIS_MM2S_TKEEP : in std_logic_vector((C_AXI_STREAM_DATA_WIDTH/8)-1 downto 0); - S_AXIS_MM2S_TLAST : in std_logic; - S_AXIS_MM2S_TVALID : in std_logic; - - M_AXIS_S2MM_ACLK : in std_logic; - M_AXIS_S2MM_ARESETN : in std_logic; - M_AXIS_S2MM_TVALID : out std_logic; - M_AXIS_S2MM_TDATA : out std_logic_vector(C_AXI_STREAM_DATA_WIDTH-1 downto 0); - M_AXIS_S2MM_TKEEP : out std_logic_vector((C_AXI_STREAM_DATA_WIDTH/8)-1 downto 0); - M_AXIS_S2MM_TLAST : out std_logic; - M_AXIS_S2MM_TREADY : in std_logic; - - S_AXI_ACLK : in std_logic; - S_AXI_ARESETN : in std_logic; - S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); - S_AXI_AWPROT : in std_logic_vector(2 downto 0); - S_AXI_AWVALID : in std_logic; - S_AXI_AWREADY : out std_logic; - S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); - S_AXI_WVALID : in std_logic; - S_AXI_WREADY : out std_logic; - S_AXI_BRESP : out std_logic_vector(1 downto 0); - S_AXI_BVALID : out std_logic; - S_AXI_BREADY : in std_logic; - S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); - S_AXI_ARPROT : in std_logic_vector(2 downto 0); - S_AXI_ARVALID : in std_logic; - S_AXI_ARREADY : out std_logic; - S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - S_AXI_RRESP : out std_logic_vector(1 downto 0); - S_AXI_RVALID : out std_logic; - S_AXI_RREADY : in std_logic - ); - end component d_axi_i2s_audio_v2_0_AXI_L; - -begin - --- Instantiation of Axi Bus Interface AXI_L -d_axi_i2s_audio_v2_0_AXI_L_inst : d_axi_i2s_audio_v2_0_AXI_L - generic map ( - C_DATA_WIDTH => C_DATA_WIDTH, - C_AXI_STREAM_DATA_WIDTH => C_AXI_STREAM_DATA_WIDTH, - C_S_AXI_DATA_WIDTH => C_AXI_L_DATA_WIDTH, - C_S_AXI_ADDR_WIDTH => C_AXI_L_ADDR_WIDTH - ) - port map ( - BCLK_O => BCLK_O, - BCLK_I => BCLK_I, - BCLK_T => BCLK_T, - LRCLK_O => LRCLK_O, - LRCLK_I => LRCLK_I, - LRCLK_T => LRCLK_T, - MCLK_O => MCLK_O, - SDATA_I => SDATA_I, - SDATA_O => SDATA_O, - CLK_100MHZ_I => CLK_100MHZ_I, - - S_AXIS_MM2S_ACLK => S_AXIS_MM2S_ACLK, - S_AXIS_MM2S_ARESETN => S_AXIS_MM2S_ARESETN, - S_AXIS_MM2S_TREADY => S_AXIS_MM2S_TREADY, - S_AXIS_MM2S_TDATA => S_AXIS_MM2S_TDATA, - S_AXIS_MM2S_TKEEP => S_AXIS_MM2S_TKEEP, - S_AXIS_MM2S_TLAST => S_AXIS_MM2S_TLAST, - S_AXIS_MM2S_TVALID => S_AXIS_MM2S_TVALID, - - M_AXIS_S2MM_ACLK => M_AXIS_S2MM_ACLK, - M_AXIS_S2MM_ARESETN => M_AXIS_S2MM_ARESETN, - M_AXIS_S2MM_TDATA => M_AXIS_S2MM_TDATA, - M_AXIS_S2MM_TLAST => M_AXIS_S2MM_TLAST, - M_AXIS_S2MM_TREADY => M_AXIS_S2MM_TREADY, - M_AXIS_S2MM_TKEEP => M_AXIS_S2MM_TKEEP, - M_AXIS_S2MM_TVALID => M_AXIS_S2MM_TVALID, - - S_AXI_ACLK => AXI_L_aclk, - S_AXI_ARESETN => AXI_L_aresetn, - S_AXI_AWADDR => AXI_L_awaddr, - S_AXI_AWPROT => AXI_L_awprot, - S_AXI_AWVALID => AXI_L_awvalid, - S_AXI_AWREADY => AXI_L_awready, - S_AXI_WDATA => AXI_L_wdata, - S_AXI_WSTRB => AXI_L_wstrb, - S_AXI_WVALID => AXI_L_wvalid, - S_AXI_WREADY => AXI_L_wready, - S_AXI_BRESP => AXI_L_bresp, - S_AXI_BVALID => AXI_L_bvalid, - S_AXI_BREADY => AXI_L_bready, - S_AXI_ARADDR => AXI_L_araddr, - S_AXI_ARPROT => AXI_L_arprot, - S_AXI_ARVALID => AXI_L_arvalid, - S_AXI_ARREADY => AXI_L_arready, - S_AXI_RDATA => AXI_L_rdata, - S_AXI_RRESP => AXI_L_rresp, - S_AXI_RVALID => AXI_L_rvalid, - S_AXI_RREADY => AXI_L_rready - ); - - -- Add user logic here - - -- User logic ends - -end arch_imp; diff --git a/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/d_axi_i2s_audio_v2_0_AXI_L.vhd b/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/d_axi_i2s_audio_v2_0_AXI_L.vhd deleted file mode 100644 index 779b8b7..0000000 --- a/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/d_axi_i2s_audio_v2_0_AXI_L.vhd +++ /dev/null @@ -1,781 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -entity d_axi_i2s_audio_v2_0_AXI_L is - generic ( - -- Stream width constant - C_AXI_STREAM_DATA_WIDTH : integer := 32; - -- audio data width constant - C_DATA_WIDTH : integer := 24; - -- Width of S_AXI data bus - C_S_AXI_DATA_WIDTH : integer := 32; - -- Width of S_AXI address bus - C_S_AXI_ADDR_WIDTH : integer := 6 - ); - port ( - - -- I2S - BCLK_O : out std_logic; - BCLK_I : in std_logic; - BCLK_T : out std_logic; - LRCLK_O : out std_logic; - LRCLK_I : in std_logic; - LRCLK_T : out std_logic; - MCLK_O : out std_logic; - SDATA_I : in std_logic; - SDATA_O : out std_logic; - CLK_100MHZ_I : in std_logic; - - -- AXI4-Stream - S_AXIS_MM2S_ACLK : in std_logic; - S_AXIS_MM2S_ARESETN : in std_logic; - S_AXIS_MM2S_TREADY : out std_logic; - S_AXIS_MM2S_TDATA : in std_logic_vector(C_AXI_STREAM_DATA_WIDTH-1 downto 0); - S_AXIS_MM2S_TKEEP : in std_logic_vector((C_AXI_STREAM_DATA_WIDTH/8)-1 downto 0); - S_AXIS_MM2S_TLAST : in std_logic; - S_AXIS_MM2S_TVALID : in std_logic; - - M_AXIS_S2MM_ACLK : in std_logic; - M_AXIS_S2MM_ARESETN : in std_logic; - M_AXIS_S2MM_TVALID : out std_logic; - M_AXIS_S2MM_TDATA : out std_logic_vector(C_AXI_STREAM_DATA_WIDTH-1 downto 0); - M_AXIS_S2MM_TKEEP : out std_logic_vector((C_AXI_STREAM_DATA_WIDTH/8)-1 downto 0); - M_AXIS_S2MM_TLAST : out std_logic; - M_AXIS_S2MM_TREADY : in std_logic; - - -- Global Clock Signal - S_AXI_ACLK : in std_logic; - -- Global Reset Signal. This Signal is Active LOW - S_AXI_ARESETN : in std_logic; - -- Write address (issued by master, acceped by Slave) - S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); - -- Write channel Protection type. This signal indicates the - -- privilege and security level of the transaction, and whether - -- the transaction is a data access or an instruction access. - S_AXI_AWPROT : in std_logic_vector(2 downto 0); - -- Write address valid. This signal indicates that the master signaling - -- valid write address and control information. - S_AXI_AWVALID : in std_logic; - -- Write address ready. This signal indicates that the slave is ready - -- to accept an address and associated control signals. - S_AXI_AWREADY : out std_logic; - -- Write data (issued by master, acceped by Slave) - S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - -- Write strobes. This signal indicates which byte lanes hold - -- valid data. There is one write strobe bit for each eight - -- bits of the write data bus. - S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); - -- Write valid. This signal indicates that valid write - -- data and strobes are available. - S_AXI_WVALID : in std_logic; - -- Write ready. This signal indicates that the slave - -- can accept the write data. - S_AXI_WREADY : out std_logic; - -- Write response. This signal indicates the status - -- of the write transaction. - S_AXI_BRESP : out std_logic_vector(1 downto 0); - -- Write response valid. This signal indicates that the channel - -- is signaling a valid write response. - S_AXI_BVALID : out std_logic; - -- Response ready. This signal indicates that the master - -- can accept a write response. - S_AXI_BREADY : in std_logic; - -- Read address (issued by master, acceped by Slave) - S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); - -- Protection type. This signal indicates the privilege - -- and security level of the transaction, and whether the - -- transaction is a data access or an instruction access. - S_AXI_ARPROT : in std_logic_vector(2 downto 0); - -- Read address valid. This signal indicates that the channel - -- is signaling valid read address and control information. - S_AXI_ARVALID : in std_logic; - -- Read address ready. This signal indicates that the slave is - -- ready to accept an address and associated control signals. - S_AXI_ARREADY : out std_logic; - -- Read data (issued by slave) - S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - -- Read response. This signal indicates the status of the - -- read transfer. - S_AXI_RRESP : out std_logic_vector(1 downto 0); - -- Read valid. This signal indicates that the channel is - -- signaling the required read data. - S_AXI_RVALID : out std_logic; - -- Read ready. This signal indicates that the master can - -- accept the read data and response information. - S_AXI_RREADY : in std_logic - ); -end d_axi_i2s_audio_v2_0_AXI_L; - -architecture arch_imp of d_axi_i2s_audio_v2_0_AXI_L is - --- Them main control component of the I2S protocol -component i2s_rx_tx - generic( - C_DATA_WIDTH : integer := 24); - port( - CLK_I : in std_logic; - RST_I : in std_logic; - TX_RS_I : in std_logic; - RX_RS_I : in std_logic; - TX_FIFO_RST_I : in std_logic; - TX_FIFO_D_I : in std_logic_vector(C_DATA_WIDTH-1 downto 0); - TX_FIFO_WR_EN_I : in std_logic; - RX_FIFO_RST_I : in std_logic; - RX_FIFO_D_O : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - RX_FIFO_RD_EN_I : in std_logic; - TX_FIFO_EMPTY_O : out std_logic; - TX_FIFO_FULL_O : out std_logic; - RX_FIFO_EMPTY_O : out std_logic; - RX_FIFO_FULL_O : out std_logic; - CLK_100MHZ_I : in std_logic; - CTL_MASTER_MODE_I : in std_logic; - - -- DBG - DBG_TX_FIFO_RST_I : out std_logic; - DBG_TX_FIFO_RD_EN_I : out std_logic; - DBG_TX_FIFO_WR_EN_I : out std_logic; - DBG_TX_FIFO_EMPTY_O : out std_logic; - DBG_TX_FIFO_FULL_O : out std_logic; - DBG_TX_FIFO_D_I : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - DBG_TX_FIFO_D_O : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - DBG_TX_RS_I : out std_logic; - - DBG_RX_FIFO_RST_I : out std_logic; - DBG_RX_FIFO_WR_EN_I : out std_logic; - DBG_RX_FIFO_RD_EN_I : out std_logic; - DBG_RX_FIFO_FULL_O : out std_logic; - DBG_RX_FIFO_EMPTY_O : out std_logic; - DBG_RX_FIFO_D_O : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - DBG_RX_FIFO_D_I : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - DBG_RX_RS_I : out std_logic; - - SAMPLING_RATE_I : in std_logic_vector(3 downto 0); - BCLK_O : out std_logic; - BCLK_I : in std_logic; - BCLK_T : out std_logic; - LRCLK_O : out std_logic; - LRCLK_I : in std_logic; - LRCLK_T : out std_logic; - MCLK_O : out std_logic; - SDATA_I : in std_logic; - SDATA_O : out std_logic); - end component; - - -- the stream module which controls the reciving and transmiting of data - -- on the AXI stream - component i2s_stream - generic( - C_AXI_STREAM_DATA_WIDTH : integer := 32; - C_DATA_WIDTH : integer := 24 - - ); - port( - TX_FIFO_FULL_I : in std_logic; - RX_FIFO_EMPTY_I : in std_logic; - TX_FIFO_D_O : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - RX_FIFO_D_I : in std_logic_vector(C_DATA_WIDTH-1 downto 0); - NR_OF_SMPL_I : in std_logic_vector(20 downto 0); - TX_STREAM_EN_I : in std_logic; - RX_STREAM_EN_I : in std_logic; - S_AXIS_MM2S_ACLK_I : in std_logic; - S_AXIS_MM2S_ARESETN : in std_logic; - S_AXIS_MM2S_TREADY_O : out std_logic; - S_AXIS_MM2S_TDATA_I : in std_logic_vector(C_AXI_STREAM_DATA_WIDTH-1 downto 0); - S_AXIS_MM2S_TLAST_I : in std_logic; - S_AXIS_MM2S_TVALID_I : in std_logic; - M_AXIS_S2MM_ACLK_I : in std_logic; - M_AXIS_S2MM_ARESETN : in std_logic; - M_AXIS_S2MM_TDATA_O : out std_logic_vector(C_AXI_STREAM_DATA_WIDTH-1 downto 0); - M_AXIS_S2MM_TLAST_O : out std_logic; - M_AXIS_S2MM_TVALID_O : out std_logic; - M_AXIS_S2MM_TREADY_I : in std_logic; - M_AXIS_S2MM_TKEEP_O : out std_logic_vector((C_AXI_STREAM_DATA_WIDTH/8)-1 downto 0) - ); - end component; - - -- Main AXI stream CLK divider (by 4) for generating the TX_FIFO_WR_EN_I signal - component Div_by_4 - port( - CE_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - DIV_O : out STD_LOGIC - ); - end component; - - ------------------------------------------ - -- Signals for user logic slave model s/w accessible register example - ------------------------------------------ - - -- I2S control signals - signal I2S_RST_I : std_logic; - signal TX_RS_I : std_logic; - signal RX_RS_I : std_logic; - - -- TX_FIFO siganals - signal TX_FIFO_RST_I : std_logic; - signal TX_FIFO_WR_EN_I : std_logic; - signal TX_FIFO_D_I : std_logic_vector(C_DATA_WIDTH-1 downto 0); - signal TX_FIFO_D_O : std_logic_vector(C_DATA_WIDTH-1 downto 0); - signal TX_FIFO_EMPTY_O : std_logic; - signal TX_FIFO_FULL_O : std_logic; - - -- RX_FIFO siganals - signal RX_FIFO_RST_I : std_logic; - signal RX_FIFO_RD_EN_I : std_logic; - signal RX_FIFO_D_O : std_logic_vector(C_DATA_WIDTH-1 downto 0); - signal RX_FIFO_EMPTY_O : std_logic; - signal RX_FIFO_FULL_O : std_logic; - - -- Clock control signals (BCLK/LRCLK) - signal CTL_MASTER_MODE_I : std_logic; - signal SAMPLING_RATE_I : std_logic_vector(3 downto 0); - - --Stream specific signals - signal NR_OF_SMPL_I : std_logic_vector(20 downto 0); - signal DIV_CE : std_logic; - signal TX_FIFO_WR_EN_STREAM_O : std_logic; - signal TX_STREAM_EN_I : std_logic; - signal RX_STREAM_EN_I : std_logic; - - - signal RxFifoRdEn : std_logic; - signal RxFifoRdEn_dly : std_logic; - signal TxFifoWrEn : std_logic; - signal TxFifoWrEn_dly : std_logic; - signal M_AXIS_S2MM_TVALID_int : std_logic; - - -- DBG - signal DBG_TX_FIFO_RST_I : std_logic; - signal DBG_TX_FIFO_RD_EN_I : std_logic; - signal DBG_TX_FIFO_WR_EN_I : std_logic; - signal DBG_TX_FIFO_EMPTY_O : std_logic; - signal DBG_TX_FIFO_FULL_O : std_logic; - signal DBG_TX_FIFO_D_O : std_logic_vector(C_DATA_WIDTH-1 downto 0); - signal DBG_TX_FIFO_D_I : std_logic_vector(C_DATA_WIDTH-1 downto 0); - - signal DBG_RX_FIFO_RST_I : std_logic; - signal DBG_RX_FIFO_WR_EN_I : std_logic; - signal DBG_RX_FIFO_RD_EN_I : std_logic; - signal DBG_RX_FIFO_FULL_O : std_logic; - signal DBG_RX_FIFO_EMPTY_O : std_logic; - signal DBG_RX_FIFO_D_O : std_logic_vector(C_DATA_WIDTH-1 downto 0); - signal DBG_RX_FIFO_D_I : std_logic_vector(C_DATA_WIDTH-1 downto 0); - - signal DBG_TX_RS_I : std_logic; - signal DBG_RX_RS_I : std_logic; - - -- AXI4LITE signals - signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); - signal axi_awready : std_logic; - signal axi_wready : std_logic; - signal axi_bresp : std_logic_vector(1 downto 0); - signal axi_bvalid : std_logic; - signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); - signal axi_arready : std_logic; - signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - signal axi_rresp : std_logic_vector(1 downto 0); - signal axi_rvalid : std_logic; - - -- Example-specific design signals - -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH - -- ADDR_LSB is used for addressing 32/64 bit registers/memories - -- ADDR_LSB = 2 for 32 bits (n downto 2) - -- ADDR_LSB = 3 for 64 bits (n downto 3) - constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1; - constant OPT_MEM_ADDR_BITS : integer := 3; - ------------------------------------------------ - ---- Signals for user logic register space example - -------------------------------------------------- - ---- Number of Slave Registers 10 - signal I2S_RESET_REG :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - signal I2S_TRANSFER_CONTROL_REG :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - signal I2S_FIFO_CONTROL_REG :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - signal I2S_DATA_IN_REG :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - signal I2S_DATA_OUT_REG :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - signal I2S_STATUS_REG :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - signal I2S_CLOCK_CONTROL_REG :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - signal I2S_PERIOD_COUNT_REG :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - signal I2S_STREAM_CONTROL_REG :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - signal slv_reg_rden : std_logic; - signal slv_reg_wren : std_logic; - signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - signal byte_index : integer; - - attribute KEEP : string; - - attribute KEEP of DBG_TX_FIFO_RST_I : signal is "TRUE"; - attribute KEEP of DBG_TX_FIFO_WR_EN_I : signal is "TRUE"; - attribute KEEP of DBG_TX_FIFO_RD_EN_I : signal is "TRUE"; - attribute KEEP of DBG_TX_FIFO_EMPTY_O : signal is "TRUE"; - attribute KEEP of DBG_TX_FIFO_FULL_O : signal is "TRUE"; - attribute KEEP of DBG_TX_FIFO_D_I : signal is "TRUE"; - attribute KEEP of DBG_TX_FIFO_D_O : signal is "TRUE"; - - attribute KEEP of DBG_RX_FIFO_RST_I : signal is "TRUE"; - attribute KEEP of DBG_RX_FIFO_WR_EN_I : signal is "TRUE"; - attribute KEEP of DBG_RX_FIFO_RD_EN_I : signal is "TRUE"; - attribute KEEP of DBG_RX_FIFO_FULL_O : signal is "TRUE"; - attribute KEEP of DBG_RX_FIFO_EMPTY_O : signal is "TRUE"; - attribute KEEP of DBG_RX_FIFO_D_I : signal is "TRUE"; - attribute KEEP of DBG_RX_FIFO_D_O : signal is "TRUE"; - - attribute KEEP of DBG_TX_RS_I : signal is "TRUE"; - attribute KEEP of DBG_RX_RS_I : signal is "TRUE"; - -begin - -- I/O Connections assignments - - S_AXI_AWREADY <= axi_awready; - S_AXI_WREADY <= axi_wready; - S_AXI_BRESP <= axi_bresp; - S_AXI_BVALID <= axi_bvalid; - S_AXI_ARREADY <= axi_arready; - S_AXI_RDATA <= axi_rdata; - S_AXI_RRESP <= axi_rresp; - S_AXI_RVALID <= axi_rvalid; - - I2S_RST_I <= I2S_RESET_REG(0); - TX_RS_I <= I2S_TRANSFER_CONTROL_REG(0); - RX_RS_I <= I2S_TRANSFER_CONTROL_REG(1); - TX_FIFO_WR_EN_I <= not TX_FIFO_FULL_O when (RX_STREAM_EN_I = '1' and S_AXIS_MM2S_TVALID = '1') else - TxFifoWrEn when (RX_STREAM_EN_I = '0') else - '0'; - RX_FIFO_RD_EN_I <= not RX_FIFO_EMPTY_O when (TX_STREAM_EN_I = '1' and M_AXIS_S2MM_TREADY = '1' and M_AXIS_S2MM_TVALID_int = '1') else - RxFifoRdEn when (TX_STREAM_EN_I = '0') else - '0'; - TX_FIFO_RST_I <= (not S_AXIS_MM2S_ARESETN) or I2S_FIFO_CONTROL_REG(30); - RX_FIFO_RST_I <= (not M_AXIS_S2MM_ARESETN) or I2S_FIFO_CONTROL_REG(31); - TX_FIFO_D_I <= TX_FIFO_D_O when RX_STREAM_EN_I = '1' else - I2S_DATA_IN_REG(C_DATA_WIDTH-1 downto 0); - SAMPLING_RATE_I <= I2S_CLOCK_CONTROL_REG(3 downto 0); - CTL_MASTER_MODE_I <= I2S_CLOCK_CONTROL_REG(16); - NR_OF_SMPL_I <= I2S_PERIOD_COUNT_REG(20 downto 0); - TX_STREAM_EN_I <= I2S_STREAM_CONTROL_REG(0); - RX_STREAM_EN_I <= I2S_STREAM_CONTROL_REG(1); - DIV_CE <= RX_STREAM_EN_I and (S_AXIS_MM2S_TVALID and not TX_FIFO_FULL_O); - --- DBG_RX_FIFO_D_O <= I2S_DATA_OUT_REG(C_DATA_WIDTH-1 downto 0); - - M_AXIS_S2MM_TVALID <= M_AXIS_S2MM_TVALID_int; - - RDWR_PULSE: process(S_AXI_ACLK) - begin - if rising_edge(S_AXI_ACLK) then - RxFifoRdEn_dly <= I2S_FIFO_CONTROL_REG(1); - TxFifoWrEn_dly <= I2S_FIFO_CONTROL_REG(0); - end if; - end process RDWR_PULSE; - - RxFifoRdEn <= I2S_FIFO_CONTROL_REG(1) and not RxFifoRdEn_dly; - TxFifoWrEn <= I2S_FIFO_CONTROL_REG(0) and not TxFifoWrEn_dly; - - ------------------------------------------------------------------------ - -- Instantiaton of the I2S controler - ------------------------------------------------------------------------ - Inst_I2sCtl: i2s_rx_tx - generic map( - C_DATA_WIDTH => C_DATA_WIDTH) - port map( - CLK_I => S_AXI_ACLK, - RST_I => I2S_RST_I, - TX_RS_I => TX_RS_I, - RX_RS_I => RX_RS_I, - TX_FIFO_RST_I => TX_FIFO_RST_I, - TX_FIFO_D_I => TX_FIFO_D_I, - TX_FIFO_WR_EN_I => TX_FIFO_WR_EN_I, - RX_FIFO_RST_I => RX_FIFO_RST_I, - RX_FIFO_D_O => RX_FIFO_D_O, - RX_FIFO_RD_EN_I => RX_FIFO_RD_EN_I, - TX_FIFO_EMPTY_O => TX_FIFO_EMPTY_O, - TX_FIFO_FULL_O => TX_FIFO_FULL_O, - RX_FIFO_EMPTY_O => RX_FIFO_EMPTY_O, - RX_FIFO_FULL_O => RX_FIFO_FULL_O, - CLK_100MHZ_I => CLK_100MHZ_I, - CTL_MASTER_MODE_I => CTL_MASTER_MODE_I, - - -- DBG - DBG_TX_FIFO_RST_I => DBG_TX_FIFO_RST_I, - DBG_TX_FIFO_RD_EN_I => DBG_TX_FIFO_RD_EN_I, - DBG_TX_FIFO_WR_EN_I => DBG_TX_FIFO_WR_EN_I, - DBG_TX_FIFO_EMPTY_O => DBG_TX_FIFO_EMPTY_O, - DBG_TX_FIFO_FULL_O => DBG_TX_FIFO_FULL_O, - DBG_TX_FIFO_D_O => DBG_TX_FIFO_D_O, - DBG_TX_FIFO_D_I => DBG_TX_FIFO_D_I, - DBG_TX_RS_I => DBG_TX_RS_I, - - DBG_RX_FIFO_RST_I => DBG_RX_FIFO_RST_I, - DBG_RX_FIFO_WR_EN_I => DBG_RX_FIFO_WR_EN_I, - DBG_RX_FIFO_RD_EN_I => DBG_RX_FIFO_RD_EN_I, - DBG_RX_FIFO_FULL_O => DBG_RX_FIFO_FULL_O, - DBG_RX_FIFO_EMPTY_O => DBG_RX_FIFO_EMPTY_O, - DBG_RX_FIFO_D_I => DBG_RX_FIFO_D_I, - DBG_RX_FIFO_D_O => DBG_RX_FIFO_D_O, - DBG_RX_RS_I => DBG_RX_RS_I, - - SAMPLING_RATE_I => SAMPLING_RATE_I, - BCLK_O => BCLK_O, - BCLK_I => BCLK_I, - BCLK_T => BCLK_T, - LRCLK_O => LRCLK_O, - LRCLK_I => LRCLK_I, - LRCLK_T => LRCLK_T, - MCLK_O => MCLK_O, - SDATA_I => SDATA_I, - SDATA_O => SDATA_O); - - - ------------------------------------------------------------------------ - -- Instantiaton of the AXI stream controler - ------------------------------------------------------------------------ - Inst_I2sStream: i2s_stream - generic map( - C_AXI_STREAM_DATA_WIDTH => C_AXI_STREAM_DATA_WIDTH, - C_DATA_WIDTH => C_DATA_WIDTH - ) - port map( - TX_FIFO_FULL_I => TX_FIFO_FULL_O, - RX_FIFO_EMPTY_I => RX_FIFO_EMPTY_O, - TX_FIFO_D_O => TX_FIFO_D_O, - RX_FIFO_D_I => RX_FIFO_D_O, - NR_OF_SMPL_I => NR_OF_SMPL_I, - TX_STREAM_EN_I => TX_STREAM_EN_I, - RX_STREAM_EN_I => RX_STREAM_EN_I, - S_AXIS_MM2S_ACLK_I => S_AXIS_MM2S_ACLK, - S_AXIS_MM2S_ARESETN => S_AXIS_MM2S_ARESETN, - S_AXIS_MM2S_TREADY_O => S_AXIS_MM2S_TREADY, - S_AXIS_MM2S_TDATA_I => S_AXIS_MM2S_TDATA, - S_AXIS_MM2S_TLAST_I => S_AXIS_MM2S_TLAST, - S_AXIS_MM2S_TVALID_I => S_AXIS_MM2S_TVALID, - M_AXIS_S2MM_ACLK_I => M_AXIS_S2MM_ACLK, - M_AXIS_S2MM_ARESETN => M_AXIS_S2MM_ARESETN, - M_AXIS_S2MM_TDATA_O => M_AXIS_S2MM_TDATA, - M_AXIS_S2MM_TLAST_O => M_AXIS_S2MM_TLAST, - M_AXIS_S2MM_TREADY_I => M_AXIS_S2MM_TREADY, - M_AXIS_S2MM_TKEEP_O => M_AXIS_S2MM_TKEEP, - M_AXIS_S2MM_TVALID_O => M_AXIS_S2MM_TVALID_int - ); - - -- Implement axi_awready generation - -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is - -- de-asserted when reset is low. - - process (S_AXI_ACLK) - begin - if rising_edge(S_AXI_ACLK) then - if S_AXI_ARESETN = '0' then - axi_awready <= '0'; - else - if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then - -- slave is ready to accept write address when - -- there is a valid write address and write data - -- on the write address and data bus. This design - -- expects no outstanding transactions. - axi_awready <= '1'; - else - axi_awready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement axi_awaddr latching - -- This process is used to latch the address when both - -- S_AXI_AWVALID and S_AXI_WVALID are valid. - - process (S_AXI_ACLK) - begin - if rising_edge(S_AXI_ACLK) then - if S_AXI_ARESETN = '0' then - axi_awaddr <= (others => '0'); - else - if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then - -- Write Address latching - axi_awaddr <= S_AXI_AWADDR; - end if; - end if; - end if; - end process; - - -- Implement axi_wready generation - -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is - -- de-asserted when reset is low. - - process (S_AXI_ACLK) - begin - if rising_edge(S_AXI_ACLK) then - if S_AXI_ARESETN = '0' then - axi_wready <= '0'; - else - if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then - -- slave is ready to accept write data when - -- there is a valid write address and write data - -- on the write address and data bus. This design - -- expects no outstanding transactions. - axi_wready <= '1'; - else - axi_wready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement memory mapped register select and write logic generation - -- The write data is accepted and written to memory mapped registers when - -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to - -- select byte enables of slave registers while writing. - -- These registers are cleared when reset (active low) is applied. - -- Slave register write enable is asserted when valid address and data are available - -- and the slave is ready to accept the write address and write data. - slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ; - - process (S_AXI_ACLK) - variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); - begin - if rising_edge(S_AXI_ACLK) then - if S_AXI_ARESETN = '0' then - I2S_RESET_REG <= (others => '0'); - I2S_TRANSFER_CONTROL_REG <= (others => '0'); - I2S_FIFO_CONTROL_REG <= (others => '0'); - I2S_DATA_IN_REG <= (others => '0'); - I2S_DATA_OUT_REG <= (others => '0'); - I2S_STATUS_REG <= (others => '0'); - I2S_CLOCK_CONTROL_REG <= (others => '0'); - I2S_PERIOD_COUNT_REG <= (others => '0'); - I2S_STREAM_CONTROL_REG <= (others => '0'); - slv_reg9 <= (others => '0'); - else - loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); - if (slv_reg_wren = '1') then - case loc_addr is - when b"0000" => - for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop - if ( S_AXI_WSTRB(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 0 - I2S_RESET_REG(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0001" => - for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop - if ( S_AXI_WSTRB(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 1 - I2S_TRANSFER_CONTROL_REG(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0010" => - for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop - if ( S_AXI_WSTRB(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 2 - I2S_FIFO_CONTROL_REG(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0011" => - for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop - if ( S_AXI_WSTRB(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 3 - I2S_DATA_IN_REG(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0110" => - for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop - if ( S_AXI_WSTRB(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 6 - I2S_CLOCK_CONTROL_REG(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0111" => - for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop - if ( S_AXI_WSTRB(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 7 - I2S_PERIOD_COUNT_REG(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1000" => - for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop - if ( S_AXI_WSTRB(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 8 - I2S_STREAM_CONTROL_REG(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1001" => - for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop - if ( S_AXI_WSTRB(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 9 - slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when others => - I2S_DATA_OUT_REG(31 downto 31-C_DATA_WIDTH) <= (others => '0'); - I2S_DATA_OUT_REG(C_DATA_WIDTH-1 downto 0) <= RX_FIFO_D_O; - I2S_STATUS_REG(0) <= TX_FIFO_EMPTY_O; - I2S_STATUS_REG(1) <= TX_FIFO_FULL_O; - I2S_STATUS_REG(15 downto 2) <= (others => '0'); - I2S_STATUS_REG(16) <= RX_FIFO_EMPTY_O; - I2S_STATUS_REG(17) <= RX_FIFO_FULL_O; - I2S_STATUS_REG(31 downto 18) <= (others => '0'); - end case; - end if; - I2S_DATA_OUT_REG(31 downto 31-C_DATA_WIDTH) <= (others => '0'); - I2S_DATA_OUT_REG(C_DATA_WIDTH-1 downto 0) <= RX_FIFO_D_O; - I2S_STATUS_REG(0) <= TX_FIFO_EMPTY_O; - I2S_STATUS_REG(1) <= TX_FIFO_FULL_O; - I2S_STATUS_REG(15 downto 2) <= (others => '0'); - I2S_STATUS_REG(16) <= RX_FIFO_EMPTY_O; - I2S_STATUS_REG(17) <= RX_FIFO_FULL_O; - I2S_STATUS_REG(31 downto 18) <= (others => '0'); - end if; - end if; - end process; - - -- Implement write response logic generation - -- The write response and response valid signals are asserted by the slave - -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. - -- This marks the acceptance of address and indicates the status of - -- write transaction. - - process (S_AXI_ACLK) - begin - if rising_edge(S_AXI_ACLK) then - if S_AXI_ARESETN = '0' then - axi_bvalid <= '0'; - axi_bresp <= "00"; --need to work more on the responses - else - if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then - axi_bvalid <= '1'; - axi_bresp <= "00"; - elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) - axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) - end if; - end if; - end if; - end process; - - -- Implement axi_arready generation - -- axi_arready is asserted for one S_AXI_ACLK clock cycle when - -- S_AXI_ARVALID is asserted. axi_awready is - -- de-asserted when reset (active low) is asserted. - -- The read address is also latched when S_AXI_ARVALID is - -- asserted. axi_araddr is reset to zero on reset assertion. - - process (S_AXI_ACLK) - begin - if rising_edge(S_AXI_ACLK) then - if S_AXI_ARESETN = '0' then - axi_arready <= '0'; - axi_araddr <= (others => '1'); - else - if (axi_arready = '0' and S_AXI_ARVALID = '1') then - -- indicates that the slave has acceped the valid read address - axi_arready <= '1'; - -- Read Address latching - axi_araddr <= S_AXI_ARADDR; - else - axi_arready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement axi_arvalid generation - -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_ARVALID and axi_arready are asserted. The slave registers - -- data are available on the axi_rdata bus at this instance. The - -- assertion of axi_rvalid marks the validity of read data on the - -- bus and axi_rresp indicates the status of read transaction.axi_rvalid - -- is deasserted on reset (active low). axi_rresp and axi_rdata are - -- cleared to zero on reset (active low). - process (S_AXI_ACLK) - begin - if rising_edge(S_AXI_ACLK) then - if S_AXI_ARESETN = '0' then - axi_rvalid <= '0'; - axi_rresp <= "00"; - else - if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then - -- Valid read data is available at the read data bus - axi_rvalid <= '1'; - axi_rresp <= "00"; -- 'OKAY' response - elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then - -- Read data is accepted by the master - axi_rvalid <= '0'; - end if; - end if; - end if; - end process; - - -- Implement memory mapped register select and read logic generation - -- Slave register read enable is asserted when valid address is available - -- and the slave is ready to accept the read address. - slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ; - - process (I2S_RESET_REG, I2S_TRANSFER_CONTROL_REG, I2S_FIFO_CONTROL_REG, I2S_DATA_IN_REG, I2S_DATA_OUT_REG, I2S_CLOCK_CONTROL_REG, I2S_STATUS_REG, I2S_PERIOD_COUNT_REG, I2S_STREAM_CONTROL_REG, slv_reg9, axi_araddr, S_AXI_ARESETN, slv_reg_rden) - variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); - begin - if S_AXI_ARESETN = '0' then - reg_data_out <= (others => '1'); - else - -- Address decoding for reading registers - loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); - case loc_addr is - when b"0000" => - reg_data_out <= I2S_RESET_REG; - when b"0001" => - reg_data_out <= I2S_TRANSFER_CONTROL_REG; - when b"0010" => - reg_data_out <= I2S_FIFO_CONTROL_REG; - when b"0011" => - reg_data_out <= I2S_DATA_IN_REG; - when b"0100" => - reg_data_out <= I2S_DATA_OUT_REG; - when b"0101" => - reg_data_out <= I2S_STATUS_REG; - when b"0110" => - reg_data_out <= I2S_CLOCK_CONTROL_REG; - when b"0111" => - reg_data_out <= I2S_PERIOD_COUNT_REG; - when b"1000" => - reg_data_out <= I2S_STREAM_CONTROL_REG; - when b"1001" => - reg_data_out <= slv_reg9; - when others => - reg_data_out <= (others => '0'); - end case; - end if; - end process; - - -- Output register or memory read data - process( S_AXI_ACLK ) is - begin - if (rising_edge (S_AXI_ACLK)) then - if ( S_AXI_ARESETN = '0' ) then - axi_rdata <= (others => '0'); - else - if (slv_reg_rden = '1') then - -- When there is a valid read address (S_AXI_ARVALID) with - -- acceptance of read address by the slave (axi_arready), - -- output the read dada - -- Read address mux - axi_rdata <= reg_data_out; -- register read data - end if; - end if; - end if; - end process; - - - -- Add user logic here - - -- User logic ends - -end arch_imp; diff --git a/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/fifo_32/fifo_32.xci b/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/fifo_32/fifo_32.xci deleted file mode 100644 index b688cf6..0000000 --- a/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/fifo_32/fifo_32.xci +++ /dev/null @@ -1,395 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - fifo_32 - - - fifo_32 - Independent_Clocks_Block_RAM - 2 - 2 - Native - Standard_FIFO - false - 24 - 4096 - 24 - 4096 - false - false - true - true - Asynchronous_Reset - 1 - true - 0 - false - false - false - false - Active_High - false - Active_High - false - Active_High - false - Active_High - false - false - false - false - false - 12 - false - 12 - false - 12 - false - 1 - 1 - No_Programmable_Full_Threshold - 4093 - 4092 - No_Programmable_Empty_Threshold - 2 - 3 - AXI4 - Common_Clock - false - Slave_Interface_Clock_Enable - READ_WRITE - 0 - 32 - 64 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 4 - true - false - false - 1 - false - 1 - FIFO - Common_Clock_Block_RAM - Data_FIFO - false - false - false - 16 - false - No_Programmable_Full_Threshold - 1023 - No_Programmable_Empty_Threshold - 1022 - FIFO - Common_Clock_Block_RAM - Data_FIFO - false - false - false - 1024 - false - No_Programmable_Full_Threshold - 1023 - No_Programmable_Empty_Threshold - 1022 - FIFO - Common_Clock_Block_RAM - Data_FIFO - false - false - false - 16 - false - No_Programmable_Full_Threshold - 1023 - No_Programmable_Empty_Threshold - 1022 - FIFO - Common_Clock_Block_RAM - Data_FIFO - false - false - false - 16 - false - No_Programmable_Full_Threshold - 1023 - No_Programmable_Empty_Threshold - 1022 - FIFO - Common_Clock_Block_RAM - Data_FIFO - false - false - false - 1024 - false - No_Programmable_Full_Threshold - 1023 - No_Programmable_Empty_Threshold - 1022 - FIFO - Common_Clock_Block_RAM - Data_FIFO - false - false - false - 1024 - false - No_Programmable_Full_Threshold - 1023 - No_Programmable_Empty_Threshold - 1022 - Fully_Registered - Fully_Registered - Fully_Registered - Fully_Registered - Fully_Registered - Fully_Registered - false - Active_High - false - Active_High - false - false - false - false - false - false - false - false - 0 - 0 - 12 - BlankString - 24 - 0 - 24 - 0 - artix7 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 2 - 0 - 1 - BlankString - 0 - 0 - 1 - 0 - 4kx9 - 2 - 3 - 0 - 4093 - 4092 - 0 - 12 - 4096 - 1 - 12 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 12 - 4096 - 1 - 12 - 1 - 1 - 1 - 0 - 2 - 0 - 1 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 32 - 64 - 8 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 8 - 1 - 1 - 4 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 512x36 - 1kx36 - 512x36 - 512x36 - 1kx36 - 1kx18 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 32 - 64 - 2 - 32 - 64 - 1 - 16 - 1024 - 16 - 16 - 1024 - 1024 - 4 - 10 - 4 - 4 - 10 - 10 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1023 - 1023 - 1023 - 1023 - 1023 - 1023 - 0 - 0 - 0 - 0 - 0 - 0 - 1022 - 1022 - 1022 - 1022 - 1022 - 1022 - 0 - 0 - 0 - 0 - 0 - 0 - artix7 - xc7a200t - sbg484 - -1 - C - - VERILOG - MIXED - TRUE - TRUE - - TRUE - 2014.3.1 - 2 - OUT_OF_CONTEXT - - . - . - - - - diff --git a/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/fifo_4/fifo_4.xci b/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/fifo_4/fifo_4.xci deleted file mode 100644 index 55742cd..0000000 --- a/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/fifo_4/fifo_4.xci +++ /dev/null @@ -1,395 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - fifo_4 - - - fifo_4 - Independent_Clocks_Block_RAM - 2 - 2 - Native - Standard_FIFO - false - 4 - 16 - 4 - 16 - false - false - true - true - Asynchronous_Reset - 1 - true - 0 - false - false - false - false - Active_High - false - Active_High - false - Active_High - false - Active_High - false - false - false - false - false - 4 - false - 4 - false - 4 - false - 1 - 1 - No_Programmable_Full_Threshold - 13 - 12 - No_Programmable_Empty_Threshold - 2 - 3 - AXI4 - Common_Clock - false - Slave_Interface_Clock_Enable - READ_WRITE - 0 - 32 - 64 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 4 - true - false - false - 1 - false - 1 - FIFO - Common_Clock_Block_RAM - Data_FIFO - false - false - false - 16 - false - No_Programmable_Full_Threshold - 1023 - No_Programmable_Empty_Threshold - 1022 - FIFO - Common_Clock_Block_RAM - Data_FIFO - false - false - false - 1024 - false - No_Programmable_Full_Threshold - 1023 - No_Programmable_Empty_Threshold - 1022 - FIFO - Common_Clock_Block_RAM - Data_FIFO - false - false - false - 16 - false - No_Programmable_Full_Threshold - 1023 - No_Programmable_Empty_Threshold - 1022 - FIFO - Common_Clock_Block_RAM - Data_FIFO - false - false - false - 16 - false - No_Programmable_Full_Threshold - 1023 - No_Programmable_Empty_Threshold - 1022 - FIFO - Common_Clock_Block_RAM - Data_FIFO - false - false - false - 1024 - false - No_Programmable_Full_Threshold - 1023 - No_Programmable_Empty_Threshold - 1022 - FIFO - Common_Clock_Block_RAM - Data_FIFO - false - false - false - 1024 - false - No_Programmable_Full_Threshold - 1023 - No_Programmable_Empty_Threshold - 1022 - Fully_Registered - Fully_Registered - Fully_Registered - Fully_Registered - Fully_Registered - Fully_Registered - false - Active_High - false - Active_High - false - false - false - false - false - false - false - false - 0 - 0 - 4 - BlankString - 4 - 0 - 4 - 0 - artix7 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 2 - 0 - 1 - BlankString - 0 - 0 - 1 - 0 - 512x36 - 2 - 3 - 0 - 13 - 12 - 0 - 4 - 16 - 1 - 4 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 4 - 16 - 1 - 4 - 1 - 1 - 1 - 0 - 2 - 0 - 1 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 32 - 64 - 8 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 8 - 1 - 1 - 4 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 512x36 - 1kx36 - 512x36 - 512x36 - 1kx36 - 1kx18 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 32 - 64 - 2 - 32 - 64 - 1 - 16 - 1024 - 16 - 16 - 1024 - 1024 - 4 - 10 - 4 - 4 - 10 - 10 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1023 - 1023 - 1023 - 1023 - 1023 - 1023 - 0 - 0 - 0 - 0 - 0 - 0 - 1022 - 1022 - 1022 - 1022 - 1022 - 1022 - 0 - 0 - 0 - 0 - 0 - 0 - artix7 - xc7a200t - sbg484 - -1 - C - - VERILOG - MIXED - TRUE - TRUE - - TRUE - 2014.3.1 - 2 - OUT_OF_CONTEXT - - . - . - - - - diff --git a/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/i2s_ctl.vhd b/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/i2s_ctl.vhd deleted file mode 100644 index 7a5bb81..0000000 --- a/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/i2s_ctl.vhd +++ /dev/null @@ -1,325 +0,0 @@ -------------------------------------------------------------------------------- --- --- COPYRIGHT (C) 2012, Digilent RO. All rights reserved --- -------------------------------------------------------------------------------- --- FILE NAME : i2s_ctl.vhd --- MODULE NAME : I2S Control --- AUTHOR : Mihaita Nagy --- AUTHOR'S EMAIL : mihaita.nagy@digilent.ro -------------------------------------------------------------------------------- --- REVISION HISTORY --- VERSION DATE AUTHOR DESCRIPTION --- 1.0 2012-25-01 Mihaita Nagy Created --- 2.0 2012-02-04 Mihaita Nagy Remade the i2s_transmitter.vhd and --- i2s_receiver.vhd into one new module. --- 3.0 2014-12-02 HegbeliC Implemented edge detection for the --- master mode and the division rate --- for the different sampling rates -------------------------------------------------------------------------------- --- KEYWORDS : I2S -------------------------------------------------------------------------------- --- DESCRIPTION : This module implements the I2S transmitter and receiver --- interface, with a 32-bit Stereo data transmission. Parameter --- C_DATA_WIDTH sets the width of the data to be transmitted, --- with a maximum value of 32 bits. If a smaller width size is --- used (i.e. 24) than the remaining bits that needs to be --- transmitted to complete the 32-bit length, are automaticaly --- set to 0. -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - ------------------------------------------------------------------------- --- Module Declaration ------------------------------------------------------------------------- -entity i2s_ctl is - generic ( - -- Width of one Slot (24/20/18/16-bit wide) - C_DATA_WIDTH: integer := 24 - ); - port ( - CLK_I : in std_logic; -- System clock (100 MHz) - RST_I : in std_logic; -- System reset - EN_TX_I : in std_logic; -- Transmit enable - EN_RX_I : in std_logic; -- Receive enable - FS_I : in std_logic_vector(3 downto 0); -- Sampling rate slector - MM_I : in std_logic; -- Audio controler Master Mode delcetor - D_L_I : in std_logic_vector(C_DATA_WIDTH-1 downto 0); -- Left channel data - D_R_I : in std_logic_vector(C_DATA_WIDTH-1 downto 0); -- Right channel data - OE_L_O : out std_logic; -- Left channel data output enable pulse - OE_R_O : out std_logic; -- Right channel data output enable pulse - WE_L_O : out std_logic; -- Left channel data write enable pulse - WE_R_O : out std_logic; -- Right channel data write enable pulse - D_L_O : out std_logic_vector(C_DATA_WIDTH-1 downto 0); -- Left channel data - D_R_O : out std_logic_vector(C_DATA_WIDTH-1 downto 0); -- Right channel data - BCLK_O : out std_logic; -- serial CLK - BCLK_I : in std_logic; -- serial CLK - BCLK_T : out std_logic; -- serial CLK - LRCLK_O : out std_logic; -- channel CLK - LRCLK_I : in std_logic; -- channel CLK - LRCLK_T : out std_logic; -- channel CLK - SDATA_O : out std_logic; -- Output serial data - SDATA_I : in std_logic -- Input serial data - ); -end i2s_ctl; - -architecture Behavioral of i2s_ctl is - ------------------------------------------------------------------------- --- Signal Declarations ------------------------------------------------------------------------- --- Counter for the clock divider -signal Cnt_Bclk : integer range 0 to 31; - --- Counter for the L/R clock divider -signal Cnt_Lrclk : integer range 0 to 31; - --- Rising and Falling edge impulses of the serial clock -signal BCLK_Fall, BCLK_Rise : std_logic; -signal BCLK_Fall_int, BCLK_Rise_int : std_logic; -signal BCLK_Fall_shot, BCLK_Rise_shot : std_logic; - --- Synchronisation signals for Rising and Falling edge -signal Q1R, Q2R, Q3R : std_logic; -signal Q1F, Q2F, Q3F : std_logic; - --- Internal synchronous BCLK signal -signal BCLK_int : std_logic; - --- Internal synchronous LRCLK signal -signal LRCLK_int : std_logic; -signal LRCLK : std_logic; - --- -signal Data_Out_int : std_logic_vector(31 downto 0); - --- -signal Data_In_int : std_logic_vector(31 downto 0); - --- -signal D_L_O_int : std_logic_vector(C_DATA_WIDTH-1 downto 0); - --- -signal D_R_O_int : std_logic_vector(C_DATA_WIDTH-1 downto 0); - ---Internal synchronous OE signals -signal OE_R_int, OE_L_int : std_logic; - ---Internal synchronous WE signals -signal WE_R_int, WE_L_int : std_logic; - --- Division rate for the BCLK and LRCLK -signal DIV_RATE : natural := 4; - ------------------------------------------------------------------------- --- Module Implementation ------------------------------------------------------------------------- - -begin - ------------------------------------------------------------------------- --- Sampling frequency and data width decoder (DIV_RATE, C_DATA_WIDTH) ------------------------------------------------------------------------- - - BIT_FS: process(CLK_I) - begin - if rising_edge(CLK_I) then - case (FS_I) is - when x"0" => DIV_RATE <= 24; - when x"1" => DIV_RATE <= 16; - when x"2" => DIV_RATE <= 12; - when x"3" => DIV_RATE <= 8; - when x"4" => DIV_RATE <= 6; - when x"5" => DIV_RATE <= 4; - when x"6" => DIV_RATE <= 2; - when others => DIV_RATE <= 4; - end case; - end if; - end process; - ------------------------------------------------------------------------- --- Serial clock generator (BCLK_O, BCLK_Fall, BCLK_Rise) ------------------------------------------------------------------------- - SER_CLK: process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - Cnt_Bclk <= 0; - BCLK_int <= '0'; - elsif Cnt_Bclk = ((DIV_RATE/2)-1) then - Cnt_Bclk <= 0; - BCLK_int <= not BCLK_int; - else - Cnt_Bclk <= Cnt_Bclk + 1; - end if; - end if; - end process SER_CLK; - - -- Rising and Falling edges when in Slave mode - BCLK_Fall_int <= '1' when Cnt_Bclk = ((DIV_RATE/2)-1) and BCLK_int = '1' and (EN_RX_I = '1' or EN_TX_I = '1') else '0'; - BCLK_Rise_int <= '1' when Cnt_Bclk = ((DIV_RATE/2)-1) and BCLK_int = '0' and (EN_RX_I = '1' or EN_TX_I = '1') else '0'; - - -- Rising edge detection when in Master Mode (BCLK_I active) - OneShotRise: process(CLK_I) - begin - if rising_edge(CLK_I) then - Q1R<=BCLK_I; - Q2R<=Q1R; - Q3R<=Q2R; - end if; - end process; - - BCLK_Rise_shot <= BCLK_I and (not Q3R); - - -- Falling edge detection when in Master Mode (BCLK_I active) - OneShotFall: process(CLK_I) - begin - if rising_edge(CLK_I) then - Q1F<=not BCLK_I; - Q2F<=Q1F; - Q3F<=Q2F; - end if; - end process; - - BCLK_Fall_shot <= not BCLK_I and (not Q3F); - - -- Falling edge selection with respect to Master Mode bit - BCLK_Fall <= BCLK_Fall_int when MM_I = '0' else - BCLK_Fall_shot; - - -- Risesing edge selection with respect to Master Mode bit - BCLK_Rise <= BCLK_Rise_int when MM_I = '0' else - BCLK_Rise_shot; - - -- Serial clock output - BCLK_O <= BCLK_int when EN_RX_I = '1' or EN_TX_I = '1' else '1'; - BCLK_T <= MM_I; - ------------------------------------------------------------------------- --- Left/Right clock generator (LRCLK_O, LRCLK_Pls) ------------------------------------------------------------------------- - LRCLK_GEN: process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - Cnt_Lrclk <= 0; - LRCLK <= '0'; -- Left channel active by default - elsif BCLK_Fall = '1' then - if Cnt_Lrclk = 31 then -- half of frame (64 bits) - Cnt_Lrclk <= 0; - LRCLK <= not LRCLK; - else - Cnt_Lrclk <= Cnt_Lrclk + 1; - end if; - end if; - end if; - end process LRCLK_GEN; - - -- L/R clock output - LRCLK_O <= LRCLK when EN_TX_I = '1' or EN_RX_I = '1' else '0'; - LRCLK_int <= LRCLK when MM_I = '0' else LRCLK_I; - LRCLK_T <= MM_I; - ------------------------------------------------------------------------- --- Load in paralled data, shift out serial data (SDATA_O) ------------------------------------------------------------------------- - SER_DATA_O: process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - Data_Out_int(31) <= '0'; - Data_Out_int(30 downto 31-C_DATA_WIDTH) <= D_L_I; -- Left channel data by default - Data_Out_int(30-C_DATA_WIDTH downto 0) <= (others => '0'); - elsif Cnt_Lrclk = 0 and BCLK_Rise = '1' then -- load par. data - if LRCLK_int = '1' then - Data_Out_int(31) <= '0'; - Data_Out_int(30 downto 31-C_DATA_WIDTH) <= D_R_I; - Data_Out_int(30-C_DATA_WIDTH downto 0) <= (others => '0'); - else - Data_Out_int(31) <= '0'; - Data_Out_int(30 downto 31-C_DATA_WIDTH) <= D_L_I; - Data_Out_int(30-C_DATA_WIDTH downto 0) <= (others => '0'); - end if; - elsif BCLK_Fall = '1' then -- shift out ser. data - Data_Out_int <= Data_Out_int(30 downto 0) & '0'; - end if; - end if; - end process SER_DATA_O; - - -- Serial data output - SDATA_O <= Data_Out_int(31) when EN_TX_I = '1' else '0'; - ------------------------------------------------------------------------- --- Shift in serial data, load out parallel data (SDATA_I) ------------------------------------------------------------------------- - SER_DATA_I: process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - Data_In_int <= (others => '0'); - D_L_O_int <= (others => '0'); - D_R_O_int <= (others => '0'); - elsif Cnt_Lrclk = 0 and BCLK_Fall = '1' then -- load par. data - if LRCLK_int = '1' then - D_L_O_int <= Data_In_int(31 downto 32-C_DATA_WIDTH); - Data_In_int <= (others => '0'); - else - D_R_O_int <= Data_In_int(31 downto 32-C_DATA_WIDTH); - Data_In_int <= (others => '0'); - end if; - elsif BCLK_Rise = '1' then -- shift in ser. data - Data_In_int <= Data_In_int(30 downto 0) & SDATA_I; - end if; - end if; - end process SER_DATA_I; - - D_L_O <= D_L_O_int; - D_R_O <= D_R_O_int; - ------------------------------------------------------------------------- --- Output Enable signals (for FIFO) ------------------------------------------------------------------------- - OE_GEN: process(CLK_I) - begin - if rising_edge(CLK_I) then - if Cnt_Lrclk = 31 and BCLK_Fall = '1' then - if LRCLK_int = '1' then -- Right channel - OE_R_int <= '1'; - else -- Left channel - OE_L_int <= '1'; - end if; - else - OE_R_int <= '0'; - OE_L_int <= '0'; - end if; - end if; - end process OE_GEN; - - OE_R_O <= OE_R_int when EN_TX_I = '1' else '0'; - OE_L_O <= OE_L_int when EN_TX_I = '1' else '0'; - ------------------------------------------------------------------------- --- Write Enable signals (for FIFO) ------------------------------------------------------------------------- - WE_GEN: process(CLK_I) - begin - if rising_edge(CLK_I) then - if Cnt_Lrclk = 1 and BCLK_Rise = '1' then - if LRCLK_int = '1' then -- Right channel - WE_R_int <= '1'; - else -- Left channel - WE_L_int <= '1'; - end if; - else - WE_R_int <= '0'; - WE_L_int <= '0'; - end if; - end if; - end process WE_GEN; - - WE_R_O <= WE_R_int when EN_RX_I = '1' else '0'; - WE_L_O <= WE_L_int when EN_RX_I = '1' else '0'; - -end Behavioral; - diff --git a/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/i2s_rx_tx.vhd b/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/i2s_rx_tx.vhd deleted file mode 100644 index 429c9e8..0000000 --- a/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/i2s_rx_tx.vhd +++ /dev/null @@ -1,436 +0,0 @@ -------------------------------------------------------------------------------- --- --- COPYRIGHT (C) 2012, Digilent RO. All rights reserved --- -------------------------------------------------------------------------------- --- FILE NAME : i2s_rx_tx.vhd --- MODULE NAME : I2S Tranceiver --- AUTHOR : Mihaita Nagy --- AUTHOR'S EMAIL : mihaita.nagy@digilent.ro -------------------------------------------------------------------------------- --- REVISION HISTORY --- VERSION DATE AUTHOR DESCRIPTION --- 1.0 2012-25-01 MihaitaN Created --- 2.0 ? MihaitaN ? --- 3.0 2014-12-02 HegbeliC Integration of the MCLK and Master Mode -------------------------------------------------------------------------------- --- KEYWORDS : I2S -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -library unisim; -use unisim.VComponents.all; - ------------------------------------------------------------------------- --- Module Declaration ------------------------------------------------------------------------- -entity i2s_rx_tx is - generic ( - -- Width of left/right channel data buses - C_DATA_WIDTH : integer := 24 - ); - port ( - -- Global signals - CLK_I : in std_logic; - RST_I : in std_logic; - - -- Control signals - TX_RS_I : in std_logic; - RX_RS_I : in std_logic; - - -- CLK input for MCLK rendering - CLK_100MHZ_I : in std_logic; - - -- Control signal for setting the sampeling rate - SAMPLING_RATE_I : in std_logic_vector (3 downto 0); - - -- Flag for when the Controller is in master mode - CTL_MASTER_MODE_I : in std_logic; - - -- DBG - DBG_TX_FIFO_RST_I : out std_logic; - DBG_TX_FIFO_WR_EN_I : out std_logic; - DBG_TX_FIFO_RD_EN_I : out std_logic; - DBG_TX_FIFO_EMPTY_O : out std_logic; - DBG_TX_FIFO_FULL_O : out std_logic; - DBG_TX_FIFO_D_I : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - DBG_TX_FIFO_D_O : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - DBG_TX_RS_I : out std_logic; - - DBG_RX_FIFO_RST_I : out std_logic; - DBG_RX_FIFO_WR_EN_I : out std_logic; - DBG_RX_FIFO_RD_EN_I : out std_logic; - DBG_RX_FIFO_FULL_O : out std_logic; - DBG_RX_FIFO_EMPTY_O : out std_logic; - DBG_RX_FIFO_D_O : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - DBG_RX_FIFO_D_I : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - DBG_RX_RS_I : out std_logic; - - -- Tx FIFO Control signals - TX_FIFO_RST_I : in std_logic; - TX_FIFO_D_I : in std_logic_vector(C_DATA_WIDTH-1 downto 0); - TX_FIFO_WR_EN_I : in std_logic; - - -- Rx FIFO Control signals - RX_FIFO_RST_I : in std_logic; - RX_FIFO_RD_EN_I : in std_logic; - RX_FIFO_D_O : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - - -- Tx FIFO Flags - TX_FIFO_EMPTY_O : out std_logic; - TX_FIFO_FULL_O : out std_logic; - - -- Rx FIFO Flags - RX_FIFO_EMPTY_O : out std_logic; - RX_FIFO_FULL_O : out std_logic; - - -- I2S interface signals - BCLK_O : out std_logic; - BCLK_I : in std_logic; - BCLK_T : out std_logic; - LRCLK_O : out std_logic; - LRCLK_I : in std_logic; - LRCLK_T : out std_logic; - MCLK_O : out std_logic; - SDATA_I : in std_logic; - SDATA_O : out std_logic - ); -end i2s_rx_tx; - -architecture Behavioral of i2s_rx_tx is - ------------------------------------------------------------------------- --- Signal Declarations ------------------------------------------------------------------------- -signal StartTransaction : std_logic; -signal StopTransaction : std_logic; -signal RxEn : std_logic; -signal TxEn : std_logic; -signal LRCLK_Int : std_logic; -signal LR : std_logic; -signal Rnw : std_logic; -signal RxFifoDataIn : std_logic_vector(C_DATA_WIDTH-1 downto 0); -signal RxFifoDataInL : std_logic_vector(C_DATA_WIDTH-1 downto 0); -signal RxFifoDataInR : std_logic_vector(C_DATA_WIDTH-1 downto 0); -signal RxFifoWrEn : std_logic; -signal RxFifoWrEnL : std_logic; -signal RxFifoWrEnR : std_logic; -signal TxFifoDataOut : std_logic_vector(C_DATA_WIDTH-1 downto 0); -signal TxFifoRdEn : std_logic; -signal TxFifoRdEnL : std_logic; -signal TxFifoRdEnR : std_logic; -signal TxFifoEmpty : std_logic; -signal RxFifoFull : std_logic; -signal SamplingFrequncy : std_logic_vector(3 downto 0); -signal Rst_Int : std_logic; -signal Rst_Int_sync : std_logic; -signal MM_Int : std_logic; -signal Rst_interior : std_logic; --- DCM signals -signal RstDcm : std_logic; -signal LockDcm : std_logic; -signal CLK_12 : std_logic; - -signal TxFifoReset : std_logic; -signal RxFifoReset : std_logic; - -signal TX_FIFO_FULL_int : std_logic; -signal RX_FIFO_EMPTY_int : std_logic; -signal RX_FIFO_D_int : std_logic_vector(C_DATA_WIDTH-1 downto 0); - ------------------------------------------------------------------------- --- Component Declarations ------------------------------------------------------------------------- -component i2s_ctl - generic ( - C_DATA_WIDTH: integer := 24); - port ( - CLK_I : in std_logic; - RST_I : in std_logic; - EN_TX_I : in std_logic; - EN_RX_I : in std_logic; - OE_L_O : out std_logic; - OE_R_O : out std_logic; - WE_L_O : out std_logic; - WE_R_O : out std_logic; - D_L_I : in std_logic_vector(C_DATA_WIDTH-1 downto 0); - D_R_I : in std_logic_vector(C_DATA_WIDTH-1 downto 0); - D_L_O : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - D_R_O : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - MM_I : in std_logic; - FS_I : in std_logic_vector(3 downto 0); - BCLK_O : out std_logic; - BCLK_I : in std_logic; - BCLK_T : out std_logic; - LRCLK_O : out std_logic; - LRCLK_I : in std_logic; - LRCLK_T : out std_logic; - SDATA_O : out std_logic; - SDATA_I : in std_logic); -end component; - --- the FIFO used for sample rate bus - -component fifo_4 - port ( - rst : in std_logic; - wr_clk : in std_logic; - rd_clk : in std_logic; - din : in std_logic_vector(3 downto 0); - wr_en : in std_logic; - rd_en : in std_logic; - dout : out std_logic_vector(3 downto 0); - full : out std_logic; - empty : out std_logic - ); -end component; - --- the FIFO, used for Rx and Tx -component fifo_32 - port ( - wr_clk : in std_logic; - rd_clk : in std_logic; - rst : in std_logic; - din : in std_logic_vector(23 downto 0); - wr_en : in std_logic; - rd_en : in std_logic; - dout : out std_logic_vector(23 downto 0); - full : out std_logic; - empty : out std_logic); -end component; - --- the DCM for generating 12.288 MHz -component DCM - port( - CLK_100 : in std_logic; - CLK_12_288 : out std_logic; - RESET : in std_logic; - LOCKED : out std_logic - ); -end component; - --- the synchronisation unite for the two CLK domains -component Sync_ff - port( - CLK : in std_logic; - D_I : in std_logic; - Q_O : out std_logic - ); -end component; - -component rst_sync - Port ( - RST_I : in STD_LOGIC; - CLK : in STD_LOGIC; - Q_O : out STD_LOGIC - ); -end component; - ------------------------------------------------------------------------- --- Module Implementation ------------------------------------------------------------------------- - -begin - ------------------------------------------------------------------------- --- Instantiate the I2S transmitter module ------------------------------------------------------------------------- - Inst_I2sRxTx: i2s_ctl - generic map( - C_DATA_WIDTH => C_DATA_WIDTH) - port map( - CLK_I => CLK_12, - RST_I => Rst_Int_sync, - EN_TX_I => TxEn, - EN_RX_I => RxEn, - OE_L_O => TxFifoRdEnL, - OE_R_O => TxFifoRdEnR, - WE_L_O => RxFifoWrEnL, - WE_R_O => RxFifoWrEnR, - D_L_I => TxFifoDataOut, - D_R_I => TxFifoDataOut, - D_L_O => RxFifoDataInL, - D_R_O => RxFifoDataInR, - MM_I => MM_Int, - FS_I => SamplingFrequncy, - BCLK_O => BCLK_O, - BCLK_I => BCLK_I, - BCLK_T => BCLK_T, - LRCLK_O => LRCLK_Int, - LRCLK_I => LRCLK_I, - LRCLK_T => LRCLK_T, - SDATA_O => SDATA_O, - SDATA_I => SDATA_I); - - TxFifoRdEn <= TxFifoRdEnL or TxFifoRdEnR; - RxFifoWrEn <= RxFifoWrEnL or RxFifoWrEnR; - LRCLK_O <= LRCLK_Int; - ------------------------------------------------------------------------- --- Instantiate the transmitter fifo ------------------------------------------------------------------------- - Inst_Sampling: fifo_4 - port map ( - rst => RST_I, - wr_clk => CLK_I, - rd_clk => CLK_12, - din => SAMPLING_RATE_I, - wr_en => '1', - rd_en => '1', - dout => SamplingFrequncy, - full => open, - empty => open); - ------------------------------------------------------------------------- --- Instantiate the transmitter fifo ------------------------------------------------------------------------- - Inst_I2sTxFifo: fifo_32 - port map( - wr_clk => CLK_I, - rd_clk => CLK_12, - rst => TxFifoReset, - din => TX_FIFO_D_I, - wr_en => TX_FIFO_WR_EN_I, - rd_en => TxFifoRdEn, - dout => TxFifoDataOut, - full => TX_FIFO_FULL_int, - empty => TxFifoEmpty); - - DBG_TX_FIFO_RST_I <= TxFifoReset; - DBG_TX_FIFO_RD_EN_I <= TxFifoRdEn; - DBG_TX_FIFO_WR_EN_I <= TX_FIFO_WR_EN_I; - DBG_TX_FIFO_FULL_O <= TX_FIFO_FULL_int; - DBG_TX_FIFO_EMPTY_O <= TxFifoEmpty; - DBG_TX_FIFO_D_I <= TX_FIFO_D_I; - DBG_TX_FIFO_D_O <= TxFifoDataOut; - DBG_TX_RS_I <= TxEn; - --- TX_FIFO_EMPTY_O <= TxFifoEmpty; - TX_FIFO_FULL_O <= TX_FIFO_FULL_int; - ------------------------------------------------------------------------- --- Instantiate the receiver fifo ------------------------------------------------------------------------- - Inst_I2sRxFifo: fifo_32 - port map( - wr_clk => CLK_12, - rd_clk => CLK_I, - rst => RX_FIFO_RST_I, - din => RxFifoDataIn, - wr_en => RxFifoWrEn, - rd_en => RX_FIFO_RD_EN_I, - dout => RX_FIFO_D_int, - full => RxFifoFull, - empty => RX_FIFO_EMPTY_int); - - DBG_RX_FIFO_RST_I <= RX_FIFO_RST_I; - DBG_RX_FIFO_WR_EN_I <= RxFifoWrEn; - DBG_RX_FIFO_RD_EN_I <= RX_FIFO_RD_EN_I; - DBG_RX_FIFO_EMPTY_O <=RX_FIFO_EMPTY_int; - DBG_RX_FIFO_D_O <= RX_FIFO_D_int; - DBG_RX_FIFO_D_I <= RxFifoDataIn; - DBG_RX_RS_I <= RxEn; - - - RX_FIFO_EMPTY_O <= RX_FIFO_EMPTY_int; --- RX_FIFO_FULL_O <= RxFifoFull; - RX_FIFO_D_O <= RX_FIFO_D_int; - - -- input selct between audio controler in master or in slave - LR <= LRCLK_Int when MM_Int = '0' else LRCLK_I; - RxFifoDataIn <= RxFifoDataInR when LR = '1' else RxFifoDataInL; - - ------------------------------------------------------------------------- --- Instantiate DCM ------------------------------------------------------------------------- - Inst_Dcm : DCM - port map( - CLK_100 => CLK_100MHZ_I, - CLK_12_288 => CLK_12, - RESET => Rst_Int, - LOCKED => LockDcm); - - Rst_Int <= RST_I and not LockDcm; - ------------------------------------------------------------------------- --- Instantiate BusSync for the sample rate read out (100 -> 12) ------------------------------------------------------------------------- - Inst_SyncBit_RX_RS: Sync_ff - port map( - CLK => CLK_12, - D_I => RX_RS_I, - Q_O => RxEn); - ------------------------------------------------------------------------- --- Instantiate BusSync for the sample rate read out (100 -> 12) ------------------------------------------------------------------------- - Inst_SyncBit_TX_RS: Sync_ff - port map( - CLK => CLK_12, - D_I => TX_RS_I, - Q_O => TxEn); - ------------------------------------------------------------------------- --- Instantiate BusSync for the sample rate read out (100 -> 12) ------------------------------------------------------------------------- - Inst_SyncBit_CTL_MM: Sync_ff - port map( - CLK => CLK_12, - D_I => CTL_MASTER_MODE_I, - Q_O => MM_Int); - ------------------------------------------------------------------------- --- Instantiate BusSync for the sample rate read out (100 -> 12) ------------------------------------------------------------------------- - Inst_Rst_Sync_TX_RST: rst_sync - port map( - CLK => CLK_12, - RST_I => TX_FIFO_RST_I, - Q_O => TxFifoReset); - ------------------------------------------------------------------------- --- Instantiate BusSync for the sample rate read out (100 -> 12) ------------------------------------------------------------------------- - Inst_Rst_Sync_RST: rst_sync - port map( - CLK => CLK_12, - RST_I => Rst_Int, - Q_O => Rst_Int_sync); - ------------------------------------------------------------------------- --- Instantiate BusSync for the sample rate read out (100 -> 12) ------------------------------------------------------------------------- - Inst_SyncBit_Tx_Empty: Sync_ff - port map( - CLK => CLK_I, - D_I => TxFifoEmpty, - Q_O => TX_FIFO_EMPTY_O); - ------------------------------------------------------------------------- --- Instantiate BusSync for the sample rate read out (100 -> 12) ------------------------------------------------------------------------- - Inst_SyncBit_Rx_Full: Sync_ff - port map( - CLK => CLK_I, - D_I => RxFifoFull, - Q_O => RX_FIFO_FULL_O); - ------------------------------------------------------------------------- --- Instantiaton of the ODDR for the Output MCLK ------------------------------------------------------------------------- - ODDR_inst : ODDR - generic map( - DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC") - port map ( - Q => MCLK_O, -- 1-bit DDR output - C => CLK_12, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D1 => '1', -- 1-bit data input (positive edge) - D2 => '0', -- 1-bit data input (negative edge) - R => '0', -- 1-bit reset input - S => '0'); -- 1-bit set input - -end Behavioral; diff --git a/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/i2s_stream.vhd b/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/i2s_stream.vhd deleted file mode 100644 index 057fcf4..0000000 --- a/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/i2s_stream.vhd +++ /dev/null @@ -1,158 +0,0 @@ -------------------------------------------------------------------------------- --- --- COPYRIGHT (C) 2014, Digilent RO. All rights reserved --- -------------------------------------------------------------------------------- --- FILE NAME : i2s_stream.vhd --- MODULE NAME : I2S Stream --- AUTHOR : Hegbeli Ciprian --- AUTHOR'S EMAIL : ciprian.hegbeli@digilent.com -------------------------------------------------------------------------------- --- REVISION HISTORY --- VERSION DATE AUTHOR DESCRIPTION --- 1.0 2014-28-03 Hegbeli Ciprian Created -------------------------------------------------------------------------------- --- KEYWORDS : Stream -------------------------------------------------------------------------------- --- DESCRIPTION : This module implements the Stream protocol for sending the --- incomming I2S data to the DMA. It implements both the S2MM --- and the MM2S allowing for a full duplex comunication -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -use IEEE.NUMERIC_STD.ALL; -use ieee.std_logic_unsigned.all; - ------------------------------------------------------------------------- --- Module Declaration ------------------------------------------------------------------------- -entity i2s_stream is - generic ( - -- Stream data width (must be multiple of 8) - C_AXI_STREAM_DATA_WIDTH : integer := 32; - -- Width of one Slot (24/20/18/16-bit wide) - C_DATA_WIDTH : integer := 24 - ); - port ( - - -- Tx FIFO Flags - TX_FIFO_FULL_I : in std_logic; - - -- Rx FIFO Flags - RX_FIFO_EMPTY_I : in std_logic; - - -- Tx FIFO Control signals - TX_FIFO_D_O : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - - -- Rx FIFO Control signals - RX_FIFO_D_I : in std_logic_vector(C_DATA_WIDTH-1 downto 0); - - NR_OF_SMPL_I : in std_logic_vector(20 downto 0); - - TX_STREAM_EN_I : in std_logic; - RX_STREAM_EN_I : in std_logic; - - -- AXI4-Stream - -- Slave - S_AXIS_MM2S_ACLK_I : in std_logic; - S_AXIS_MM2S_ARESETN : in std_logic; - S_AXIS_MM2S_TREADY_O : out std_logic; - S_AXIS_MM2S_TDATA_I : in std_logic_vector(C_AXI_STREAM_DATA_WIDTH-1 downto 0); - S_AXIS_MM2S_TLAST_I : in std_logic; - S_AXIS_MM2S_TVALID_I : in std_logic; - - -- Master - M_AXIS_S2MM_ACLK_I : in std_logic; - M_AXIS_S2MM_ARESETN : in std_logic; - M_AXIS_S2MM_TDATA_O : out std_logic_vector(C_AXI_STREAM_DATA_WIDTH-1 downto 0); - M_AXIS_S2MM_TLAST_O : out std_logic; - M_AXIS_S2MM_TVALID_O : out std_logic; - M_AXIS_S2MM_TREADY_I : in std_logic; - M_AXIS_S2MM_TKEEP_O : out std_logic_vector((C_AXI_STREAM_DATA_WIDTH/8)-1 downto 0) - - ); -end i2s_stream; - -architecture Behavioral of i2s_stream is - ------------------------------------------------------------------------- --- Signal Declarations ------------------------------------------------------------------------- -signal nr_of_rd, nr_of_wr : std_logic_vector (20 downto 0); -signal tlast : std_logic; -signal ready : std_logic; - ------------------------------------------------------------------------- --- Module Implementation ------------------------------------------------------------------------- - -begin - - ------------------------------------------------------------------------- --- MM2S protocol imnplementation ------------------------------------------------------------------------- - S_Control: process (S_AXIS_MM2S_ACLK_I) - begin - if (S_AXIS_MM2S_ACLK_I'event and S_AXIS_MM2S_ACLK_I = '0') then - if (S_AXIS_MM2S_ARESETN = '0') then - nr_of_rd <= NR_OF_SMPL_I; - elsif (RX_STREAM_EN_I = '1') then - if (nr_of_rd > 0) then - if (S_AXIS_MM2S_TVALID_I = '1' and ready = '1') then - TX_FIFO_D_O <= S_AXIS_MM2S_TDATA_I(C_DATA_WIDTH-1 downto 0); - nr_of_rd <= nr_of_rd-1; - end if; - end if; - else - nr_of_rd <= NR_OF_SMPL_I; - end if; - end if; - end process; - - -- ready signal decalaration - ready <= not TX_FIFO_FULL_I when RX_STREAM_EN_I = '1' else - '0'; - S_AXIS_MM2S_TREADY_O <= ready; - ------------------------------------------------------------------------- --- S2MM protocol implementation ------------------------------------------------------------------------- - M_Control: process (M_AXIS_S2MM_ACLK_I) - begin - if (M_AXIS_S2MM_ACLK_I'event and M_AXIS_S2MM_ACLK_I = '1') then - if (M_AXIS_S2MM_ARESETN = '0') THEN - tlast <= '0'; - nr_of_wr <= NR_OF_SMPL_I; - elsif (TX_STREAM_EN_I = '1') then - if (nr_of_wr > 0) then - if (M_AXIS_S2MM_TREADY_I = '1' and RX_FIFO_EMPTY_I = '0') then - nr_of_wr <= nr_of_wr-1; - end if; - end if; - if (nr_of_wr = 0) then - tlast <= '0'; - end if; - if (nr_of_wr = 1) then - tlast <= '1'; - end if; - else - tlast <= '0'; - nr_of_wr <= NR_OF_SMPL_I; - end if; - end if; - end process; - - -- S2MM Data signals - M_AXIS_S2MM_TDATA_O(C_AXI_STREAM_DATA_WIDTH-1 downto C_DATA_WIDTH) <= (others => '0'); - M_AXIS_S2MM_TDATA_O(C_DATA_WIDTH-1 downto 0) <= RX_FIFO_D_I; - -- S2MM valid signal only active when strea is enabled and not EOL - M_AXIS_S2MM_TVALID_O <= not RX_FIFO_EMPTY_I when (nr_of_wr > 0 and TX_STREAM_EN_I = '1') else - '0'; - M_AXIS_S2MM_TLAST_O <= tlast; - -- Kepp all incomming samples - M_AXIS_S2MM_TKEEP_O <= (others => '1'); - -end Behavioral; - diff --git a/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/rst_sync.vhd b/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/rst_sync.vhd deleted file mode 100644 index bbb2b58..0000000 --- a/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/rst_sync.vhd +++ /dev/null @@ -1,73 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 10/29/2014 12:36:46 PM --- Design Name: --- Module Name: rst_sync - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -Library UNISIM; -use UNISIM.vcomponents.all; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity rst_sync is - Port ( RST_I : in STD_LOGIC; - CLK : in STD_LOGIC; - Q_O : out STD_LOGIC); -end rst_sync; - -architecture Behavioral of rst_sync is - -signal d_int: std_logic; -signal q_int: std_logic; - -begin - -FDRE_inst_1 : FDPE - generic map ( - INIT => '0') -- Initial value of register ('0' or '1') - port map ( - Q => d_int, -- Data output - C => CLK, -- Clock input - CE => '1', -- Clock enable input - PRE => RST_I, -- Synchronous reset input - D => '0' -- Data input - ); - -FDRE_inst_2 : FDPE - generic map ( - INIT => '0') -- Initial value of register ('0' or '1') - port map ( - Q => q_int, -- Data output - C => CLK, -- Clock input - CE => '1', -- Clock enable input - PRE => RST_I, -- Synchronous reset input - D => d_int -- Data input - ); - -Q_O <= q_int; -end Behavioral; diff --git a/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/xgui/d_axi_i2s_audio_v2_0.tcl b/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/xgui/d_axi_i2s_audio_v2_0.tcl deleted file mode 100644 index 69fa659..0000000 --- a/hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/xgui/d_axi_i2s_audio_v2_0.tcl +++ /dev/null @@ -1,109 +0,0 @@ -# Definitional proc to organize widgets for parameters. -proc init_gui { IPINST } { - ipgui::add_param $IPINST -name "Component_Name" - #Adding Page - set Page_0 [ipgui::add_page $IPINST -name "Page 0"] - set_property tooltip {Page 0} ${Page_0} - ipgui::add_param $IPINST -name "C_DATA_WIDTH" -parent ${Page_0} - ipgui::add_param $IPINST -name "C_AXI_STREAM_DATA_WIDTH" -parent ${Page_0} - ipgui::add_param $IPINST -name "C_AXI_L_DATA_WIDTH" -parent ${Page_0} - ipgui::add_param $IPINST -name "C_AXI_L_ADDR_WIDTH" -parent ${Page_0} - ipgui::add_param $IPINST -name "ENABLE_STREAM" -parent ${Page_0} - ipgui::add_param $IPINST -name "BIDIRECTIONAL_CLK" -parent ${Page_0} - - -} - -proc update_PARAM_VALUE.BIDIRECTIONAL_CLK { PARAM_VALUE.BIDIRECTIONAL_CLK } { - # Procedure called to update BIDIRECTIONAL_CLK when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.BIDIRECTIONAL_CLK { PARAM_VALUE.BIDIRECTIONAL_CLK } { - # Procedure called to validate BIDIRECTIONAL_CLK - return true -} - -proc update_PARAM_VALUE.C_AXI_L_ADDR_WIDTH { PARAM_VALUE.C_AXI_L_ADDR_WIDTH } { - # Procedure called to update C_AXI_L_ADDR_WIDTH when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.C_AXI_L_ADDR_WIDTH { PARAM_VALUE.C_AXI_L_ADDR_WIDTH } { - # Procedure called to validate C_AXI_L_ADDR_WIDTH - return true -} - -proc update_PARAM_VALUE.C_AXI_L_DATA_WIDTH { PARAM_VALUE.C_AXI_L_DATA_WIDTH } { - # Procedure called to update C_AXI_L_DATA_WIDTH when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.C_AXI_L_DATA_WIDTH { PARAM_VALUE.C_AXI_L_DATA_WIDTH } { - # Procedure called to validate C_AXI_L_DATA_WIDTH - return true -} - -proc update_PARAM_VALUE.C_AXI_STREAM_DATA_WIDTH { PARAM_VALUE.C_AXI_STREAM_DATA_WIDTH } { - # Procedure called to update C_AXI_STREAM_DATA_WIDTH when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.C_AXI_STREAM_DATA_WIDTH { PARAM_VALUE.C_AXI_STREAM_DATA_WIDTH } { - # Procedure called to validate C_AXI_STREAM_DATA_WIDTH - return true -} - -proc update_PARAM_VALUE.C_DATA_WIDTH { PARAM_VALUE.C_DATA_WIDTH } { - # Procedure called to update C_DATA_WIDTH when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.C_DATA_WIDTH { PARAM_VALUE.C_DATA_WIDTH } { - # Procedure called to validate C_DATA_WIDTH - return true -} - -proc update_PARAM_VALUE.ENABLE_STREAM { PARAM_VALUE.ENABLE_STREAM } { - # Procedure called to update ENABLE_STREAM when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.ENABLE_STREAM { PARAM_VALUE.ENABLE_STREAM } { - # Procedure called to validate ENABLE_STREAM - return true -} - -proc update_PARAM_VALUE.C_AXI_L_BASEADDR { PARAM_VALUE.C_AXI_L_BASEADDR } { - # Procedure called to update C_AXI_L_BASEADDR when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.C_AXI_L_BASEADDR { PARAM_VALUE.C_AXI_L_BASEADDR } { - # Procedure called to validate C_AXI_L_BASEADDR - return true -} - -proc update_PARAM_VALUE.C_AXI_L_HIGHADDR { PARAM_VALUE.C_AXI_L_HIGHADDR } { - # Procedure called to update C_AXI_L_HIGHADDR when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.C_AXI_L_HIGHADDR { PARAM_VALUE.C_AXI_L_HIGHADDR } { - # Procedure called to validate C_AXI_L_HIGHADDR - return true -} - - -proc update_MODELPARAM_VALUE.C_DATA_WIDTH { MODELPARAM_VALUE.C_DATA_WIDTH PARAM_VALUE.C_DATA_WIDTH } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.C_DATA_WIDTH}] ${MODELPARAM_VALUE.C_DATA_WIDTH} -} - -proc update_MODELPARAM_VALUE.C_AXI_STREAM_DATA_WIDTH { MODELPARAM_VALUE.C_AXI_STREAM_DATA_WIDTH PARAM_VALUE.C_AXI_STREAM_DATA_WIDTH } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.C_AXI_STREAM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_AXI_STREAM_DATA_WIDTH} -} - -proc update_MODELPARAM_VALUE.C_AXI_L_DATA_WIDTH { MODELPARAM_VALUE.C_AXI_L_DATA_WIDTH PARAM_VALUE.C_AXI_L_DATA_WIDTH } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.C_AXI_L_DATA_WIDTH}] ${MODELPARAM_VALUE.C_AXI_L_DATA_WIDTH} -} - -proc update_MODELPARAM_VALUE.C_AXI_L_ADDR_WIDTH { MODELPARAM_VALUE.C_AXI_L_ADDR_WIDTH PARAM_VALUE.C_AXI_L_ADDR_WIDTH } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.C_AXI_L_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_AXI_L_ADDR_WIDTH} -} - diff --git a/hdmi-out-test/hdmi-out-test.runs/impl_1/design_1_wrapper.bit b/hdmi-out-test/hdmi-out-test.runs/impl_1/dvi_top.bit similarity index 76% rename from hdmi-out-test/hdmi-out-test.runs/impl_1/design_1_wrapper.bit rename to hdmi-out-test/hdmi-out-test.runs/impl_1/dvi_top.bit index 51a9fae..c268735 100644 Binary files a/hdmi-out-test/hdmi-out-test.runs/impl_1/design_1_wrapper.bit and b/hdmi-out-test/hdmi-out-test.runs/impl_1/dvi_top.bit differ diff --git a/hdmi-out-test/hdmi-out-test.srcs/sources_1/bd/design_1/design_1.bd b/hdmi-out-test/hdmi-out-test.srcs/sources_1/bd/blinki_bd/blinki_bd.bd similarity index 50% rename from hdmi-out-test/hdmi-out-test.srcs/sources_1/bd/design_1/design_1.bd rename to hdmi-out-test/hdmi-out-test.srcs/sources_1/bd/blinki_bd/blinki_bd.bd index e82416d..7140a6a 100644 --- a/hdmi-out-test/hdmi-out-test.srcs/sources_1/bd/design_1/design_1.bd +++ b/hdmi-out-test/hdmi-out-test.srcs/sources_1/bd/blinki_bd/blinki_bd.bd @@ -1,52 +1,24 @@ { "design": { "design_info": { - "boundary_crc": "0x27337D8971FDBBAA", + "boundary_crc": "0x21E765320D4D646C", "device": "xc7z020clg400-1", - "gen_directory": "../../../../hdmi-out-test.gen/sources_1/bd/design_1", - "name": "design_1", + "gen_directory": "../../../../hdmi-out-test.gen/sources_1/bd/blinki_bd", + "name": "blinki_bd", "rev_ctrl_bd_flag": "RevCtrlBdOff", "synth_flow_mode": "Hierarchical", "tool_version": "2021.2", "validated": "true" }, "design_tree": { - "axi_dma_0": "", "axi_gpio_0": "", - "axi_iic_0": "", - "axi_mem_intercon": { - "xbar": "", - "s00_couplers": {}, - "s01_couplers": {}, - "m00_couplers": { + "ps7_0_axi_periph": { + "s00_couplers": { "auto_pc": "" } }, - "processing_system7_0": "", - "processing_system7_0_axi_periph": { - "xbar": "", - "s00_couplers": { - "auto_pc": "" - }, - "m00_couplers": {}, - "m01_couplers": {}, - "m02_couplers": {}, - "m03_couplers": {}, - "m04_couplers": {}, - "m05_couplers": {} - }, - "rst_processing_system7_0_100M": "", - "xlconcat_0": "", - "d_axi_i2s_audio_0": "", - "CONST0": "", - "hier_0": { - "v_tpg_0": "", - "rgb2dvi_0": "", - "CONST1": "", - "v_axi4s_vid_out_0": "", - "v_tc_0": "", - "rst_processing_system7_0_100M1": "" - } + "rst_ps7_0_100M": "", + "processing_system7_0": "" }, "interface_ports": { "DDR": { @@ -114,41 +86,20 @@ "value_src": "default" } } - }, - "btns_4bits": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:gpio:1.0", - "vlnv": "xilinx.com:interface:gpio_rtl:1.0" - }, - "iic_rtl": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:iic:1.0", - "vlnv": "xilinx.com:interface:iic_rtl:1.0" } }, "ports": { - "MCLK_O": { - "direction": "O" - }, - "BCLK_O": { - "direction": "O" - }, - "LRCLK_O": { - "direction": "O" - }, - "SDATA_O": { - "direction": "O" - }, - "SDATA_I": { - "direction": "I" - }, - "TMDS_Clk_n_0": { + "FCLK_CLK0_0": { "type": "clk", "direction": "O", "parameters": { + "CLK_DOMAIN": { + "value": "blinki_bd_processing_system7_0_0_FCLK_CLK0", + "value_src": "default_prop" + }, "FREQ_HZ": { "value": "100000000", - "value_src": "default" + "value_src": "user_prop" }, "FREQ_TOLERANCE_HZ": { "value": "0", @@ -164,18 +115,17 @@ } } }, - "TMDS_Data_p_0": { - "direction": "O", - "left": "2", - "right": "0" - }, - "TMDS_Clk_p_0": { + "FCLK_CLK1_0": { "type": "clk", "direction": "O", "parameters": { + "CLK_DOMAIN": { + "value": "blinki_bd_processing_system7_0_0_FCLK_CLK1", + "value_src": "default_prop" + }, "FREQ_HZ": { "value": "100000000", - "value_src": "default" + "value_src": "user_prop" }, "FREQ_TOLERANCE_HZ": { "value": "0", @@ -191,127 +141,35 @@ } } }, - "TMDS_Data_n_0": { + "gpio_io_o_0": { "direction": "O", - "left": "2", + "left": "3", "right": "0" } }, "components": { - "axi_dma_0": { - "vlnv": "xilinx.com:ip:axi_dma:7.1", - "xci_name": "design_1_axi_dma_0_0", - "xci_path": "ip/design_1_axi_dma_0_0/design_1_axi_dma_0_0.xci", - "inst_hier_path": "axi_dma_0", - "parameters": { - "c_include_mm2s_dre": { - "value": "0" - }, - "c_include_s2mm_dre": { - "value": "0" - }, - "c_include_sg": { - "value": "0" - }, - "c_micro_dma": { - "value": "0" - }, - "c_mm2s_burst_size": { - "value": "8" - }, - "c_s2mm_burst_size": { - "value": "8" - }, - "c_sg_length_width": { - "value": "23" - } - }, - "interface_ports": { - "M_AXI_MM2S": { - "vlnv": "xilinx.com:interface:aximm_rtl:1.0", - "mode": "Master", - "address_space_ref": "Data_MM2S", - "base_address": { - "minimum": "0x00000000", - "maximum": "0xFFFFFFFF", - "width": "32" - } - }, - "M_AXI_S2MM": { - "vlnv": "xilinx.com:interface:aximm_rtl:1.0", - "mode": "Master", - "address_space_ref": "Data_S2MM", - "base_address": { - "minimum": "0x00000000", - "maximum": "0xFFFFFFFF", - "width": "32" - } - } - }, - "addressing": { - "address_spaces": { - "Data_MM2S": { - "range": "4G", - "width": "32" - }, - "Data_S2MM": { - "range": "4G", - "width": "32" - } - } - } - }, "axi_gpio_0": { "vlnv": "xilinx.com:ip:axi_gpio:2.0", - "xci_name": "design_1_axi_gpio_0_0", - "xci_path": "ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xci", + "xci_name": "blinki_bd_axi_gpio_0_0", + "xci_path": "ip/blinki_bd_axi_gpio_0_0/blinki_bd_axi_gpio_0_0.xci", "inst_hier_path": "axi_gpio_0", "parameters": { - "C_INTERRUPT_PRESENT": { - "value": "1" - }, "GPIO_BOARD_INTERFACE": { - "value": "btns_4bits" + "value": "leds_4bits" }, "USE_BOARD_FLOW": { "value": "true" } } }, - "axi_iic_0": { - "vlnv": "xilinx.com:ip:axi_iic:2.1", - "xci_name": "design_1_axi_iic_0_0", - "xci_path": "ip/design_1_axi_iic_0_0/design_1_axi_iic_0_0.xci", - "inst_hier_path": "axi_iic_0", - "parameters": { - "IIC_BOARD_INTERFACE": { - "value": "audio_i2c" - }, - "USE_BOARD_FLOW": { - "value": "true" - } - } - }, - "axi_mem_intercon": { + "ps7_0_axi_periph": { "vlnv": "xilinx.com:ip:axi_interconnect:2.1", - "xci_path": "ip/design_1_axi_mem_intercon_0/design_1_axi_mem_intercon_0.xci", - "inst_hier_path": "axi_mem_intercon", - "xci_name": "design_1_axi_mem_intercon_0", + "xci_path": "ip/blinki_bd_ps7_0_axi_periph_0/blinki_bd_ps7_0_axi_periph_0.xci", + "inst_hier_path": "ps7_0_axi_periph", + "xci_name": "blinki_bd_ps7_0_axi_periph_0", "parameters": { "NUM_MI": { "value": "1" - }, - "NUM_SI": { - "value": "2" - }, - "S01_HAS_DATA_FIFO": { - "value": "0" - }, - "S02_HAS_DATA_FIFO": { - "value": "1" - }, - "SYNCHRONIZATION_STAGES": { - "value": "2" } }, "interface_ports": { @@ -320,11 +178,6 @@ "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" }, - "S01_AXI": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, "M00_AXI": { "mode": "Master", "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", @@ -361,22 +214,6 @@ "type": "rst", "direction": "I" }, - "S01_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "S01_AXI" - }, - "ASSOCIATED_RESET": { - "value": "S01_ARESETN" - } - } - }, - "S01_ARESETN": { - "type": "rst", - "direction": "I" - }, "M00_ACLK": { "type": "clk", "direction": "I", @@ -395,152 +232,7 @@ } }, "components": { - "xbar": { - "vlnv": "xilinx.com:ip:axi_crossbar:2.1", - "xci_name": "design_1_xbar_4", - "xci_path": "ip/design_1_xbar_4/design_1_xbar_4.xci", - "inst_hier_path": "axi_mem_intercon/xbar", - "parameters": { - "NUM_MI": { - "value": "1" - }, - "NUM_SI": { - "value": "2" - }, - "STRATEGY": { - "value": "0" - } - }, - "interface_ports": { - "S00_AXI": { - "vlnv": "xilinx.com:interface:aximm_rtl:1.0", - "mode": "Slave", - "bridges": [ - "M00_AXI" - ] - }, - "S01_AXI": { - "vlnv": "xilinx.com:interface:aximm_rtl:1.0", - "mode": "Slave", - "bridges": [ - "M00_AXI" - ] - } - } - }, "s00_couplers": { - "interface_ports": { - "M_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "S_AXI": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - } - }, - "ports": { - "M_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M_ARESETN" - } - } - }, - "M_ARESETN": { - "type": "rst", - "direction": "I" - }, - "S_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "S_AXI" - }, - "ASSOCIATED_RESET": { - "value": "S_ARESETN" - } - } - }, - "S_ARESETN": { - "type": "rst", - "direction": "I" - } - }, - "interface_nets": { - "s00_couplers_to_s00_couplers": { - "interface_ports": [ - "S_AXI", - "M_AXI" - ] - } - } - }, - "s01_couplers": { - "interface_ports": { - "M_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "S_AXI": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - } - }, - "ports": { - "M_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M_ARESETN" - } - } - }, - "M_ARESETN": { - "type": "rst", - "direction": "I" - }, - "S_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "S_AXI" - }, - "ASSOCIATED_RESET": { - "value": "S_ARESETN" - } - } - }, - "S_ARESETN": { - "type": "rst", - "direction": "I" - } - }, - "interface_nets": { - "s01_couplers_to_s01_couplers": { - "interface_ports": [ - "S_AXI", - "M_AXI" - ] - } - } - }, - "m00_couplers": { "interface_ports": { "M_AXI": { "mode": "Master", @@ -590,15 +282,15 @@ "components": { "auto_pc": { "vlnv": "xilinx.com:ip:axi_protocol_converter:2.1", - "xci_name": "design_1_auto_pc_0", - "xci_path": "ip/design_1_auto_pc_0/design_1_auto_pc_0.xci", - "inst_hier_path": "axi_mem_intercon/m00_couplers/auto_pc", + "xci_name": "blinki_bd_auto_pc_0", + "xci_path": "ip/blinki_bd_auto_pc_0/blinki_bd_auto_pc_0.xci", + "inst_hier_path": "ps7_0_axi_periph/s00_couplers/auto_pc", "parameters": { "MI_PROTOCOL": { - "value": "AXI3" + "value": "AXI4LITE" }, "SI_PROTOCOL": { - "value": "AXI4" + "value": "AXI3" } }, "interface_ports": { @@ -613,13 +305,13 @@ } }, "interface_nets": { - "auto_pc_to_m00_couplers": { + "auto_pc_to_s00_couplers": { "interface_ports": [ "M_AXI", "auto_pc/M_AXI" ] }, - "m00_couplers_to_auto_pc": { + "s00_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" @@ -643,56 +335,20 @@ } }, "interface_nets": { - "axi_mem_intercon_to_s00_couplers": { + "ps7_0_axi_periph_to_s00_couplers": { "interface_ports": [ "S00_AXI", "s00_couplers/S_AXI" ] }, - "axi_mem_intercon_to_s01_couplers": { - "interface_ports": [ - "S01_AXI", - "s01_couplers/S_AXI" - ] - }, - "m00_couplers_to_axi_mem_intercon": { + "s00_couplers_to_ps7_0_axi_periph": { "interface_ports": [ "M00_AXI", - "m00_couplers/M_AXI" - ] - }, - "s00_couplers_to_xbar": { - "interface_ports": [ - "s00_couplers/M_AXI", - "xbar/S00_AXI" - ] - }, - "s01_couplers_to_xbar": { - "interface_ports": [ - "s01_couplers/M_AXI", - "xbar/S01_AXI" - ] - }, - "xbar_to_m00_couplers": { - "interface_ports": [ - "xbar/M00_AXI", - "m00_couplers/S_AXI" + "s00_couplers/M_AXI" ] } }, "nets": { - "M00_ACLK_1": { - "ports": [ - "M00_ACLK", - "m00_couplers/M_ACLK" - ] - }, - "M00_ARESETN_1": { - "ports": [ - "M00_ARESETN", - "m00_couplers/M_ARESETN" - ] - }, "S00_ACLK_1": { "ports": [ "S00_ACLK", @@ -705,42 +361,30 @@ "s00_couplers/S_ARESETN" ] }, - "S01_ACLK_1": { + "ps7_0_axi_periph_ACLK_net": { "ports": [ - "S01_ACLK", - "s01_couplers/S_ACLK" + "M00_ACLK", + "s00_couplers/M_ACLK" ] }, - "S01_ARESETN_1": { + "ps7_0_axi_periph_ARESETN_net": { "ports": [ - "S01_ARESETN", - "s01_couplers/S_ARESETN" - ] - }, - "axi_mem_intercon_ACLK_net": { - "ports": [ - "ACLK", - "xbar/aclk", - "s00_couplers/M_ACLK", - "s01_couplers/M_ACLK", - "m00_couplers/S_ACLK" - ] - }, - "axi_mem_intercon_ARESETN_net": { - "ports": [ - "ARESETN", - "xbar/aresetn", - "s00_couplers/M_ARESETN", - "s01_couplers/M_ARESETN", - "m00_couplers/S_ARESETN" + "M00_ARESETN", + "s00_couplers/M_ARESETN" ] } } }, + "rst_ps7_0_100M": { + "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", + "xci_name": "blinki_bd_rst_ps7_0_100M_0", + "xci_path": "ip/blinki_bd_rst_ps7_0_100M_0/blinki_bd_rst_ps7_0_100M_0.xci", + "inst_hier_path": "rst_ps7_0_100M" + }, "processing_system7_0": { "vlnv": "xilinx.com:ip:processing_system7:5.5", - "xci_name": "design_1_processing_system7_0_0", - "xci_path": "ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xci", + "xci_name": "blinki_bd_processing_system7_0_0", + "xci_path": "ip/blinki_bd_processing_system7_0_0/blinki_bd_processing_system7_0_0.xci", "inst_hier_path": "processing_system7_0", "parameters": { "PCW_ACT_APU_PERIPHERAL_FREQMHZ": { @@ -768,7 +412,7 @@ "value": "100.000000" }, "PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": { - "value": "76.923080" + "value": "100.000000" }, "PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ": { "value": "10.000000" @@ -858,7 +502,7 @@ "value": "100000000" }, "PCW_CLK1_FREQ": { - "value": "76923080" + "value": "100000000" }, "PCW_CLK2_FREQ": { "value": "10000000" @@ -866,18 +510,6 @@ "PCW_CLK3_FREQ": { "value": "10000000" }, - "PCW_CORE0_FIQ_INTR": { - "value": "0" - }, - "PCW_CORE0_IRQ_INTR": { - "value": "0" - }, - "PCW_CORE1_FIQ_INTR": { - "value": "0" - }, - "PCW_CORE1_IRQ_INTR": { - "value": "0" - }, "PCW_CPU_CPU_6X4X_MAX_RANGE": { "value": "667" }, @@ -1047,7 +679,7 @@ "value": "0" }, "PCW_EN_EMIO_TTC0": { - "value": "1" + "value": "0" }, "PCW_EN_EMIO_TTC1": { "value": "0" @@ -1131,7 +763,7 @@ "value": "0" }, "PCW_EN_TTC0": { - "value": "1" + "value": "0" }, "PCW_EN_TTC1": { "value": "0" @@ -1173,7 +805,7 @@ "value": "100" }, "PCW_FPGA1_PERIPHERAL_FREQMHZ": { - "value": "74.250" + "value": "100" }, "PCW_FPGA2_PERIPHERAL_FREQMHZ": { "value": "50" @@ -1188,7 +820,7 @@ "value": "1" }, "PCW_GP0_EN_MODIFIABLE_TXN": { - "value": "0" + "value": "1" }, "PCW_GP0_NUM_READ_THREADS": { "value": "4" @@ -1197,7 +829,7 @@ "value": "4" }, "PCW_GP1_EN_MODIFIABLE_TXN": { - "value": "0" + "value": "1" }, "PCW_GP1_NUM_READ_THREADS": { "value": "4" @@ -1241,12 +873,6 @@ "PCW_INCLUDE_ACP_TRANS_CHECK": { "value": "0" }, - "PCW_IRQ_F2P_INTR": { - "value": "1" - }, - "PCW_IRQ_F2P_MODE": { - "value": "DIRECT" - }, "PCW_MIO_0_IOTYPE": { "value": "LVCMOS 3.3V" }, @@ -1841,24 +1467,6 @@ "PCW_OVERRIDE_BASIC_CLOCK": { "value": "0" }, - "PCW_P2F_ENET0_INTR": { - "value": "0" - }, - "PCW_P2F_GPIO_INTR": { - "value": "0" - }, - "PCW_P2F_QSPI_INTR": { - "value": "0" - }, - "PCW_P2F_SDIO0_INTR": { - "value": "0" - }, - "PCW_P2F_UART0_INTR": { - "value": "0" - }, - "PCW_P2F_USB0_INTR": { - "value": "0" - }, "PCW_PACKAGE_DDR_BOARD_DELAY0": { "value": "0.279" }, @@ -2021,21 +1629,6 @@ "PCW_SPI_PERIPHERAL_VALID": { "value": "0" }, - "PCW_S_AXI_HP0_DATA_WIDTH": { - "value": "32" - }, - "PCW_S_AXI_HP0_ID_WIDTH": { - "value": "6" - }, - "PCW_S_AXI_HP1_DATA_WIDTH": { - "value": "64" - }, - "PCW_S_AXI_HP2_DATA_WIDTH": { - "value": "64" - }, - "PCW_S_AXI_HP3_DATA_WIDTH": { - "value": "64" - }, "PCW_TPIU_PERIPHERAL_CLKSRC": { "value": "External" }, @@ -2045,9 +1638,6 @@ "PCW_TRACE_PERIPHERAL_ENABLE": { "value": "0" }, - "PCW_TTC0_BASEADDR": { - "value": "0xE0104000" - }, "PCW_TTC0_CLK0_PERIPHERAL_CLKSRC": { "value": "CPU_1X" }, @@ -2066,14 +1656,8 @@ "PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0": { "value": "1" }, - "PCW_TTC0_HIGHADDR": { - "value": "0xE0104fff" - }, "PCW_TTC0_PERIPHERAL_ENABLE": { - "value": "1" - }, - "PCW_TTC0_TTC0_IO": { - "value": "EMIO" + "value": "0" }, "PCW_TTC1_CLK0_PERIPHERAL_CLKSRC": { "value": "CPU_1X" @@ -2096,9 +1680,6 @@ "PCW_TTC1_PERIPHERAL_ENABLE": { "value": "0" }, - "PCW_TTC_PERIPHERAL_FREQMHZ": { - "value": "50" - }, "PCW_UART0_BASEADDR": { "value": "0xE0000000" }, @@ -2379,7 +1960,7 @@ "value": "0" }, "PCW_USE_FABRIC_INTERRUPT": { - "value": "1" + "value": "0" }, "PCW_USE_HIGH_OCM": { "value": "0" @@ -2406,7 +1987,7 @@ "value": "0" }, "PCW_USE_S_AXI_HP0": { - "value": "1" + "value": "0" }, "PCW_USE_S_AXI_HP1": { "value": "0" @@ -2433,7 +2014,7 @@ "value": "0" }, "preset": { - "value": "ZedBoard" + "value": "None" } }, "interface_ports": { @@ -2446,11 +2027,6 @@ "maximum": "0x7FFFFFFF", "width": "32" } - }, - "S_AXI_HP0": { - "vlnv": "xilinx.com:interface:aximm_rtl:1.0", - "mode": "Slave", - "memory_map_ref": "S_AXI_HP0" } }, "addressing": { @@ -2512,7 +2088,7 @@ }, "IO_Peripheral_Registers": { "name": "IO_Peripheral_Registers", - "display_name": "IOPeripheralRegisters", + "display_name": "IO Peripheral Registers", "base_address": "0xE0000000", "range": "3M", "width": "32", @@ -2520,7 +2096,7 @@ }, "SMC_Memories": { "name": "SMC_Memories", - "display_name": "SMCMemories", + "display_name": "SMC Memories", "base_address": "0xE1000000", "range": "80M", "width": "32", @@ -2528,7 +2104,7 @@ }, "SLCR_Registers": { "name": "SLCR_Registers", - "display_name": "SLCRRegisters", + "display_name": "SLCR Registers", "base_address": "0xF8000000", "range": "3K", "width": "32", @@ -2536,7 +2112,7 @@ }, "PS_System_Registers": { "name": "PS_System_Registers", - "display_name": "PSSystemRegisters", + "display_name": "PS System Registers", "base_address": "0xF8001000", "range": "8252K", "width": "32", @@ -2544,7 +2120,7 @@ }, "CPU_Private_Registers": { "name": "CPU_Private_Registers", - "display_name": "CPUPrivateRegisters", + "display_name": "CPU Private Registers", "base_address": "0xF8900000", "range": "6156K", "width": "32", @@ -2571,1222 +2147,9 @@ } } } - }, - "processing_system7_0_axi_periph": { - "vlnv": "xilinx.com:ip:axi_interconnect:2.1", - "xci_path": "ip/design_1_processing_system7_0_axi_periph_0/design_1_processing_system7_0_axi_periph_0.xci", - "inst_hier_path": "processing_system7_0_axi_periph", - "xci_name": "design_1_processing_system7_0_axi_periph_0", - "parameters": { - "NUM_MI": { - "value": "6" - }, - "SYNCHRONIZATION_STAGES": { - "value": "2" - } - }, - "interface_ports": { - "S00_AXI": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "M00_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "M01_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "M02_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "M03_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "M04_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "M05_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - } - }, - "ports": { - "ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_RESET": { - "value": "ARESETN" - } - } - }, - "ARESETN": { - "type": "rst", - "direction": "I" - }, - "S00_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "S00_AXI" - }, - "ASSOCIATED_RESET": { - "value": "S00_ARESETN" - } - } - }, - "S00_ARESETN": { - "type": "rst", - "direction": "I" - }, - "M00_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M00_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M00_ARESETN" - } - } - }, - "M00_ARESETN": { - "type": "rst", - "direction": "I" - }, - "M01_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M01_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M01_ARESETN" - } - } - }, - "M01_ARESETN": { - "type": "rst", - "direction": "I" - }, - "M02_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M02_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M02_ARESETN" - } - } - }, - "M02_ARESETN": { - "type": "rst", - "direction": "I" - }, - "M03_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M03_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M03_ARESETN" - } - } - }, - "M03_ARESETN": { - "type": "rst", - "direction": "I" - }, - "M04_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M04_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M04_ARESETN" - } - } - }, - "M04_ARESETN": { - "type": "rst", - "direction": "I" - }, - "M05_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M05_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M05_ARESETN" - } - } - }, - "M05_ARESETN": { - "type": "rst", - "direction": "I" - } - }, - "components": { - "xbar": { - "vlnv": "xilinx.com:ip:axi_crossbar:2.1", - "xci_name": "design_1_xbar_5", - "xci_path": "ip/design_1_xbar_5/design_1_xbar_5.xci", - "inst_hier_path": "processing_system7_0_axi_periph/xbar", - "parameters": { - "NUM_MI": { - "value": "6" - }, - "NUM_SI": { - "value": "1" - }, - "STRATEGY": { - "value": "0" - } - }, - "interface_ports": { - "S00_AXI": { - "vlnv": "xilinx.com:interface:aximm_rtl:1.0", - "mode": "Slave", - "bridges": [ - "M00_AXI", - "M01_AXI", - "M02_AXI", - "M03_AXI", - "M04_AXI", - "M05_AXI" - ] - } - } - }, - "s00_couplers": { - "interface_ports": { - "M_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "S_AXI": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - } - }, - "ports": { - "M_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M_ARESETN" - } - } - }, - "M_ARESETN": { - "type": "rst", - "direction": "I" - }, - "S_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "S_AXI" - }, - "ASSOCIATED_RESET": { - "value": "S_ARESETN" - } - } - }, - "S_ARESETN": { - "type": "rst", - "direction": "I" - } - }, - "components": { - "auto_pc": { - "vlnv": "xilinx.com:ip:axi_protocol_converter:2.1", - "xci_name": "design_1_auto_pc_1", - "xci_path": "ip/design_1_auto_pc_1/design_1_auto_pc_1.xci", - "inst_hier_path": "processing_system7_0_axi_periph/s00_couplers/auto_pc", - "parameters": { - "MI_PROTOCOL": { - "value": "AXI4LITE" - }, - "SI_PROTOCOL": { - "value": "AXI3" - } - }, - "interface_ports": { - "S_AXI": { - "vlnv": "xilinx.com:interface:aximm_rtl:1.0", - "mode": "Slave", - "bridges": [ - "M_AXI" - ] - } - } - } - }, - "interface_nets": { - "auto_pc_to_s00_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, - "s00_couplers_to_auto_pc": { - "interface_ports": [ - "S_AXI", - "auto_pc/S_AXI" - ] - } - }, - "nets": { - "S_ACLK_1": { - "ports": [ - "S_ACLK", - "auto_pc/aclk" - ] - }, - "S_ARESETN_1": { - "ports": [ - "S_ARESETN", - "auto_pc/aresetn" - ] - } - } - }, - "m00_couplers": { - "interface_ports": { - "M_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "S_AXI": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - } - }, - "ports": { - "M_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M_ARESETN" - } - } - }, - "M_ARESETN": { - "type": "rst", - "direction": "I" - }, - "S_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "S_AXI" - }, - "ASSOCIATED_RESET": { - "value": "S_ARESETN" - } - } - }, - "S_ARESETN": { - "type": "rst", - "direction": "I" - } - }, - "interface_nets": { - "m00_couplers_to_m00_couplers": { - "interface_ports": [ - "S_AXI", - "M_AXI" - ] - } - } - }, - "m01_couplers": { - "interface_ports": { - "M_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "S_AXI": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - } - }, - "ports": { - "M_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M_ARESETN" - } - } - }, - "M_ARESETN": { - "type": "rst", - "direction": "I" - }, - "S_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "S_AXI" - }, - "ASSOCIATED_RESET": { - "value": "S_ARESETN" - } - } - }, - "S_ARESETN": { - "type": "rst", - "direction": "I" - } - }, - "interface_nets": { - "m01_couplers_to_m01_couplers": { - "interface_ports": [ - "S_AXI", - "M_AXI" - ] - } - } - }, - "m02_couplers": { - "interface_ports": { - "M_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "S_AXI": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - } - }, - "ports": { - "M_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M_ARESETN" - } - } - }, - "M_ARESETN": { - "type": "rst", - "direction": "I" - }, - "S_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "S_AXI" - }, - "ASSOCIATED_RESET": { - "value": "S_ARESETN" - } - } - }, - "S_ARESETN": { - "type": "rst", - "direction": "I" - } - }, - "interface_nets": { - "m02_couplers_to_m02_couplers": { - "interface_ports": [ - "S_AXI", - "M_AXI" - ] - } - } - }, - "m03_couplers": { - "interface_ports": { - "M_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "S_AXI": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - } - }, - "ports": { - "M_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M_ARESETN" - } - } - }, - "M_ARESETN": { - "type": "rst", - "direction": "I" - }, - "S_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "S_AXI" - }, - "ASSOCIATED_RESET": { - "value": "S_ARESETN" - } - } - }, - "S_ARESETN": { - "type": "rst", - "direction": "I" - } - }, - "interface_nets": { - "m03_couplers_to_m03_couplers": { - "interface_ports": [ - "S_AXI", - "M_AXI" - ] - } - } - }, - "m04_couplers": { - "interface_ports": { - "M_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "S_AXI": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - } - }, - "ports": { - "M_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M_ARESETN" - } - } - }, - "M_ARESETN": { - "type": "rst", - "direction": "I" - }, - "S_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "S_AXI" - }, - "ASSOCIATED_RESET": { - "value": "S_ARESETN" - } - } - }, - "S_ARESETN": { - "type": "rst", - "direction": "I" - } - }, - "interface_nets": { - "m04_couplers_to_m04_couplers": { - "interface_ports": [ - "S_AXI", - "M_AXI" - ] - } - } - }, - "m05_couplers": { - "interface_ports": { - "M_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "S_AXI": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - } - }, - "ports": { - "M_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M_ARESETN" - } - } - }, - "M_ARESETN": { - "type": "rst", - "direction": "I" - }, - "S_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "S_AXI" - }, - "ASSOCIATED_RESET": { - "value": "S_ARESETN" - } - } - }, - "S_ARESETN": { - "type": "rst", - "direction": "I" - } - }, - "interface_nets": { - "m05_couplers_to_m05_couplers": { - "interface_ports": [ - "S_AXI", - "M_AXI" - ] - } - } - } - }, - "interface_nets": { - "m00_couplers_to_processing_system7_0_axi_periph": { - "interface_ports": [ - "M00_AXI", - "m00_couplers/M_AXI" - ] - }, - "m01_couplers_to_processing_system7_0_axi_periph": { - "interface_ports": [ - "M01_AXI", - "m01_couplers/M_AXI" - ] - }, - "m02_couplers_to_processing_system7_0_axi_periph": { - "interface_ports": [ - "M02_AXI", - "m02_couplers/M_AXI" - ] - }, - "m03_couplers_to_processing_system7_0_axi_periph": { - "interface_ports": [ - "M03_AXI", - "m03_couplers/M_AXI" - ] - }, - "m04_couplers_to_processing_system7_0_axi_periph": { - "interface_ports": [ - "M04_AXI", - "m04_couplers/M_AXI" - ] - }, - "m05_couplers_to_processing_system7_0_axi_periph": { - "interface_ports": [ - "M05_AXI", - "m05_couplers/M_AXI" - ] - }, - "processing_system7_0_axi_periph_to_s00_couplers": { - "interface_ports": [ - "S00_AXI", - "s00_couplers/S_AXI" - ] - }, - "s00_couplers_to_xbar": { - "interface_ports": [ - "s00_couplers/M_AXI", - "xbar/S00_AXI" - ] - }, - "xbar_to_m00_couplers": { - "interface_ports": [ - "xbar/M00_AXI", - "m00_couplers/S_AXI" - ] - }, - "xbar_to_m01_couplers": { - "interface_ports": [ - "xbar/M01_AXI", - "m01_couplers/S_AXI" - ] - }, - "xbar_to_m02_couplers": { - "interface_ports": [ - "xbar/M02_AXI", - "m02_couplers/S_AXI" - ] - }, - "xbar_to_m03_couplers": { - "interface_ports": [ - "xbar/M03_AXI", - "m03_couplers/S_AXI" - ] - }, - "xbar_to_m04_couplers": { - "interface_ports": [ - "xbar/M04_AXI", - "m04_couplers/S_AXI" - ] - }, - "xbar_to_m05_couplers": { - "interface_ports": [ - "xbar/M05_AXI", - "m05_couplers/S_AXI" - ] - } - }, - "nets": { - "M00_ACLK_1": { - "ports": [ - "M00_ACLK", - "m00_couplers/M_ACLK" - ] - }, - "M00_ARESETN_1": { - "ports": [ - "M00_ARESETN", - "m00_couplers/M_ARESETN" - ] - }, - "M01_ACLK_1": { - "ports": [ - "M01_ACLK", - "m01_couplers/M_ACLK" - ] - }, - "M01_ARESETN_1": { - "ports": [ - "M01_ARESETN", - "m01_couplers/M_ARESETN" - ] - }, - "M02_ACLK_1": { - "ports": [ - "M02_ACLK", - "m02_couplers/M_ACLK" - ] - }, - "M02_ARESETN_1": { - "ports": [ - "M02_ARESETN", - "m02_couplers/M_ARESETN" - ] - }, - "M03_ACLK_1": { - "ports": [ - "M03_ACLK", - "m03_couplers/M_ACLK" - ] - }, - "M03_ARESETN_1": { - "ports": [ - "M03_ARESETN", - "m03_couplers/M_ARESETN" - ] - }, - "M04_ACLK_1": { - "ports": [ - "M04_ACLK", - "m04_couplers/M_ACLK" - ] - }, - "M04_ARESETN_1": { - "ports": [ - "M04_ARESETN", - "m04_couplers/M_ARESETN" - ] - }, - "M05_ACLK_1": { - "ports": [ - "M05_ACLK", - "m05_couplers/M_ACLK" - ] - }, - "M05_ARESETN_1": { - "ports": [ - "M05_ARESETN", - "m05_couplers/M_ARESETN" - ] - }, - "S00_ACLK_1": { - "ports": [ - "S00_ACLK", - "s00_couplers/S_ACLK" - ] - }, - "S00_ARESETN_1": { - "ports": [ - "S00_ARESETN", - "s00_couplers/S_ARESETN" - ] - }, - "processing_system7_0_axi_periph_ACLK_net": { - "ports": [ - "ACLK", - "xbar/aclk", - "s00_couplers/M_ACLK", - "m00_couplers/S_ACLK", - "m01_couplers/S_ACLK", - "m02_couplers/S_ACLK", - "m03_couplers/S_ACLK", - "m04_couplers/S_ACLK", - "m05_couplers/S_ACLK" - ] - }, - "processing_system7_0_axi_periph_ARESETN_net": { - "ports": [ - "ARESETN", - "xbar/aresetn", - "s00_couplers/M_ARESETN", - "m00_couplers/S_ARESETN", - "m01_couplers/S_ARESETN", - "m02_couplers/S_ARESETN", - "m03_couplers/S_ARESETN", - "m04_couplers/S_ARESETN", - "m05_couplers/S_ARESETN" - ] - } - } - }, - "rst_processing_system7_0_100M": { - "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", - "xci_name": "design_1_rst_processing_system7_0_100M_0", - "xci_path": "ip/design_1_rst_processing_system7_0_100M_0/design_1_rst_processing_system7_0_100M_0.xci", - "inst_hier_path": "rst_processing_system7_0_100M" - }, - "xlconcat_0": { - "vlnv": "xilinx.com:ip:xlconcat:2.1", - "xci_name": "design_1_xlconcat_0_0", - "xci_path": "ip/design_1_xlconcat_0_0/design_1_xlconcat_0_0.xci", - "inst_hier_path": "xlconcat_0", - "parameters": { - "NUM_PORTS": { - "value": "4" - }, - "dout_width": { - "value": "4" - } - } - }, - "d_axi_i2s_audio_0": { - "vlnv": "digilentinc.com:user:d_axi_i2s_audio:2.0", - "xci_name": "design_1_d_axi_i2s_audio_0_0", - "xci_path": "ip/design_1_d_axi_i2s_audio_0_0/design_1_d_axi_i2s_audio_0_0.xci", - "inst_hier_path": "d_axi_i2s_audio_0", - "parameters": { - "ENABLE_STREAM": { - "value": "true" - } - } - }, - "CONST0": { - "vlnv": "xilinx.com:ip:xlconstant:1.1", - "xci_name": "design_1_xlconstant_0_2", - "xci_path": "ip/design_1_xlconstant_0_2/design_1_xlconstant_0_2.xci", - "inst_hier_path": "CONST0", - "parameters": { - "CONST_VAL": { - "value": "0" - } - } - }, - "hier_0": { - "interface_ports": { - "s_axi_CTRL": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "ctrl": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - } - }, - "ports": { - "PixelClk": { - "type": "clk", - "direction": "I" - }, - "TMDS_Clk_p_0": { - "type": "clk", - "direction": "O" - }, - "TMDS_Clk_n_0": { - "type": "clk", - "direction": "O" - }, - "TMDS_Data_p_0": { - "direction": "O", - "left": "2", - "right": "0" - }, - "TMDS_Data_n_0": { - "direction": "O", - "left": "2", - "right": "0" - }, - "ext_reset_in": { - "type": "rst", - "direction": "I" - }, - "clk_0": { - "type": "clk", - "direction": "I" - }, - "interconnect_aresetn": { - "type": "rst", - "direction": "O", - "left": "0", - "right": "0" - }, - "overflow": { - "direction": "O" - }, - "underflow": { - "direction": "O" - }, - "fifo_read_level": { - "direction": "O", - "left": "10", - "right": "0" - } - }, - "components": { - "v_tpg_0": { - "vlnv": "xilinx.com:ip:v_tpg:8.2", - "xci_name": "design_1_v_tpg_0_0", - "xci_path": "ip/design_1_v_tpg_0_0/design_1_v_tpg_0_0.xci", - "inst_hier_path": "hier_0/v_tpg_0", - "interface_ports": { - "s_axi_CTRL": { - "vlnv": "xilinx.com:interface:aximm_rtl:1.0", - "mode": "Slave", - "memory_map_ref": "s_axi_CTRL" - } - }, - "addressing": { - "memory_maps": { - "s_axi_CTRL": { - "address_blocks": { - "Reg": { - "base_address": "0", - "range": "64K", - "width": "16", - "usage": "register", - "offset_base_param": "C_S_AXI_CTRL_BASEADDR", - "offset_high_param": "C_S_AXI_CTRL_HIGHADDR" - } - } - } - } - } - }, - "rgb2dvi_0": { - "vlnv": "digilentinc.com:ip:rgb2dvi:1.4", - "xci_name": "design_1_rgb2dvi_0_1", - "xci_path": "ip/design_1_rgb2dvi_0_1/design_1_rgb2dvi_0_1.xci", - "inst_hier_path": "hier_0/rgb2dvi_0", - "parameters": { - "kClkRange": { - "value": "3" - } - } - }, - "CONST1": { - "vlnv": "xilinx.com:ip:xlconstant:1.1", - "xci_name": "design_1_xlconstant_0_0", - "xci_path": "ip/design_1_xlconstant_0_0/design_1_xlconstant_0_0.xci", - "inst_hier_path": "hier_0/CONST1" - }, - "v_axi4s_vid_out_0": { - "vlnv": "xilinx.com:ip:v_axi4s_vid_out:4.0", - "xci_name": "design_1_v_axi4s_vid_out_0_0", - "xci_path": "ip/design_1_v_axi4s_vid_out_0_0/design_1_v_axi4s_vid_out_0_0.xci", - "inst_hier_path": "hier_0/v_axi4s_vid_out_0", - "parameters": { - "C_HAS_ASYNC_CLK": { - "value": "1" - } - } - }, - "v_tc_0": { - "vlnv": "xilinx.com:ip:v_tc:6.2", - "xci_name": "design_1_v_tc_0_0", - "xci_path": "ip/design_1_v_tc_0_0/design_1_v_tc_0_0.xci", - "inst_hier_path": "hier_0/v_tc_0", - "parameters": { - "active_chroma_generation": { - "value": "false" - }, - "enable_detection": { - "value": "false" - }, - "horizontal_blank_generation": { - "value": "true" - }, - "vertical_blank_generation": { - "value": "true" - } - } - }, - "rst_processing_system7_0_100M1": { - "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", - "xci_name": "design_1_rst_processing_system7_0_100M_1", - "xci_path": "ip/design_1_rst_processing_system7_0_100M_1/design_1_rst_processing_system7_0_100M_1.xci", - "inst_hier_path": "hier_0/rst_processing_system7_0_100M1" - } - }, - "interface_nets": { - "processing_system7_0_axi_periph_M04_AXI": { - "interface_ports": [ - "s_axi_CTRL", - "v_tpg_0/s_axi_CTRL" - ] - }, - "processing_system7_0_axi_periph_M05_AXI": { - "interface_ports": [ - "ctrl", - "v_tc_0/ctrl" - ] - }, - "v_axi4s_vid_out_0_vid_io_out": { - "interface_ports": [ - "rgb2dvi_0/RGB", - "v_axi4s_vid_out_0/vid_io_out" - ] - }, - "v_tc_0_vtiming_out": { - "interface_ports": [ - "v_tc_0/vtiming_out", - "v_axi4s_vid_out_0/vtiming_in" - ] - }, - "v_tpg_0_m_axis_video": { - "interface_ports": [ - "v_tpg_0/m_axis_video", - "v_axi4s_vid_out_0/video_in" - ] - } - }, - "nets": { - "CONST1_dout": { - "ports": [ - "CONST1/dout", - "v_tc_0/resetn", - "v_tc_0/s_axi_aclken", - "v_axi4s_vid_out_0/aclken", - "v_axi4s_vid_out_0/aresetn", - "v_axi4s_vid_out_0/vid_io_out_ce", - "v_tc_0/clken" - ] - }, - "clk_0_1": { - "ports": [ - "clk_0", - "v_tc_0/s_axi_aclk", - "v_tpg_0/ap_clk", - "v_axi4s_vid_out_0/aclk" - ] - }, - "fifo_read_level": { - "ports": [ - "v_axi4s_vid_out_0/fifo_read_level", - "fifo_read_level" - ] - }, - "overflow": { - "ports": [ - "v_axi4s_vid_out_0/overflow", - "overflow" - ] - }, - "processing_system7_0_FCLK_CLK1": { - "ports": [ - "PixelClk", - "rgb2dvi_0/PixelClk", - "rst_processing_system7_0_100M1/slowest_sync_clk", - "v_axi4s_vid_out_0/vid_io_out_clk", - "v_tc_0/clk" - ] - }, - "processing_system7_0_FCLK_RESET0_N": { - "ports": [ - "ext_reset_in", - "rst_processing_system7_0_100M1/ext_reset_in" - ] - }, - "rgb2dvi_0_TMDS_Clk_n": { - "ports": [ - "rgb2dvi_0/TMDS_Clk_n", - "TMDS_Clk_n_0" - ] - }, - "rgb2dvi_0_TMDS_Clk_p": { - "ports": [ - "rgb2dvi_0/TMDS_Clk_p", - "TMDS_Clk_p_0" - ] - }, - "rgb2dvi_0_TMDS_Data_n": { - "ports": [ - "rgb2dvi_0/TMDS_Data_n", - "TMDS_Data_n_0" - ] - }, - "rgb2dvi_0_TMDS_Data_p": { - "ports": [ - "rgb2dvi_0/TMDS_Data_p", - "TMDS_Data_p_0" - ] - }, - "rst_processing_system7_0_100M1_interconnect_aresetn": { - "ports": [ - "rst_processing_system7_0_100M1/interconnect_aresetn", - "interconnect_aresetn" - ] - }, - "rst_processing_system7_0_100M1_peripheral_reset": { - "ports": [ - "rst_processing_system7_0_100M1/peripheral_reset", - "rgb2dvi_0/aRst", - "v_axi4s_vid_out_0/vid_io_out_reset" - ] - }, - "underflow": { - "ports": [ - "v_axi4s_vid_out_0/underflow", - "underflow" - ] - }, - "v_axi4s_vid_out_0_sof_state_out": { - "ports": [ - "v_axi4s_vid_out_0/sof_state_out", - "v_tc_0/sof_state" - ] - }, - "vtg_ce": { - "ports": [ - "v_axi4s_vid_out_0/vtg_ce", - "v_tc_0/gen_clken" - ] - } - } } }, "interface_nets": { - "axi_dma_0_M_AXIS_MM2S": { - "interface_ports": [ - "axi_dma_0/M_AXIS_MM2S", - "d_axi_i2s_audio_0/AXI_MM2S" - ] - }, - "axi_dma_0_M_AXI_MM2S": { - "interface_ports": [ - "axi_dma_0/M_AXI_MM2S", - "axi_mem_intercon/S00_AXI" - ] - }, - "axi_dma_0_M_AXI_S2MM": { - "interface_ports": [ - "axi_dma_0/M_AXI_S2MM", - "axi_mem_intercon/S01_AXI" - ] - }, - "axi_gpio_0_GPIO": { - "interface_ports": [ - "btns_4bits", - "axi_gpio_0/GPIO" - ] - }, - "axi_iic_0_IIC": { - "interface_ports": [ - "iic_rtl", - "axi_iic_0/IIC" - ] - }, - "axi_mem_intercon_M00_AXI": { - "interface_ports": [ - "axi_mem_intercon/M00_AXI", - "processing_system7_0/S_AXI_HP0" - ] - }, - "d_axi_i2s_audio_0_AXI_S2MM": { - "interface_ports": [ - "axi_dma_0/S_AXIS_S2MM", - "d_axi_i2s_audio_0/AXI_S2MM" - ] - }, "processing_system7_0_DDR": { "interface_ports": [ "DDR", @@ -3802,263 +2165,66 @@ "processing_system7_0_M_AXI_GP0": { "interface_ports": [ "processing_system7_0/M_AXI_GP0", - "processing_system7_0_axi_periph/S00_AXI" + "ps7_0_axi_periph/S00_AXI" ] }, - "processing_system7_0_axi_periph_M00_AXI": { - "interface_ports": [ - "axi_dma_0/S_AXI_LITE", - "processing_system7_0_axi_periph/M00_AXI" - ] - }, - "processing_system7_0_axi_periph_M01_AXI": { - "interface_ports": [ - "d_axi_i2s_audio_0/AXI_L", - "processing_system7_0_axi_periph/M01_AXI" - ] - }, - "processing_system7_0_axi_periph_M02_AXI": { - "interface_ports": [ - "axi_iic_0/S_AXI", - "processing_system7_0_axi_periph/M02_AXI" - ] - }, - "processing_system7_0_axi_periph_M03_AXI": { + "ps7_0_axi_periph_M00_AXI": { "interface_ports": [ "axi_gpio_0/S_AXI", - "processing_system7_0_axi_periph/M03_AXI" - ] - }, - "processing_system7_0_axi_periph_M04_AXI": { - "interface_ports": [ - "processing_system7_0_axi_periph/M04_AXI", - "hier_0/s_axi_CTRL" - ] - }, - "processing_system7_0_axi_periph_M05_AXI": { - "interface_ports": [ - "processing_system7_0_axi_periph/M05_AXI", - "hier_0/ctrl" + "ps7_0_axi_periph/M00_AXI" ] } }, "nets": { - "SDATA_I_0_1": { + "axi_gpio_0_gpio_io_o": { "ports": [ - "SDATA_I", - "d_axi_i2s_audio_0/SDATA_I" - ] - }, - "axi_dma_0_mm2s_introut": { - "ports": [ - "axi_dma_0/mm2s_introut", - "xlconcat_0/In0" - ] - }, - "axi_dma_0_s2mm_introut": { - "ports": [ - "axi_dma_0/s2mm_introut", - "xlconcat_0/In1" - ] - }, - "axi_gpio_0_ip2intc_irpt": { - "ports": [ - "axi_gpio_0/ip2intc_irpt", - "xlconcat_0/In3" - ] - }, - "axi_iic_0_iic2intc_irpt": { - "ports": [ - "axi_iic_0/iic2intc_irpt", - "xlconcat_0/In2" - ] - }, - "d_axi_i2s_audio_0_BCLK_O": { - "ports": [ - "d_axi_i2s_audio_0/BCLK_O", - "BCLK_O" - ] - }, - "d_axi_i2s_audio_0_LRCLK_O": { - "ports": [ - "d_axi_i2s_audio_0/LRCLK_O", - "LRCLK_O" - ] - }, - "d_axi_i2s_audio_0_MCLK_O": { - "ports": [ - "d_axi_i2s_audio_0/MCLK_O", - "MCLK_O" - ] - }, - "d_axi_i2s_audio_0_SDATA_O": { - "ports": [ - "d_axi_i2s_audio_0/SDATA_O", - "SDATA_O" - ] - }, - "processing_system7_0_FCLK_CLK0": { - "ports": [ - "processing_system7_0/FCLK_CLK0", - "axi_dma_0/s_axi_lite_aclk", - "axi_dma_0/m_axi_mm2s_aclk", - "axi_dma_0/m_axi_s2mm_aclk", - "axi_gpio_0/s_axi_aclk", - "axi_iic_0/s_axi_aclk", - "axi_mem_intercon/ACLK", - "axi_mem_intercon/S00_ACLK", - "axi_mem_intercon/S01_ACLK", - "axi_mem_intercon/M00_ACLK", - "processing_system7_0/M_AXI_GP0_ACLK", - "processing_system7_0_axi_periph/ACLK", - "processing_system7_0_axi_periph/S00_ACLK", - "processing_system7_0_axi_periph/M00_ACLK", - "processing_system7_0_axi_periph/M01_ACLK", - "processing_system7_0_axi_periph/M02_ACLK", - "processing_system7_0_axi_periph/M03_ACLK", - "rst_processing_system7_0_100M/slowest_sync_clk", - "processing_system7_0/S_AXI_HP0_ACLK", - "d_axi_i2s_audio_0/CLK_100MHZ_I", - "d_axi_i2s_audio_0/S_AXIS_MM2S_ACLK", - "d_axi_i2s_audio_0/M_AXIS_S2MM_ACLK", - "d_axi_i2s_audio_0/AXI_L_aclk", - "hier_0/clk_0", - "processing_system7_0_axi_periph/M04_ACLK", - "processing_system7_0_axi_periph/M05_ACLK" + "axi_gpio_0/gpio_io_o", + "gpio_io_o_0" ] }, "processing_system7_0_FCLK_CLK1": { + "ports": [ + "processing_system7_0/FCLK_CLK0", + "FCLK_CLK0_0", + "axi_gpio_0/s_axi_aclk", + "ps7_0_axi_periph/ACLK", + "ps7_0_axi_periph/M00_ACLK", + "ps7_0_axi_periph/S00_ACLK", + "rst_ps7_0_100M/slowest_sync_clk", + "processing_system7_0/M_AXI_GP0_ACLK" + ] + }, + "processing_system7_0_FCLK_CLK2": { "ports": [ "processing_system7_0/FCLK_CLK1", - "hier_0/PixelClk" + "FCLK_CLK1_0" ] }, "processing_system7_0_FCLK_RESET0_N": { "ports": [ "processing_system7_0/FCLK_RESET0_N", - "rst_processing_system7_0_100M/ext_reset_in", - "hier_0/ext_reset_in" + "rst_ps7_0_100M/ext_reset_in" ] }, - "rgb2dvi_0_TMDS_Clk_n": { + "rst_ps7_0_100M_peripheral_aresetn": { "ports": [ - "hier_0/TMDS_Clk_n_0", - "TMDS_Clk_n_0" - ] - }, - "rgb2dvi_0_TMDS_Clk_p": { - "ports": [ - "hier_0/TMDS_Clk_p_0", - "TMDS_Clk_p_0" - ] - }, - "rgb2dvi_0_TMDS_Data_n": { - "ports": [ - "hier_0/TMDS_Data_n_0", - "TMDS_Data_n_0" - ] - }, - "rgb2dvi_0_TMDS_Data_p": { - "ports": [ - "hier_0/TMDS_Data_p_0", - "TMDS_Data_p_0" - ] - }, - "rst_processing_system7_0_100M_interconnect_aresetn": { - "ports": [ - "rst_processing_system7_0_100M/interconnect_aresetn", - "axi_mem_intercon/ARESETN", - "processing_system7_0_axi_periph/ARESETN" - ] - }, - "rst_processing_system7_0_100M_peripheral_aresetn": { - "ports": [ - "rst_processing_system7_0_100M/peripheral_aresetn", - "axi_dma_0/axi_resetn", + "rst_ps7_0_100M/peripheral_aresetn", "axi_gpio_0/s_axi_aresetn", - "axi_iic_0/s_axi_aresetn", - "axi_mem_intercon/S00_ARESETN", - "axi_mem_intercon/S01_ARESETN", - "axi_mem_intercon/M00_ARESETN", - "processing_system7_0_axi_periph/S00_ARESETN", - "processing_system7_0_axi_periph/M00_ARESETN", - "processing_system7_0_axi_periph/M01_ARESETN", - "processing_system7_0_axi_periph/M02_ARESETN", - "processing_system7_0_axi_periph/M03_ARESETN", - "d_axi_i2s_audio_0/S_AXIS_MM2S_ARESETN", - "d_axi_i2s_audio_0/M_AXIS_S2MM_ARESETN", - "d_axi_i2s_audio_0/AXI_L_aresetn", - "processing_system7_0_axi_periph/M04_ARESETN", - "processing_system7_0_axi_periph/M05_ARESETN" - ] - }, - "xlconcat_0_dout": { - "ports": [ - "xlconcat_0/dout", - "processing_system7_0/IRQ_F2P" + "ps7_0_axi_periph/ARESETN", + "ps7_0_axi_periph/M00_ARESETN", + "ps7_0_axi_periph/S00_ARESETN" ] } }, "addressing": { - "/axi_dma_0": { - "address_spaces": { - "Data_MM2S": { - "segments": { - "SEG_processing_system7_0_HP0_DDR_LOWOCM": { - "address_block": "/processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM", - "offset": "0x00000000", - "range": "512M" - } - } - }, - "Data_S2MM": { - "segments": { - "SEG_processing_system7_0_HP0_DDR_LOWOCM": { - "address_block": "/processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM", - "offset": "0x00000000", - "range": "512M" - } - } - } - } - }, "/processing_system7_0": { "address_spaces": { "Data": { "segments": { - "SEG_axi_dma_0_Reg": { - "address_block": "/axi_dma_0/S_AXI_LITE/Reg", - "offset": "0x40400000", - "range": "64K" - }, "SEG_axi_gpio_0_Reg": { "address_block": "/axi_gpio_0/S_AXI/Reg", "offset": "0x41200000", "range": "64K" - }, - "SEG_axi_iic_0_Reg": { - "address_block": "/axi_iic_0/S_AXI/Reg", - "offset": "0x41600000", - "range": "64K" - }, - "SEG_d_axi_i2s_audio_0_AXI_L_reg": { - "address_block": "/d_axi_i2s_audio_0/AXI_L/AXI_L_reg", - "offset": "0x43C00000", - "range": "64K", - "offset_base_param": "C_AXI_L_BASEADDR", - "offset_high_param": "C_AXI_L_HIGHADDR" - }, - "SEG_v_tc_0_Reg": { - "address_block": "/hier_0/v_tc_0/ctrl/Reg", - "offset": "0x43C20000", - "range": "64K" - }, - "SEG_v_tpg_0_Reg": { - "address_block": "/hier_0/v_tpg_0/s_axi_CTRL/Reg", - "offset": "0x43C10000", - "range": "64K", - "offset_base_param": "C_S_AXI_CTRL_BASEADDR", - "offset_high_param": "C_S_AXI_CTRL_HIGHADDR" } } } diff --git a/hdmi-out-test/hdmi-out-test.vitis/hdmi-out-test.files/Debug/hdmiout-test1.elf b/hdmi-out-test/hdmi-out-test.vitis/hdmi-out-test.files/Debug/hdmiout-test1.elf deleted file mode 100755 index a3e61fc..0000000 Binary files a/hdmi-out-test/hdmi-out-test.vitis/hdmi-out-test.files/Debug/hdmiout-test1.elf and /dev/null differ diff --git a/hdmi-out-test/hdmi-out-test.vitis/hdmi-out-test.files/Debug/test0.elf b/hdmi-out-test/hdmi-out-test.vitis/hdmi-out-test.files/Debug/test0.elf new file mode 100755 index 0000000..69a0c4b Binary files /dev/null and b/hdmi-out-test/hdmi-out-test.vitis/hdmi-out-test.files/Debug/test0.elf differ diff --git a/hdmi-out-test/hdmi-out-test.vitis/hdmi-out-test.files/src/main.c b/hdmi-out-test/hdmi-out-test.vitis/hdmi-out-test.files/src/helloworld.c similarity index 77% rename from hdmi-out-test/hdmi-out-test.vitis/hdmi-out-test.files/src/main.c rename to hdmi-out-test/hdmi-out-test.vitis/hdmi-out-test.files/src/helloworld.c index df8dfec..b4623c3 100644 --- a/hdmi-out-test/hdmi-out-test.vitis/hdmi-out-test.files/src/main.c +++ b/hdmi-out-test/hdmi-out-test.vitis/hdmi-out-test.files/src/helloworld.c @@ -1,20 +1,20 @@ #include -//#include "platform.h" #include "xil_printf.h" -#include "xv_tpg.h" -#include "xvtc.h" +//#include "xv_tpg.h" +//#include "xvtc.h" int main() { //init_platform(); int Status; - XV_tpg tpg_inst; // Instance of the TPG core - XVtc VtcInst; // Instance of the VTC core + //XV_tpg tpg_inst; // Instance of the TPG core + //XVtc VtcInst; // Instance of the VTC core - print("--- hdmi-out-test ---\n\r"); + print("--- hdmi-in-test ---\n\r"); //--( TPG Initialization + /* print("TPG Initialization\n\r"); Status = XV_tpg_Initialize(&tpg_inst, XPAR_XV_TPG_0_DEVICE_ID); if(Status!= XST_SUCCESS) @@ -37,9 +37,11 @@ int main() XV_tpg_EnableAutoRestart(&tpg_inst); XV_tpg_Start(&tpg_inst); xil_printf("TPG started!\r\n"); + */ //--) //--( VTC Initialization + /* print("VTC Initialization\n\r"); XVtc_Config *Config; XVtc_Timing ti; @@ -74,8 +76,14 @@ int main() //Enable the vtc XVtc_Enable(&VtcInst); xil_printf("VTC enabled!\r\n"); + */ //--) + xil_printf("\r\nInstructions:\r\n"); + xil_printf("1. connect HDMI_OUT to HDMI_IN\r\n"); + xil_printf("2. Check LD1,LD0 are on\r\n"); + xil_printf("3. open ila_1 on vivado (connected to hdmi input after tmds2rgb conversion\r\n"); + xil_printf("4. trigger it and compare results with logs/hdmi-loop-test-ila.png \r\n"); while(1){ } diff --git a/hdmi-out-test/hdmi-out-test.xpr b/hdmi-out-test/hdmi-out-test.xpr index 98db169..1157776 100644 --- a/hdmi-out-test/hdmi-out-test.xpr +++ b/hdmi-out-test/hdmi-out-test.xpr @@ -6,7 +6,7 @@ -