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hdmi-out-test: bd based -> hdl based 

changed hdmi-out-test to hdl based
using projectF dvi output instead of digilent ip cores
seems simpler to understand and use
master
neyko3 2024-08-16 21:59:34 +09:00
parent 3fa8109f96
commit 75d0481279
36 changed files with 1076 additions and 6755 deletions
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1
hdmi-out-test/digilent.ipdefs

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Subproject commit 7a5edbe128009522608a67c76e5346edbcf95d95

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hdmi-out-test/docs/pg016_v_tc.pdf
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hdmi-out-test/docs/pg044_v_axis_vid_out.pdf
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hdmi-out-test/docs/pg103-v-tpg-en-us-8.2.pdf
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hdmi-out-test/design_1_wrapper.xsa → hdmi-out-test/dvi_top.xsa
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hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/component.xml
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189
hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/DCM.vhd
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-- file: DCM.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____12.289______0.000______50.0______335.213____300.046
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity DCM is
port
(-- Clock in ports
CLK_100 : in std_logic;
-- Clock out ports
CLK_12_288 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end DCM;
architecture xilinx of DCM is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "DCM,clk_wiz_v3_6,{component_name=DCM,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1_unused : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1 <= CLK_100;
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
plle2_adv_inst : PLLE2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 5,
CLKFBOUT_MULT => 51,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 83,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN1_PERIOD => 10.000,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1_unused,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
-- Input clock control
CLKFBIN => clkfbout,
CLKIN1 => clkin1,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Other control and status signals
LOCKED => LOCKED,
PWRDWN => '0',
RST => RESET);
-- Output buffering
-------------------------------------
-- -- Output buffering
-- -------------------------------------
-- clkf_buf : BUFG
-- port map
-- (O => clkfbout_buf,
-- I => clkfbout);
--
--
clkout1_buf : BUFG
port map
(O => CLK_12_288,
I => clkout0);
--clkfbout_buf <= clkfbout;
--CLK_12_288 <= clkout0;
end xilinx;

66
hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/Div_by_4.vhd
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:49:17 04/02/2014
-- Design Name:
-- Module Name: Div_by_4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Div_by_4 is
Port
(
CE_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
DIV_O : out STD_LOGIC
);
end Div_by_4;
architecture Behavioral of Div_by_4 is
signal cnt : integer range 0 to 2 :=0;
signal clk_div : STD_LOGIC := '0';
begin
process (CLK_I)
begin
if (CLK_I'event and CLK_I = '1') then
if (CE_I = '1') then
cnt <= cnt + 1;
if cnt = 2 then
cnt <= 0;
clk_div <= not clk_div;
end if;
else
cnt <= 0;
end if;
end if;
end process;
DIV_O <= clk_div;
end Behavioral;

61
hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/Sync_ff.vhd
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-------------------------------------------------------------------------------
--
-- COPYRIGHT (C) 2012, Digilent RO. All rights reserved
--
-------------------------------------------------------------------------------
-- FILE NAME : Sync_ff.vhd
-- MODULE NAME : Synchornisation Flip-Flops
-- AUTHOR : Hegbeli Ciprian
-- AUTHOR'S EMAIL : ciprian.hegbeli@digilent.ro
-------------------------------------------------------------------------------
-- REVISION HISTORY
-- VERSION DATE AUTHOR DESCRIPTION
-- 1.0 2014-04-02 CiprianH Created
-------------------------------------------------------------------------------
-- KEYWORDS : Sync
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
------------------------------------------------------------------------
-- Module Declaration
------------------------------------------------------------------------
entity Sync_ff is
Port (
-- Input Clock
CLK : in STD_LOGIC;
-- Asynchorn signal
D_I : in STD_LOGIC;
-- Sync signal
Q_O : out STD_LOGIC
);
end Sync_ff;
architecture Behavioral of Sync_ff is
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
signal sreg : std_logic_vector(1 downto 0);
attribute ASYNC_REG : string;
attribute ASYNC_REG of sreg : signal is "TRUE";
attribute TIG : string;
attribute TIG of D_I: signal is "TRUE";
begin
------------------------------------------------------------------------
-- Output synchro with second CLK
------------------------------------------------------------------------
sync_b_proc_2: process(CLK)
begin
if rising_edge(CLK) then
Q_O <= sreg(1);
sreg <= sreg(0) & D_I;
end if;
end process;
end Behavioral;

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hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/d_axi_i2s_audio.xdc
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set_false_path -through [get_pins -filter {NAME =~ */Inst_I2sCtl/Inst_SyncBit_*/sreg_reg[0]/D} -hier]
set_false_path -through [get_pins -filter {NAME =~ */Inst_I2sCtl/Inst_Rst_Sync*/FDRE_inst_*/PRE} -hier]
set_property ASYNC_REG true [get_cells -filter {NAME =~ */Inst_I2sCtl/Inst_Rst_Sync*} -hier]

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hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/d_axi_i2s_audio_v2_0.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity d_axi_i2s_audio_v2_0 is
generic (
C_DATA_WIDTH : integer := 24;
-- AXI4-Stream parameter
C_AXI_STREAM_DATA_WIDTH : integer := 32;
-- Parameters of Axi Slave Bus Interface AXI_L
C_AXI_L_DATA_WIDTH : integer := 32;
C_AXI_L_ADDR_WIDTH : integer := 6
);
port (
-- I2S
BCLK_O : out std_logic;
BCLK_I : in std_logic;
BCLK_T : out std_logic;
LRCLK_O : out std_logic;
LRCLK_I : in std_logic;
LRCLK_T : out std_logic;
MCLK_O : out std_logic;
SDATA_I : in std_logic;
SDATA_O : out std_logic;
CLK_100MHZ_I : in std_logic;
-- AXI4-Stream
S_AXIS_MM2S_ACLK : in std_logic;
S_AXIS_MM2S_ARESETN : in std_logic;
S_AXIS_MM2S_TREADY : out std_logic;
S_AXIS_MM2S_TDATA : in std_logic_vector(C_AXI_STREAM_DATA_WIDTH-1 downto 0);
S_AXIS_MM2S_TKEEP : in std_logic_vector((C_AXI_STREAM_DATA_WIDTH/8)-1 downto 0);
S_AXIS_MM2S_TLAST : in std_logic;
S_AXIS_MM2S_TVALID : in std_logic;
M_AXIS_S2MM_ACLK : in std_logic;
M_AXIS_S2MM_ARESETN : in std_logic;
M_AXIS_S2MM_TVALID : out std_logic;
M_AXIS_S2MM_TDATA : out std_logic_vector(C_AXI_STREAM_DATA_WIDTH-1 downto 0);
M_AXIS_S2MM_TKEEP : out std_logic_vector((C_AXI_STREAM_DATA_WIDTH/8)-1 downto 0);
M_AXIS_S2MM_TLAST : out std_logic;
M_AXIS_S2MM_TREADY : in std_logic;
-- Ports of Axi Slave Bus Interface AXI_L
AXI_L_aclk : in std_logic;
AXI_L_aresetn : in std_logic;
AXI_L_awaddr : in std_logic_vector(C_AXI_L_ADDR_WIDTH-1 downto 0);
AXI_L_awprot : in std_logic_vector(2 downto 0);
AXI_L_awvalid : in std_logic;
AXI_L_awready : out std_logic;
AXI_L_wdata : in std_logic_vector(C_AXI_L_DATA_WIDTH-1 downto 0);
AXI_L_wstrb : in std_logic_vector((C_AXI_L_DATA_WIDTH/8)-1 downto 0);
AXI_L_wvalid : in std_logic;
AXI_L_wready : out std_logic;
AXI_L_bresp : out std_logic_vector(1 downto 0);
AXI_L_bvalid : out std_logic;
AXI_L_bready : in std_logic;
AXI_L_araddr : in std_logic_vector(C_AXI_L_ADDR_WIDTH-1 downto 0);
AXI_L_arprot : in std_logic_vector(2 downto 0);
AXI_L_arvalid : in std_logic;
AXI_L_arready : out std_logic;
AXI_L_rdata : out std_logic_vector(C_AXI_L_DATA_WIDTH-1 downto 0);
AXI_L_rresp : out std_logic_vector(1 downto 0);
AXI_L_rvalid : out std_logic;
AXI_L_rready : in std_logic
);
end d_axi_i2s_audio_v2_0;
architecture arch_imp of d_axi_i2s_audio_v2_0 is
-- component declaration
component d_axi_i2s_audio_v2_0_AXI_L is
generic (
-- Stream width constant
C_AXI_STREAM_DATA_WIDTH : integer := 32;
-- audio data width constant
C_DATA_WIDTH : integer := 24;
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 6
);
port (
-- I2S
BCLK_O : out std_logic;
BCLK_I : in std_logic;
BCLK_T : out std_logic;
LRCLK_O : out std_logic;
LRCLK_I : in std_logic;
LRCLK_T : out std_logic;
MCLK_O : out std_logic;
SDATA_I : in std_logic;
SDATA_O : out std_logic;
CLK_100MHZ_I : in std_logic;
-- AXI4-Stream
S_AXIS_MM2S_ACLK : in std_logic;
S_AXIS_MM2S_ARESETN : in std_logic;
S_AXIS_MM2S_TREADY : out std_logic;
S_AXIS_MM2S_TDATA : in std_logic_vector(C_AXI_STREAM_DATA_WIDTH-1 downto 0);
S_AXIS_MM2S_TKEEP : in std_logic_vector((C_AXI_STREAM_DATA_WIDTH/8)-1 downto 0);
S_AXIS_MM2S_TLAST : in std_logic;
S_AXIS_MM2S_TVALID : in std_logic;
M_AXIS_S2MM_ACLK : in std_logic;
M_AXIS_S2MM_ARESETN : in std_logic;
M_AXIS_S2MM_TVALID : out std_logic;
M_AXIS_S2MM_TDATA : out std_logic_vector(C_AXI_STREAM_DATA_WIDTH-1 downto 0);
M_AXIS_S2MM_TKEEP : out std_logic_vector((C_AXI_STREAM_DATA_WIDTH/8)-1 downto 0);
M_AXIS_S2MM_TLAST : out std_logic;
M_AXIS_S2MM_TREADY : in std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component d_axi_i2s_audio_v2_0_AXI_L;
begin
-- Instantiation of Axi Bus Interface AXI_L
d_axi_i2s_audio_v2_0_AXI_L_inst : d_axi_i2s_audio_v2_0_AXI_L
generic map (
C_DATA_WIDTH => C_DATA_WIDTH,
C_AXI_STREAM_DATA_WIDTH => C_AXI_STREAM_DATA_WIDTH,
C_S_AXI_DATA_WIDTH => C_AXI_L_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_AXI_L_ADDR_WIDTH
)
port map (
BCLK_O => BCLK_O,
BCLK_I => BCLK_I,
BCLK_T => BCLK_T,
LRCLK_O => LRCLK_O,
LRCLK_I => LRCLK_I,
LRCLK_T => LRCLK_T,
MCLK_O => MCLK_O,
SDATA_I => SDATA_I,
SDATA_O => SDATA_O,
CLK_100MHZ_I => CLK_100MHZ_I,
S_AXIS_MM2S_ACLK => S_AXIS_MM2S_ACLK,
S_AXIS_MM2S_ARESETN => S_AXIS_MM2S_ARESETN,
S_AXIS_MM2S_TREADY => S_AXIS_MM2S_TREADY,
S_AXIS_MM2S_TDATA => S_AXIS_MM2S_TDATA,
S_AXIS_MM2S_TKEEP => S_AXIS_MM2S_TKEEP,
S_AXIS_MM2S_TLAST => S_AXIS_MM2S_TLAST,
S_AXIS_MM2S_TVALID => S_AXIS_MM2S_TVALID,
M_AXIS_S2MM_ACLK => M_AXIS_S2MM_ACLK,
M_AXIS_S2MM_ARESETN => M_AXIS_S2MM_ARESETN,
M_AXIS_S2MM_TDATA => M_AXIS_S2MM_TDATA,
M_AXIS_S2MM_TLAST => M_AXIS_S2MM_TLAST,
M_AXIS_S2MM_TREADY => M_AXIS_S2MM_TREADY,
M_AXIS_S2MM_TKEEP => M_AXIS_S2MM_TKEEP,
M_AXIS_S2MM_TVALID => M_AXIS_S2MM_TVALID,
S_AXI_ACLK => AXI_L_aclk,
S_AXI_ARESETN => AXI_L_aresetn,
S_AXI_AWADDR => AXI_L_awaddr,
S_AXI_AWPROT => AXI_L_awprot,
S_AXI_AWVALID => AXI_L_awvalid,
S_AXI_AWREADY => AXI_L_awready,
S_AXI_WDATA => AXI_L_wdata,
S_AXI_WSTRB => AXI_L_wstrb,
S_AXI_WVALID => AXI_L_wvalid,
S_AXI_WREADY => AXI_L_wready,
S_AXI_BRESP => AXI_L_bresp,
S_AXI_BVALID => AXI_L_bvalid,
S_AXI_BREADY => AXI_L_bready,
S_AXI_ARADDR => AXI_L_araddr,
S_AXI_ARPROT => AXI_L_arprot,
S_AXI_ARVALID => AXI_L_arvalid,
S_AXI_ARREADY => AXI_L_arready,
S_AXI_RDATA => AXI_L_rdata,
S_AXI_RRESP => AXI_L_rresp,
S_AXI_RVALID => AXI_L_rvalid,
S_AXI_RREADY => AXI_L_rready
);
-- Add user logic here
-- User logic ends
end arch_imp;

781
hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/d_axi_i2s_audio_v2_0_AXI_L.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity d_axi_i2s_audio_v2_0_AXI_L is
generic (
-- Stream width constant
C_AXI_STREAM_DATA_WIDTH : integer := 32;
-- audio data width constant
C_DATA_WIDTH : integer := 24;
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 6
);
port (
-- I2S
BCLK_O : out std_logic;
BCLK_I : in std_logic;
BCLK_T : out std_logic;
LRCLK_O : out std_logic;
LRCLK_I : in std_logic;
LRCLK_T : out std_logic;
MCLK_O : out std_logic;
SDATA_I : in std_logic;
SDATA_O : out std_logic;
CLK_100MHZ_I : in std_logic;
-- AXI4-Stream
S_AXIS_MM2S_ACLK : in std_logic;
S_AXIS_MM2S_ARESETN : in std_logic;
S_AXIS_MM2S_TREADY : out std_logic;
S_AXIS_MM2S_TDATA : in std_logic_vector(C_AXI_STREAM_DATA_WIDTH-1 downto 0);
S_AXIS_MM2S_TKEEP : in std_logic_vector((C_AXI_STREAM_DATA_WIDTH/8)-1 downto 0);
S_AXIS_MM2S_TLAST : in std_logic;
S_AXIS_MM2S_TVALID : in std_logic;
M_AXIS_S2MM_ACLK : in std_logic;
M_AXIS_S2MM_ARESETN : in std_logic;
M_AXIS_S2MM_TVALID : out std_logic;
M_AXIS_S2MM_TDATA : out std_logic_vector(C_AXI_STREAM_DATA_WIDTH-1 downto 0);
M_AXIS_S2MM_TKEEP : out std_logic_vector((C_AXI_STREAM_DATA_WIDTH/8)-1 downto 0);
M_AXIS_S2MM_TLAST : out std_logic;
M_AXIS_S2MM_TREADY : in std_logic;
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end d_axi_i2s_audio_v2_0_AXI_L;
architecture arch_imp of d_axi_i2s_audio_v2_0_AXI_L is
-- Them main control component of the I2S protocol
component i2s_rx_tx
generic(
C_DATA_WIDTH : integer := 24);
port(
CLK_I : in std_logic;
RST_I : in std_logic;
TX_RS_I : in std_logic;
RX_RS_I : in std_logic;
TX_FIFO_RST_I : in std_logic;
TX_FIFO_D_I : in std_logic_vector(C_DATA_WIDTH-1 downto 0);
TX_FIFO_WR_EN_I : in std_logic;
RX_FIFO_RST_I : in std_logic;
RX_FIFO_D_O : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
RX_FIFO_RD_EN_I : in std_logic;
TX_FIFO_EMPTY_O : out std_logic;
TX_FIFO_FULL_O : out std_logic;
RX_FIFO_EMPTY_O : out std_logic;
RX_FIFO_FULL_O : out std_logic;
CLK_100MHZ_I : in std_logic;
CTL_MASTER_MODE_I : in std_logic;
-- DBG
DBG_TX_FIFO_RST_I : out std_logic;
DBG_TX_FIFO_RD_EN_I : out std_logic;
DBG_TX_FIFO_WR_EN_I : out std_logic;
DBG_TX_FIFO_EMPTY_O : out std_logic;
DBG_TX_FIFO_FULL_O : out std_logic;
DBG_TX_FIFO_D_I : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
DBG_TX_FIFO_D_O : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
DBG_TX_RS_I : out std_logic;
DBG_RX_FIFO_RST_I : out std_logic;
DBG_RX_FIFO_WR_EN_I : out std_logic;
DBG_RX_FIFO_RD_EN_I : out std_logic;
DBG_RX_FIFO_FULL_O : out std_logic;
DBG_RX_FIFO_EMPTY_O : out std_logic;
DBG_RX_FIFO_D_O : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
DBG_RX_FIFO_D_I : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
DBG_RX_RS_I : out std_logic;
SAMPLING_RATE_I : in std_logic_vector(3 downto 0);
BCLK_O : out std_logic;
BCLK_I : in std_logic;
BCLK_T : out std_logic;
LRCLK_O : out std_logic;
LRCLK_I : in std_logic;
LRCLK_T : out std_logic;
MCLK_O : out std_logic;
SDATA_I : in std_logic;
SDATA_O : out std_logic);
end component;
-- the stream module which controls the reciving and transmiting of data
-- on the AXI stream
component i2s_stream
generic(
C_AXI_STREAM_DATA_WIDTH : integer := 32;
C_DATA_WIDTH : integer := 24
);
port(
TX_FIFO_FULL_I : in std_logic;
RX_FIFO_EMPTY_I : in std_logic;
TX_FIFO_D_O : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
RX_FIFO_D_I : in std_logic_vector(C_DATA_WIDTH-1 downto 0);
NR_OF_SMPL_I : in std_logic_vector(20 downto 0);
TX_STREAM_EN_I : in std_logic;
RX_STREAM_EN_I : in std_logic;
S_AXIS_MM2S_ACLK_I : in std_logic;
S_AXIS_MM2S_ARESETN : in std_logic;
S_AXIS_MM2S_TREADY_O : out std_logic;
S_AXIS_MM2S_TDATA_I : in std_logic_vector(C_AXI_STREAM_DATA_WIDTH-1 downto 0);
S_AXIS_MM2S_TLAST_I : in std_logic;
S_AXIS_MM2S_TVALID_I : in std_logic;
M_AXIS_S2MM_ACLK_I : in std_logic;
M_AXIS_S2MM_ARESETN : in std_logic;
M_AXIS_S2MM_TDATA_O : out std_logic_vector(C_AXI_STREAM_DATA_WIDTH-1 downto 0);
M_AXIS_S2MM_TLAST_O : out std_logic;
M_AXIS_S2MM_TVALID_O : out std_logic;
M_AXIS_S2MM_TREADY_I : in std_logic;
M_AXIS_S2MM_TKEEP_O : out std_logic_vector((C_AXI_STREAM_DATA_WIDTH/8)-1 downto 0)
);
end component;
-- Main AXI stream CLK divider (by 4) for generating the TX_FIFO_WR_EN_I signal
component Div_by_4
port(
CE_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
DIV_O : out STD_LOGIC
);
end component;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
-- I2S control signals
signal I2S_RST_I : std_logic;
signal TX_RS_I : std_logic;
signal RX_RS_I : std_logic;
-- TX_FIFO siganals
signal TX_FIFO_RST_I : std_logic;
signal TX_FIFO_WR_EN_I : std_logic;
signal TX_FIFO_D_I : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal TX_FIFO_D_O : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal TX_FIFO_EMPTY_O : std_logic;
signal TX_FIFO_FULL_O : std_logic;
-- RX_FIFO siganals
signal RX_FIFO_RST_I : std_logic;
signal RX_FIFO_RD_EN_I : std_logic;
signal RX_FIFO_D_O : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal RX_FIFO_EMPTY_O : std_logic;
signal RX_FIFO_FULL_O : std_logic;
-- Clock control signals (BCLK/LRCLK)
signal CTL_MASTER_MODE_I : std_logic;
signal SAMPLING_RATE_I : std_logic_vector(3 downto 0);
--Stream specific signals
signal NR_OF_SMPL_I : std_logic_vector(20 downto 0);
signal DIV_CE : std_logic;
signal TX_FIFO_WR_EN_STREAM_O : std_logic;
signal TX_STREAM_EN_I : std_logic;
signal RX_STREAM_EN_I : std_logic;
signal RxFifoRdEn : std_logic;
signal RxFifoRdEn_dly : std_logic;
signal TxFifoWrEn : std_logic;
signal TxFifoWrEn_dly : std_logic;
signal M_AXIS_S2MM_TVALID_int : std_logic;
-- DBG
signal DBG_TX_FIFO_RST_I : std_logic;
signal DBG_TX_FIFO_RD_EN_I : std_logic;
signal DBG_TX_FIFO_WR_EN_I : std_logic;
signal DBG_TX_FIFO_EMPTY_O : std_logic;
signal DBG_TX_FIFO_FULL_O : std_logic;
signal DBG_TX_FIFO_D_O : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal DBG_TX_FIFO_D_I : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal DBG_RX_FIFO_RST_I : std_logic;
signal DBG_RX_FIFO_WR_EN_I : std_logic;
signal DBG_RX_FIFO_RD_EN_I : std_logic;
signal DBG_RX_FIFO_FULL_O : std_logic;
signal DBG_RX_FIFO_EMPTY_O : std_logic;
signal DBG_RX_FIFO_D_O : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal DBG_RX_FIFO_D_I : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal DBG_TX_RS_I : std_logic;
signal DBG_RX_RS_I : std_logic;
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 3;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 10
signal I2S_RESET_REG :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal I2S_TRANSFER_CONTROL_REG :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal I2S_FIFO_CONTROL_REG :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal I2S_DATA_IN_REG :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal I2S_DATA_OUT_REG :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal I2S_STATUS_REG :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal I2S_CLOCK_CONTROL_REG :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal I2S_PERIOD_COUNT_REG :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal I2S_STREAM_CONTROL_REG :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
attribute KEEP : string;
attribute KEEP of DBG_TX_FIFO_RST_I : signal is "TRUE";
attribute KEEP of DBG_TX_FIFO_WR_EN_I : signal is "TRUE";
attribute KEEP of DBG_TX_FIFO_RD_EN_I : signal is "TRUE";
attribute KEEP of DBG_TX_FIFO_EMPTY_O : signal is "TRUE";
attribute KEEP of DBG_TX_FIFO_FULL_O : signal is "TRUE";
attribute KEEP of DBG_TX_FIFO_D_I : signal is "TRUE";
attribute KEEP of DBG_TX_FIFO_D_O : signal is "TRUE";
attribute KEEP of DBG_RX_FIFO_RST_I : signal is "TRUE";
attribute KEEP of DBG_RX_FIFO_WR_EN_I : signal is "TRUE";
attribute KEEP of DBG_RX_FIFO_RD_EN_I : signal is "TRUE";
attribute KEEP of DBG_RX_FIFO_FULL_O : signal is "TRUE";
attribute KEEP of DBG_RX_FIFO_EMPTY_O : signal is "TRUE";
attribute KEEP of DBG_RX_FIFO_D_I : signal is "TRUE";
attribute KEEP of DBG_RX_FIFO_D_O : signal is "TRUE";
attribute KEEP of DBG_TX_RS_I : signal is "TRUE";
attribute KEEP of DBG_RX_RS_I : signal is "TRUE";
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
I2S_RST_I <= I2S_RESET_REG(0);
TX_RS_I <= I2S_TRANSFER_CONTROL_REG(0);
RX_RS_I <= I2S_TRANSFER_CONTROL_REG(1);
TX_FIFO_WR_EN_I <= not TX_FIFO_FULL_O when (RX_STREAM_EN_I = '1' and S_AXIS_MM2S_TVALID = '1') else
TxFifoWrEn when (RX_STREAM_EN_I = '0') else
'0';
RX_FIFO_RD_EN_I <= not RX_FIFO_EMPTY_O when (TX_STREAM_EN_I = '1' and M_AXIS_S2MM_TREADY = '1' and M_AXIS_S2MM_TVALID_int = '1') else
RxFifoRdEn when (TX_STREAM_EN_I = '0') else
'0';
TX_FIFO_RST_I <= (not S_AXIS_MM2S_ARESETN) or I2S_FIFO_CONTROL_REG(30);
RX_FIFO_RST_I <= (not M_AXIS_S2MM_ARESETN) or I2S_FIFO_CONTROL_REG(31);
TX_FIFO_D_I <= TX_FIFO_D_O when RX_STREAM_EN_I = '1' else
I2S_DATA_IN_REG(C_DATA_WIDTH-1 downto 0);
SAMPLING_RATE_I <= I2S_CLOCK_CONTROL_REG(3 downto 0);
CTL_MASTER_MODE_I <= I2S_CLOCK_CONTROL_REG(16);
NR_OF_SMPL_I <= I2S_PERIOD_COUNT_REG(20 downto 0);
TX_STREAM_EN_I <= I2S_STREAM_CONTROL_REG(0);
RX_STREAM_EN_I <= I2S_STREAM_CONTROL_REG(1);
DIV_CE <= RX_STREAM_EN_I and (S_AXIS_MM2S_TVALID and not TX_FIFO_FULL_O);
-- DBG_RX_FIFO_D_O <= I2S_DATA_OUT_REG(C_DATA_WIDTH-1 downto 0);
M_AXIS_S2MM_TVALID <= M_AXIS_S2MM_TVALID_int;
RDWR_PULSE: process(S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
RxFifoRdEn_dly <= I2S_FIFO_CONTROL_REG(1);
TxFifoWrEn_dly <= I2S_FIFO_CONTROL_REG(0);
end if;
end process RDWR_PULSE;
RxFifoRdEn <= I2S_FIFO_CONTROL_REG(1) and not RxFifoRdEn_dly;
TxFifoWrEn <= I2S_FIFO_CONTROL_REG(0) and not TxFifoWrEn_dly;
------------------------------------------------------------------------
-- Instantiaton of the I2S controler
------------------------------------------------------------------------
Inst_I2sCtl: i2s_rx_tx
generic map(
C_DATA_WIDTH => C_DATA_WIDTH)
port map(
CLK_I => S_AXI_ACLK,
RST_I => I2S_RST_I,
TX_RS_I => TX_RS_I,
RX_RS_I => RX_RS_I,
TX_FIFO_RST_I => TX_FIFO_RST_I,
TX_FIFO_D_I => TX_FIFO_D_I,
TX_FIFO_WR_EN_I => TX_FIFO_WR_EN_I,
RX_FIFO_RST_I => RX_FIFO_RST_I,
RX_FIFO_D_O => RX_FIFO_D_O,
RX_FIFO_RD_EN_I => RX_FIFO_RD_EN_I,
TX_FIFO_EMPTY_O => TX_FIFO_EMPTY_O,
TX_FIFO_FULL_O => TX_FIFO_FULL_O,
RX_FIFO_EMPTY_O => RX_FIFO_EMPTY_O,
RX_FIFO_FULL_O => RX_FIFO_FULL_O,
CLK_100MHZ_I => CLK_100MHZ_I,
CTL_MASTER_MODE_I => CTL_MASTER_MODE_I,
-- DBG
DBG_TX_FIFO_RST_I => DBG_TX_FIFO_RST_I,
DBG_TX_FIFO_RD_EN_I => DBG_TX_FIFO_RD_EN_I,
DBG_TX_FIFO_WR_EN_I => DBG_TX_FIFO_WR_EN_I,
DBG_TX_FIFO_EMPTY_O => DBG_TX_FIFO_EMPTY_O,
DBG_TX_FIFO_FULL_O => DBG_TX_FIFO_FULL_O,
DBG_TX_FIFO_D_O => DBG_TX_FIFO_D_O,
DBG_TX_FIFO_D_I => DBG_TX_FIFO_D_I,
DBG_TX_RS_I => DBG_TX_RS_I,
DBG_RX_FIFO_RST_I => DBG_RX_FIFO_RST_I,
DBG_RX_FIFO_WR_EN_I => DBG_RX_FIFO_WR_EN_I,
DBG_RX_FIFO_RD_EN_I => DBG_RX_FIFO_RD_EN_I,
DBG_RX_FIFO_FULL_O => DBG_RX_FIFO_FULL_O,
DBG_RX_FIFO_EMPTY_O => DBG_RX_FIFO_EMPTY_O,
DBG_RX_FIFO_D_I => DBG_RX_FIFO_D_I,
DBG_RX_FIFO_D_O => DBG_RX_FIFO_D_O,
DBG_RX_RS_I => DBG_RX_RS_I,
SAMPLING_RATE_I => SAMPLING_RATE_I,
BCLK_O => BCLK_O,
BCLK_I => BCLK_I,
BCLK_T => BCLK_T,
LRCLK_O => LRCLK_O,
LRCLK_I => LRCLK_I,
LRCLK_T => LRCLK_T,
MCLK_O => MCLK_O,
SDATA_I => SDATA_I,
SDATA_O => SDATA_O);
------------------------------------------------------------------------
-- Instantiaton of the AXI stream controler
------------------------------------------------------------------------
Inst_I2sStream: i2s_stream
generic map(
C_AXI_STREAM_DATA_WIDTH => C_AXI_STREAM_DATA_WIDTH,
C_DATA_WIDTH => C_DATA_WIDTH
)
port map(
TX_FIFO_FULL_I => TX_FIFO_FULL_O,
RX_FIFO_EMPTY_I => RX_FIFO_EMPTY_O,
TX_FIFO_D_O => TX_FIFO_D_O,
RX_FIFO_D_I => RX_FIFO_D_O,
NR_OF_SMPL_I => NR_OF_SMPL_I,
TX_STREAM_EN_I => TX_STREAM_EN_I,
RX_STREAM_EN_I => RX_STREAM_EN_I,
S_AXIS_MM2S_ACLK_I => S_AXIS_MM2S_ACLK,
S_AXIS_MM2S_ARESETN => S_AXIS_MM2S_ARESETN,
S_AXIS_MM2S_TREADY_O => S_AXIS_MM2S_TREADY,
S_AXIS_MM2S_TDATA_I => S_AXIS_MM2S_TDATA,
S_AXIS_MM2S_TLAST_I => S_AXIS_MM2S_TLAST,
S_AXIS_MM2S_TVALID_I => S_AXIS_MM2S_TVALID,
M_AXIS_S2MM_ACLK_I => M_AXIS_S2MM_ACLK,
M_AXIS_S2MM_ARESETN => M_AXIS_S2MM_ARESETN,
M_AXIS_S2MM_TDATA_O => M_AXIS_S2MM_TDATA,
M_AXIS_S2MM_TLAST_O => M_AXIS_S2MM_TLAST,
M_AXIS_S2MM_TREADY_I => M_AXIS_S2MM_TREADY,
M_AXIS_S2MM_TKEEP_O => M_AXIS_S2MM_TKEEP,
M_AXIS_S2MM_TVALID_O => M_AXIS_S2MM_TVALID_int
);
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
I2S_RESET_REG <= (others => '0');
I2S_TRANSFER_CONTROL_REG <= (others => '0');
I2S_FIFO_CONTROL_REG <= (others => '0');
I2S_DATA_IN_REG <= (others => '0');
I2S_DATA_OUT_REG <= (others => '0');
I2S_STATUS_REG <= (others => '0');
I2S_CLOCK_CONTROL_REG <= (others => '0');
I2S_PERIOD_COUNT_REG <= (others => '0');
I2S_STREAM_CONTROL_REG <= (others => '0');
slv_reg9 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"0000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
I2S_RESET_REG(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
I2S_TRANSFER_CONTROL_REG(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
I2S_FIFO_CONTROL_REG(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
I2S_DATA_IN_REG(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
I2S_CLOCK_CONTROL_REG(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
I2S_PERIOD_COUNT_REG(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 8
I2S_STREAM_CONTROL_REG(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 9
slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
I2S_DATA_OUT_REG(31 downto 31-C_DATA_WIDTH) <= (others => '0');
I2S_DATA_OUT_REG(C_DATA_WIDTH-1 downto 0) <= RX_FIFO_D_O;
I2S_STATUS_REG(0) <= TX_FIFO_EMPTY_O;
I2S_STATUS_REG(1) <= TX_FIFO_FULL_O;
I2S_STATUS_REG(15 downto 2) <= (others => '0');
I2S_STATUS_REG(16) <= RX_FIFO_EMPTY_O;
I2S_STATUS_REG(17) <= RX_FIFO_FULL_O;
I2S_STATUS_REG(31 downto 18) <= (others => '0');
end case;
end if;
I2S_DATA_OUT_REG(31 downto 31-C_DATA_WIDTH) <= (others => '0');
I2S_DATA_OUT_REG(C_DATA_WIDTH-1 downto 0) <= RX_FIFO_D_O;
I2S_STATUS_REG(0) <= TX_FIFO_EMPTY_O;
I2S_STATUS_REG(1) <= TX_FIFO_FULL_O;
I2S_STATUS_REG(15 downto 2) <= (others => '0');
I2S_STATUS_REG(16) <= RX_FIFO_EMPTY_O;
I2S_STATUS_REG(17) <= RX_FIFO_FULL_O;
I2S_STATUS_REG(31 downto 18) <= (others => '0');
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (I2S_RESET_REG, I2S_TRANSFER_CONTROL_REG, I2S_FIFO_CONTROL_REG, I2S_DATA_IN_REG, I2S_DATA_OUT_REG, I2S_CLOCK_CONTROL_REG, I2S_STATUS_REG, I2S_PERIOD_COUNT_REG, I2S_STREAM_CONTROL_REG, slv_reg9, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if S_AXI_ARESETN = '0' then
reg_data_out <= (others => '1');
else
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"0000" =>
reg_data_out <= I2S_RESET_REG;
when b"0001" =>
reg_data_out <= I2S_TRANSFER_CONTROL_REG;
when b"0010" =>
reg_data_out <= I2S_FIFO_CONTROL_REG;
when b"0011" =>
reg_data_out <= I2S_DATA_IN_REG;
when b"0100" =>
reg_data_out <= I2S_DATA_OUT_REG;
when b"0101" =>
reg_data_out <= I2S_STATUS_REG;
when b"0110" =>
reg_data_out <= I2S_CLOCK_CONTROL_REG;
when b"0111" =>
reg_data_out <= I2S_PERIOD_COUNT_REG;
when b"1000" =>
reg_data_out <= I2S_STREAM_CONTROL_REG;
when b"1001" =>
reg_data_out <= slv_reg9;
when others =>
reg_data_out <= (others => '0');
end case;
end if;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
-- User logic ends
end arch_imp;

395
hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/fifo_32/fifo_32.xci
View File

@ -1,395 +0,0 @@
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">24</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">4kx9</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">3</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">4092</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">4096</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">12</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">12</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">4096</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">12</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
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395
hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/fifo_4/fifo_4.xci
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@ -1,395 +0,0 @@
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325
hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/i2s_ctl.vhd
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@ -1,325 +0,0 @@
-------------------------------------------------------------------------------
--
-- COPYRIGHT (C) 2012, Digilent RO. All rights reserved
--
-------------------------------------------------------------------------------
-- FILE NAME : i2s_ctl.vhd
-- MODULE NAME : I2S Control
-- AUTHOR : Mihaita Nagy
-- AUTHOR'S EMAIL : mihaita.nagy@digilent.ro
-------------------------------------------------------------------------------
-- REVISION HISTORY
-- VERSION DATE AUTHOR DESCRIPTION
-- 1.0 2012-25-01 Mihaita Nagy Created
-- 2.0 2012-02-04 Mihaita Nagy Remade the i2s_transmitter.vhd and
-- i2s_receiver.vhd into one new module.
-- 3.0 2014-12-02 HegbeliC Implemented edge detection for the
-- master mode and the division rate
-- for the different sampling rates
-------------------------------------------------------------------------------
-- KEYWORDS : I2S
-------------------------------------------------------------------------------
-- DESCRIPTION : This module implements the I2S transmitter and receiver
-- interface, with a 32-bit Stereo data transmission. Parameter
-- C_DATA_WIDTH sets the width of the data to be transmitted,
-- with a maximum value of 32 bits. If a smaller width size is
-- used (i.e. 24) than the remaining bits that needs to be
-- transmitted to complete the 32-bit length, are automaticaly
-- set to 0.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
------------------------------------------------------------------------
-- Module Declaration
------------------------------------------------------------------------
entity i2s_ctl is
generic (
-- Width of one Slot (24/20/18/16-bit wide)
C_DATA_WIDTH: integer := 24
);
port (
CLK_I : in std_logic; -- System clock (100 MHz)
RST_I : in std_logic; -- System reset
EN_TX_I : in std_logic; -- Transmit enable
EN_RX_I : in std_logic; -- Receive enable
FS_I : in std_logic_vector(3 downto 0); -- Sampling rate slector
MM_I : in std_logic; -- Audio controler Master Mode delcetor
D_L_I : in std_logic_vector(C_DATA_WIDTH-1 downto 0); -- Left channel data
D_R_I : in std_logic_vector(C_DATA_WIDTH-1 downto 0); -- Right channel data
OE_L_O : out std_logic; -- Left channel data output enable pulse
OE_R_O : out std_logic; -- Right channel data output enable pulse
WE_L_O : out std_logic; -- Left channel data write enable pulse
WE_R_O : out std_logic; -- Right channel data write enable pulse
D_L_O : out std_logic_vector(C_DATA_WIDTH-1 downto 0); -- Left channel data
D_R_O : out std_logic_vector(C_DATA_WIDTH-1 downto 0); -- Right channel data
BCLK_O : out std_logic; -- serial CLK
BCLK_I : in std_logic; -- serial CLK
BCLK_T : out std_logic; -- serial CLK
LRCLK_O : out std_logic; -- channel CLK
LRCLK_I : in std_logic; -- channel CLK
LRCLK_T : out std_logic; -- channel CLK
SDATA_O : out std_logic; -- Output serial data
SDATA_I : in std_logic -- Input serial data
);
end i2s_ctl;
architecture Behavioral of i2s_ctl is
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
-- Counter for the clock divider
signal Cnt_Bclk : integer range 0 to 31;
-- Counter for the L/R clock divider
signal Cnt_Lrclk : integer range 0 to 31;
-- Rising and Falling edge impulses of the serial clock
signal BCLK_Fall, BCLK_Rise : std_logic;
signal BCLK_Fall_int, BCLK_Rise_int : std_logic;
signal BCLK_Fall_shot, BCLK_Rise_shot : std_logic;
-- Synchronisation signals for Rising and Falling edge
signal Q1R, Q2R, Q3R : std_logic;
signal Q1F, Q2F, Q3F : std_logic;
-- Internal synchronous BCLK signal
signal BCLK_int : std_logic;
-- Internal synchronous LRCLK signal
signal LRCLK_int : std_logic;
signal LRCLK : std_logic;
--
signal Data_Out_int : std_logic_vector(31 downto 0);
--
signal Data_In_int : std_logic_vector(31 downto 0);
--
signal D_L_O_int : std_logic_vector(C_DATA_WIDTH-1 downto 0);
--
signal D_R_O_int : std_logic_vector(C_DATA_WIDTH-1 downto 0);
--Internal synchronous OE signals
signal OE_R_int, OE_L_int : std_logic;
--Internal synchronous WE signals
signal WE_R_int, WE_L_int : std_logic;
-- Division rate for the BCLK and LRCLK
signal DIV_RATE : natural := 4;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
------------------------------------------------------------------------
-- Sampling frequency and data width decoder (DIV_RATE, C_DATA_WIDTH)
------------------------------------------------------------------------
BIT_FS: process(CLK_I)
begin
if rising_edge(CLK_I) then
case (FS_I) is
when x"0" => DIV_RATE <= 24;
when x"1" => DIV_RATE <= 16;
when x"2" => DIV_RATE <= 12;
when x"3" => DIV_RATE <= 8;
when x"4" => DIV_RATE <= 6;
when x"5" => DIV_RATE <= 4;
when x"6" => DIV_RATE <= 2;
when others => DIV_RATE <= 4;
end case;
end if;
end process;
------------------------------------------------------------------------
-- Serial clock generator (BCLK_O, BCLK_Fall, BCLK_Rise)
------------------------------------------------------------------------
SER_CLK: process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
Cnt_Bclk <= 0;
BCLK_int <= '0';
elsif Cnt_Bclk = ((DIV_RATE/2)-1) then
Cnt_Bclk <= 0;
BCLK_int <= not BCLK_int;
else
Cnt_Bclk <= Cnt_Bclk + 1;
end if;
end if;
end process SER_CLK;
-- Rising and Falling edges when in Slave mode
BCLK_Fall_int <= '1' when Cnt_Bclk = ((DIV_RATE/2)-1) and BCLK_int = '1' and (EN_RX_I = '1' or EN_TX_I = '1') else '0';
BCLK_Rise_int <= '1' when Cnt_Bclk = ((DIV_RATE/2)-1) and BCLK_int = '0' and (EN_RX_I = '1' or EN_TX_I = '1') else '0';
-- Rising edge detection when in Master Mode (BCLK_I active)
OneShotRise: process(CLK_I)
begin
if rising_edge(CLK_I) then
Q1R<=BCLK_I;
Q2R<=Q1R;
Q3R<=Q2R;
end if;
end process;
BCLK_Rise_shot <= BCLK_I and (not Q3R);
-- Falling edge detection when in Master Mode (BCLK_I active)
OneShotFall: process(CLK_I)
begin
if rising_edge(CLK_I) then
Q1F<=not BCLK_I;
Q2F<=Q1F;
Q3F<=Q2F;
end if;
end process;
BCLK_Fall_shot <= not BCLK_I and (not Q3F);
-- Falling edge selection with respect to Master Mode bit
BCLK_Fall <= BCLK_Fall_int when MM_I = '0' else
BCLK_Fall_shot;
-- Risesing edge selection with respect to Master Mode bit
BCLK_Rise <= BCLK_Rise_int when MM_I = '0' else
BCLK_Rise_shot;
-- Serial clock output
BCLK_O <= BCLK_int when EN_RX_I = '1' or EN_TX_I = '1' else '1';
BCLK_T <= MM_I;
------------------------------------------------------------------------
-- Left/Right clock generator (LRCLK_O, LRCLK_Pls)
------------------------------------------------------------------------
LRCLK_GEN: process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
Cnt_Lrclk <= 0;
LRCLK <= '0'; -- Left channel active by default
elsif BCLK_Fall = '1' then
if Cnt_Lrclk = 31 then -- half of frame (64 bits)
Cnt_Lrclk <= 0;
LRCLK <= not LRCLK;
else
Cnt_Lrclk <= Cnt_Lrclk + 1;
end if;
end if;
end if;
end process LRCLK_GEN;
-- L/R clock output
LRCLK_O <= LRCLK when EN_TX_I = '1' or EN_RX_I = '1' else '0';
LRCLK_int <= LRCLK when MM_I = '0' else LRCLK_I;
LRCLK_T <= MM_I;
------------------------------------------------------------------------
-- Load in paralled data, shift out serial data (SDATA_O)
------------------------------------------------------------------------
SER_DATA_O: process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
Data_Out_int(31) <= '0';
Data_Out_int(30 downto 31-C_DATA_WIDTH) <= D_L_I; -- Left channel data by default
Data_Out_int(30-C_DATA_WIDTH downto 0) <= (others => '0');
elsif Cnt_Lrclk = 0 and BCLK_Rise = '1' then -- load par. data
if LRCLK_int = '1' then
Data_Out_int(31) <= '0';
Data_Out_int(30 downto 31-C_DATA_WIDTH) <= D_R_I;
Data_Out_int(30-C_DATA_WIDTH downto 0) <= (others => '0');
else
Data_Out_int(31) <= '0';
Data_Out_int(30 downto 31-C_DATA_WIDTH) <= D_L_I;
Data_Out_int(30-C_DATA_WIDTH downto 0) <= (others => '0');
end if;
elsif BCLK_Fall = '1' then -- shift out ser. data
Data_Out_int <= Data_Out_int(30 downto 0) & '0';
end if;
end if;
end process SER_DATA_O;
-- Serial data output
SDATA_O <= Data_Out_int(31) when EN_TX_I = '1' else '0';
------------------------------------------------------------------------
-- Shift in serial data, load out parallel data (SDATA_I)
------------------------------------------------------------------------
SER_DATA_I: process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
Data_In_int <= (others => '0');
D_L_O_int <= (others => '0');
D_R_O_int <= (others => '0');
elsif Cnt_Lrclk = 0 and BCLK_Fall = '1' then -- load par. data
if LRCLK_int = '1' then
D_L_O_int <= Data_In_int(31 downto 32-C_DATA_WIDTH);
Data_In_int <= (others => '0');
else
D_R_O_int <= Data_In_int(31 downto 32-C_DATA_WIDTH);
Data_In_int <= (others => '0');
end if;
elsif BCLK_Rise = '1' then -- shift in ser. data
Data_In_int <= Data_In_int(30 downto 0) & SDATA_I;
end if;
end if;
end process SER_DATA_I;
D_L_O <= D_L_O_int;
D_R_O <= D_R_O_int;
------------------------------------------------------------------------
-- Output Enable signals (for FIFO)
------------------------------------------------------------------------
OE_GEN: process(CLK_I)
begin
if rising_edge(CLK_I) then
if Cnt_Lrclk = 31 and BCLK_Fall = '1' then
if LRCLK_int = '1' then -- Right channel
OE_R_int <= '1';
else -- Left channel
OE_L_int <= '1';
end if;
else
OE_R_int <= '0';
OE_L_int <= '0';
end if;
end if;
end process OE_GEN;
OE_R_O <= OE_R_int when EN_TX_I = '1' else '0';
OE_L_O <= OE_L_int when EN_TX_I = '1' else '0';
------------------------------------------------------------------------
-- Write Enable signals (for FIFO)
------------------------------------------------------------------------
WE_GEN: process(CLK_I)
begin
if rising_edge(CLK_I) then
if Cnt_Lrclk = 1 and BCLK_Rise = '1' then
if LRCLK_int = '1' then -- Right channel
WE_R_int <= '1';
else -- Left channel
WE_L_int <= '1';
end if;
else
WE_R_int <= '0';
WE_L_int <= '0';
end if;
end if;
end process WE_GEN;
WE_R_O <= WE_R_int when EN_RX_I = '1' else '0';
WE_L_O <= WE_L_int when EN_RX_I = '1' else '0';
end Behavioral;

436
hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/i2s_rx_tx.vhd
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@ -1,436 +0,0 @@
-------------------------------------------------------------------------------
--
-- COPYRIGHT (C) 2012, Digilent RO. All rights reserved
--
-------------------------------------------------------------------------------
-- FILE NAME : i2s_rx_tx.vhd
-- MODULE NAME : I2S Tranceiver
-- AUTHOR : Mihaita Nagy
-- AUTHOR'S EMAIL : mihaita.nagy@digilent.ro
-------------------------------------------------------------------------------
-- REVISION HISTORY
-- VERSION DATE AUTHOR DESCRIPTION
-- 1.0 2012-25-01 MihaitaN Created
-- 2.0 ? MihaitaN ?
-- 3.0 2014-12-02 HegbeliC Integration of the MCLK and Master Mode
-------------------------------------------------------------------------------
-- KEYWORDS : I2S
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.VComponents.all;
------------------------------------------------------------------------
-- Module Declaration
------------------------------------------------------------------------
entity i2s_rx_tx is
generic (
-- Width of left/right channel data buses
C_DATA_WIDTH : integer := 24
);
port (
-- Global signals
CLK_I : in std_logic;
RST_I : in std_logic;
-- Control signals
TX_RS_I : in std_logic;
RX_RS_I : in std_logic;
-- CLK input for MCLK rendering
CLK_100MHZ_I : in std_logic;
-- Control signal for setting the sampeling rate
SAMPLING_RATE_I : in std_logic_vector (3 downto 0);
-- Flag for when the Controller is in master mode
CTL_MASTER_MODE_I : in std_logic;
-- DBG
DBG_TX_FIFO_RST_I : out std_logic;
DBG_TX_FIFO_WR_EN_I : out std_logic;
DBG_TX_FIFO_RD_EN_I : out std_logic;
DBG_TX_FIFO_EMPTY_O : out std_logic;
DBG_TX_FIFO_FULL_O : out std_logic;
DBG_TX_FIFO_D_I : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
DBG_TX_FIFO_D_O : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
DBG_TX_RS_I : out std_logic;
DBG_RX_FIFO_RST_I : out std_logic;
DBG_RX_FIFO_WR_EN_I : out std_logic;
DBG_RX_FIFO_RD_EN_I : out std_logic;
DBG_RX_FIFO_FULL_O : out std_logic;
DBG_RX_FIFO_EMPTY_O : out std_logic;
DBG_RX_FIFO_D_O : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
DBG_RX_FIFO_D_I : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
DBG_RX_RS_I : out std_logic;
-- Tx FIFO Control signals
TX_FIFO_RST_I : in std_logic;
TX_FIFO_D_I : in std_logic_vector(C_DATA_WIDTH-1 downto 0);
TX_FIFO_WR_EN_I : in std_logic;
-- Rx FIFO Control signals
RX_FIFO_RST_I : in std_logic;
RX_FIFO_RD_EN_I : in std_logic;
RX_FIFO_D_O : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
-- Tx FIFO Flags
TX_FIFO_EMPTY_O : out std_logic;
TX_FIFO_FULL_O : out std_logic;
-- Rx FIFO Flags
RX_FIFO_EMPTY_O : out std_logic;
RX_FIFO_FULL_O : out std_logic;
-- I2S interface signals
BCLK_O : out std_logic;
BCLK_I : in std_logic;
BCLK_T : out std_logic;
LRCLK_O : out std_logic;
LRCLK_I : in std_logic;
LRCLK_T : out std_logic;
MCLK_O : out std_logic;
SDATA_I : in std_logic;
SDATA_O : out std_logic
);
end i2s_rx_tx;
architecture Behavioral of i2s_rx_tx is
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
signal StartTransaction : std_logic;
signal StopTransaction : std_logic;
signal RxEn : std_logic;
signal TxEn : std_logic;
signal LRCLK_Int : std_logic;
signal LR : std_logic;
signal Rnw : std_logic;
signal RxFifoDataIn : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal RxFifoDataInL : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal RxFifoDataInR : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal RxFifoWrEn : std_logic;
signal RxFifoWrEnL : std_logic;
signal RxFifoWrEnR : std_logic;
signal TxFifoDataOut : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal TxFifoRdEn : std_logic;
signal TxFifoRdEnL : std_logic;
signal TxFifoRdEnR : std_logic;
signal TxFifoEmpty : std_logic;
signal RxFifoFull : std_logic;
signal SamplingFrequncy : std_logic_vector(3 downto 0);
signal Rst_Int : std_logic;
signal Rst_Int_sync : std_logic;
signal MM_Int : std_logic;
signal Rst_interior : std_logic;
-- DCM signals
signal RstDcm : std_logic;
signal LockDcm : std_logic;
signal CLK_12 : std_logic;
signal TxFifoReset : std_logic;
signal RxFifoReset : std_logic;
signal TX_FIFO_FULL_int : std_logic;
signal RX_FIFO_EMPTY_int : std_logic;
signal RX_FIFO_D_int : std_logic_vector(C_DATA_WIDTH-1 downto 0);
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
component i2s_ctl
generic (
C_DATA_WIDTH: integer := 24);
port (
CLK_I : in std_logic;
RST_I : in std_logic;
EN_TX_I : in std_logic;
EN_RX_I : in std_logic;
OE_L_O : out std_logic;
OE_R_O : out std_logic;
WE_L_O : out std_logic;
WE_R_O : out std_logic;
D_L_I : in std_logic_vector(C_DATA_WIDTH-1 downto 0);
D_R_I : in std_logic_vector(C_DATA_WIDTH-1 downto 0);
D_L_O : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
D_R_O : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
MM_I : in std_logic;
FS_I : in std_logic_vector(3 downto 0);
BCLK_O : out std_logic;
BCLK_I : in std_logic;
BCLK_T : out std_logic;
LRCLK_O : out std_logic;
LRCLK_I : in std_logic;
LRCLK_T : out std_logic;
SDATA_O : out std_logic;
SDATA_I : in std_logic);
end component;
-- the FIFO used for sample rate bus
component fifo_4
port (
rst : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(3 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(3 downto 0);
full : out std_logic;
empty : out std_logic
);
end component;
-- the FIFO, used for Rx and Tx
component fifo_32
port (
wr_clk : in std_logic;
rd_clk : in std_logic;
rst : in std_logic;
din : in std_logic_vector(23 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(23 downto 0);
full : out std_logic;
empty : out std_logic);
end component;
-- the DCM for generating 12.288 MHz
component DCM
port(
CLK_100 : in std_logic;
CLK_12_288 : out std_logic;
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
-- the synchronisation unite for the two CLK domains
component Sync_ff
port(
CLK : in std_logic;
D_I : in std_logic;
Q_O : out std_logic
);
end component;
component rst_sync
Port (
RST_I : in STD_LOGIC;
CLK : in STD_LOGIC;
Q_O : out STD_LOGIC
);
end component;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
------------------------------------------------------------------------
-- Instantiate the I2S transmitter module
------------------------------------------------------------------------
Inst_I2sRxTx: i2s_ctl
generic map(
C_DATA_WIDTH => C_DATA_WIDTH)
port map(
CLK_I => CLK_12,
RST_I => Rst_Int_sync,
EN_TX_I => TxEn,
EN_RX_I => RxEn,
OE_L_O => TxFifoRdEnL,
OE_R_O => TxFifoRdEnR,
WE_L_O => RxFifoWrEnL,
WE_R_O => RxFifoWrEnR,
D_L_I => TxFifoDataOut,
D_R_I => TxFifoDataOut,
D_L_O => RxFifoDataInL,
D_R_O => RxFifoDataInR,
MM_I => MM_Int,
FS_I => SamplingFrequncy,
BCLK_O => BCLK_O,
BCLK_I => BCLK_I,
BCLK_T => BCLK_T,
LRCLK_O => LRCLK_Int,
LRCLK_I => LRCLK_I,
LRCLK_T => LRCLK_T,
SDATA_O => SDATA_O,
SDATA_I => SDATA_I);
TxFifoRdEn <= TxFifoRdEnL or TxFifoRdEnR;
RxFifoWrEn <= RxFifoWrEnL or RxFifoWrEnR;
LRCLK_O <= LRCLK_Int;
------------------------------------------------------------------------
-- Instantiate the transmitter fifo
------------------------------------------------------------------------
Inst_Sampling: fifo_4
port map (
rst => RST_I,
wr_clk => CLK_I,
rd_clk => CLK_12,
din => SAMPLING_RATE_I,
wr_en => '1',
rd_en => '1',
dout => SamplingFrequncy,
full => open,
empty => open);
------------------------------------------------------------------------
-- Instantiate the transmitter fifo
------------------------------------------------------------------------
Inst_I2sTxFifo: fifo_32
port map(
wr_clk => CLK_I,
rd_clk => CLK_12,
rst => TxFifoReset,
din => TX_FIFO_D_I,
wr_en => TX_FIFO_WR_EN_I,
rd_en => TxFifoRdEn,
dout => TxFifoDataOut,
full => TX_FIFO_FULL_int,
empty => TxFifoEmpty);
DBG_TX_FIFO_RST_I <= TxFifoReset;
DBG_TX_FIFO_RD_EN_I <= TxFifoRdEn;
DBG_TX_FIFO_WR_EN_I <= TX_FIFO_WR_EN_I;
DBG_TX_FIFO_FULL_O <= TX_FIFO_FULL_int;
DBG_TX_FIFO_EMPTY_O <= TxFifoEmpty;
DBG_TX_FIFO_D_I <= TX_FIFO_D_I;
DBG_TX_FIFO_D_O <= TxFifoDataOut;
DBG_TX_RS_I <= TxEn;
-- TX_FIFO_EMPTY_O <= TxFifoEmpty;
TX_FIFO_FULL_O <= TX_FIFO_FULL_int;
------------------------------------------------------------------------
-- Instantiate the receiver fifo
------------------------------------------------------------------------
Inst_I2sRxFifo: fifo_32
port map(
wr_clk => CLK_12,
rd_clk => CLK_I,
rst => RX_FIFO_RST_I,
din => RxFifoDataIn,
wr_en => RxFifoWrEn,
rd_en => RX_FIFO_RD_EN_I,
dout => RX_FIFO_D_int,
full => RxFifoFull,
empty => RX_FIFO_EMPTY_int);
DBG_RX_FIFO_RST_I <= RX_FIFO_RST_I;
DBG_RX_FIFO_WR_EN_I <= RxFifoWrEn;
DBG_RX_FIFO_RD_EN_I <= RX_FIFO_RD_EN_I;
DBG_RX_FIFO_EMPTY_O <=RX_FIFO_EMPTY_int;
DBG_RX_FIFO_D_O <= RX_FIFO_D_int;
DBG_RX_FIFO_D_I <= RxFifoDataIn;
DBG_RX_RS_I <= RxEn;
RX_FIFO_EMPTY_O <= RX_FIFO_EMPTY_int;
-- RX_FIFO_FULL_O <= RxFifoFull;
RX_FIFO_D_O <= RX_FIFO_D_int;
-- input selct between audio controler in master or in slave
LR <= LRCLK_Int when MM_Int = '0' else LRCLK_I;
RxFifoDataIn <= RxFifoDataInR when LR = '1' else RxFifoDataInL;
------------------------------------------------------------------------
-- Instantiate DCM
------------------------------------------------------------------------
Inst_Dcm : DCM
port map(
CLK_100 => CLK_100MHZ_I,
CLK_12_288 => CLK_12,
RESET => Rst_Int,
LOCKED => LockDcm);
Rst_Int <= RST_I and not LockDcm;
------------------------------------------------------------------------
-- Instantiate BusSync for the sample rate read out (100 -> 12)
------------------------------------------------------------------------
Inst_SyncBit_RX_RS: Sync_ff
port map(
CLK => CLK_12,
D_I => RX_RS_I,
Q_O => RxEn);
------------------------------------------------------------------------
-- Instantiate BusSync for the sample rate read out (100 -> 12)
------------------------------------------------------------------------
Inst_SyncBit_TX_RS: Sync_ff
port map(
CLK => CLK_12,
D_I => TX_RS_I,
Q_O => TxEn);
------------------------------------------------------------------------
-- Instantiate BusSync for the sample rate read out (100 -> 12)
------------------------------------------------------------------------
Inst_SyncBit_CTL_MM: Sync_ff
port map(
CLK => CLK_12,
D_I => CTL_MASTER_MODE_I,
Q_O => MM_Int);
------------------------------------------------------------------------
-- Instantiate BusSync for the sample rate read out (100 -> 12)
------------------------------------------------------------------------
Inst_Rst_Sync_TX_RST: rst_sync
port map(
CLK => CLK_12,
RST_I => TX_FIFO_RST_I,
Q_O => TxFifoReset);
------------------------------------------------------------------------
-- Instantiate BusSync for the sample rate read out (100 -> 12)
------------------------------------------------------------------------
Inst_Rst_Sync_RST: rst_sync
port map(
CLK => CLK_12,
RST_I => Rst_Int,
Q_O => Rst_Int_sync);
------------------------------------------------------------------------
-- Instantiate BusSync for the sample rate read out (100 -> 12)
------------------------------------------------------------------------
Inst_SyncBit_Tx_Empty: Sync_ff
port map(
CLK => CLK_I,
D_I => TxFifoEmpty,
Q_O => TX_FIFO_EMPTY_O);
------------------------------------------------------------------------
-- Instantiate BusSync for the sample rate read out (100 -> 12)
------------------------------------------------------------------------
Inst_SyncBit_Rx_Full: Sync_ff
port map(
CLK => CLK_I,
D_I => RxFifoFull,
Q_O => RX_FIFO_FULL_O);
------------------------------------------------------------------------
-- Instantiaton of the ODDR for the Output MCLK
------------------------------------------------------------------------
ODDR_inst : ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port ('1' or '0')
SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
port map (
Q => MCLK_O, -- 1-bit DDR output
C => CLK_12, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D1 => '1', -- 1-bit data input (positive edge)
D2 => '0', -- 1-bit data input (negative edge)
R => '0', -- 1-bit reset input
S => '0'); -- 1-bit set input
end Behavioral;

158
hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/i2s_stream.vhd
View File

@ -1,158 +0,0 @@
-------------------------------------------------------------------------------
--
-- COPYRIGHT (C) 2014, Digilent RO. All rights reserved
--
-------------------------------------------------------------------------------
-- FILE NAME : i2s_stream.vhd
-- MODULE NAME : I2S Stream
-- AUTHOR : Hegbeli Ciprian
-- AUTHOR'S EMAIL : ciprian.hegbeli@digilent.com
-------------------------------------------------------------------------------
-- REVISION HISTORY
-- VERSION DATE AUTHOR DESCRIPTION
-- 1.0 2014-28-03 Hegbeli Ciprian Created
-------------------------------------------------------------------------------
-- KEYWORDS : Stream
-------------------------------------------------------------------------------
-- DESCRIPTION : This module implements the Stream protocol for sending the
-- incomming I2S data to the DMA. It implements both the S2MM
-- and the MM2S allowing for a full duplex comunication
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;
------------------------------------------------------------------------
-- Module Declaration
------------------------------------------------------------------------
entity i2s_stream is
generic (
-- Stream data width (must be multiple of 8)
C_AXI_STREAM_DATA_WIDTH : integer := 32;
-- Width of one Slot (24/20/18/16-bit wide)
C_DATA_WIDTH : integer := 24
);
port (
-- Tx FIFO Flags
TX_FIFO_FULL_I : in std_logic;
-- Rx FIFO Flags
RX_FIFO_EMPTY_I : in std_logic;
-- Tx FIFO Control signals
TX_FIFO_D_O : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
-- Rx FIFO Control signals
RX_FIFO_D_I : in std_logic_vector(C_DATA_WIDTH-1 downto 0);
NR_OF_SMPL_I : in std_logic_vector(20 downto 0);
TX_STREAM_EN_I : in std_logic;
RX_STREAM_EN_I : in std_logic;
-- AXI4-Stream
-- Slave
S_AXIS_MM2S_ACLK_I : in std_logic;
S_AXIS_MM2S_ARESETN : in std_logic;
S_AXIS_MM2S_TREADY_O : out std_logic;
S_AXIS_MM2S_TDATA_I : in std_logic_vector(C_AXI_STREAM_DATA_WIDTH-1 downto 0);
S_AXIS_MM2S_TLAST_I : in std_logic;
S_AXIS_MM2S_TVALID_I : in std_logic;
-- Master
M_AXIS_S2MM_ACLK_I : in std_logic;
M_AXIS_S2MM_ARESETN : in std_logic;
M_AXIS_S2MM_TDATA_O : out std_logic_vector(C_AXI_STREAM_DATA_WIDTH-1 downto 0);
M_AXIS_S2MM_TLAST_O : out std_logic;
M_AXIS_S2MM_TVALID_O : out std_logic;
M_AXIS_S2MM_TREADY_I : in std_logic;
M_AXIS_S2MM_TKEEP_O : out std_logic_vector((C_AXI_STREAM_DATA_WIDTH/8)-1 downto 0)
);
end i2s_stream;
architecture Behavioral of i2s_stream is
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
signal nr_of_rd, nr_of_wr : std_logic_vector (20 downto 0);
signal tlast : std_logic;
signal ready : std_logic;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
------------------------------------------------------------------------
-- MM2S protocol imnplementation
------------------------------------------------------------------------
S_Control: process (S_AXIS_MM2S_ACLK_I)
begin
if (S_AXIS_MM2S_ACLK_I'event and S_AXIS_MM2S_ACLK_I = '0') then
if (S_AXIS_MM2S_ARESETN = '0') then
nr_of_rd <= NR_OF_SMPL_I;
elsif (RX_STREAM_EN_I = '1') then
if (nr_of_rd > 0) then
if (S_AXIS_MM2S_TVALID_I = '1' and ready = '1') then
TX_FIFO_D_O <= S_AXIS_MM2S_TDATA_I(C_DATA_WIDTH-1 downto 0);
nr_of_rd <= nr_of_rd-1;
end if;
end if;
else
nr_of_rd <= NR_OF_SMPL_I;
end if;
end if;
end process;
-- ready signal decalaration
ready <= not TX_FIFO_FULL_I when RX_STREAM_EN_I = '1' else
'0';
S_AXIS_MM2S_TREADY_O <= ready;
------------------------------------------------------------------------
-- S2MM protocol implementation
------------------------------------------------------------------------
M_Control: process (M_AXIS_S2MM_ACLK_I)
begin
if (M_AXIS_S2MM_ACLK_I'event and M_AXIS_S2MM_ACLK_I = '1') then
if (M_AXIS_S2MM_ARESETN = '0') THEN
tlast <= '0';
nr_of_wr <= NR_OF_SMPL_I;
elsif (TX_STREAM_EN_I = '1') then
if (nr_of_wr > 0) then
if (M_AXIS_S2MM_TREADY_I = '1' and RX_FIFO_EMPTY_I = '0') then
nr_of_wr <= nr_of_wr-1;
end if;
end if;
if (nr_of_wr = 0) then
tlast <= '0';
end if;
if (nr_of_wr = 1) then
tlast <= '1';
end if;
else
tlast <= '0';
nr_of_wr <= NR_OF_SMPL_I;
end if;
end if;
end process;
-- S2MM Data signals
M_AXIS_S2MM_TDATA_O(C_AXI_STREAM_DATA_WIDTH-1 downto C_DATA_WIDTH) <= (others => '0');
M_AXIS_S2MM_TDATA_O(C_DATA_WIDTH-1 downto 0) <= RX_FIFO_D_I;
-- S2MM valid signal only active when strea is enabled and not EOL
M_AXIS_S2MM_TVALID_O <= not RX_FIFO_EMPTY_I when (nr_of_wr > 0 and TX_STREAM_EN_I = '1') else
'0';
M_AXIS_S2MM_TLAST_O <= tlast;
-- Kepp all incomming samples
M_AXIS_S2MM_TKEEP_O <= (others => '1');
end Behavioral;

73
hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/src/rst_sync.vhd
View File

@ -1,73 +0,0 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/29/2014 12:36:46 PM
-- Design Name:
-- Module Name: rst_sync - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rst_sync is
Port ( RST_I : in STD_LOGIC;
CLK : in STD_LOGIC;
Q_O : out STD_LOGIC);
end rst_sync;
architecture Behavioral of rst_sync is
signal d_int: std_logic;
signal q_int: std_logic;
begin
FDRE_inst_1 : FDPE
generic map (
INIT => '0') -- Initial value of register ('0' or '1')
port map (
Q => d_int, -- Data output
C => CLK, -- Clock input
CE => '1', -- Clock enable input
PRE => RST_I, -- Synchronous reset input
D => '0' -- Data input
);
FDRE_inst_2 : FDPE
generic map (
INIT => '0') -- Initial value of register ('0' or '1')
port map (
Q => q_int, -- Data output
C => CLK, -- Clock input
CE => '1', -- Clock enable input
PRE => RST_I, -- Synchronous reset input
D => d_int -- Data input
);
Q_O <= q_int;
end Behavioral;

109
hdmi-out-test/hdmi-out-test.ipdefs/repo_0/local/ip/d_axi_i2s_audio_v2_0/xgui/d_axi_i2s_audio_v2_0.tcl
View File

@ -1,109 +0,0 @@
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
set_property tooltip {Page 0} ${Page_0}
ipgui::add_param $IPINST -name "C_DATA_WIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI_STREAM_DATA_WIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI_L_DATA_WIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI_L_ADDR_WIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "ENABLE_STREAM" -parent ${Page_0}
ipgui::add_param $IPINST -name "BIDIRECTIONAL_CLK" -parent ${Page_0}
}
proc update_PARAM_VALUE.BIDIRECTIONAL_CLK { PARAM_VALUE.BIDIRECTIONAL_CLK } {
# Procedure called to update BIDIRECTIONAL_CLK when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.BIDIRECTIONAL_CLK { PARAM_VALUE.BIDIRECTIONAL_CLK } {
# Procedure called to validate BIDIRECTIONAL_CLK
return true
}
proc update_PARAM_VALUE.C_AXI_L_ADDR_WIDTH { PARAM_VALUE.C_AXI_L_ADDR_WIDTH } {
# Procedure called to update C_AXI_L_ADDR_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI_L_ADDR_WIDTH { PARAM_VALUE.C_AXI_L_ADDR_WIDTH } {
# Procedure called to validate C_AXI_L_ADDR_WIDTH
return true
}
proc update_PARAM_VALUE.C_AXI_L_DATA_WIDTH { PARAM_VALUE.C_AXI_L_DATA_WIDTH } {
# Procedure called to update C_AXI_L_DATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI_L_DATA_WIDTH { PARAM_VALUE.C_AXI_L_DATA_WIDTH } {
# Procedure called to validate C_AXI_L_DATA_WIDTH
return true
}
proc update_PARAM_VALUE.C_AXI_STREAM_DATA_WIDTH { PARAM_VALUE.C_AXI_STREAM_DATA_WIDTH } {
# Procedure called to update C_AXI_STREAM_DATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI_STREAM_DATA_WIDTH { PARAM_VALUE.C_AXI_STREAM_DATA_WIDTH } {
# Procedure called to validate C_AXI_STREAM_DATA_WIDTH
return true
}
proc update_PARAM_VALUE.C_DATA_WIDTH { PARAM_VALUE.C_DATA_WIDTH } {
# Procedure called to update C_DATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_DATA_WIDTH { PARAM_VALUE.C_DATA_WIDTH } {
# Procedure called to validate C_DATA_WIDTH
return true
}
proc update_PARAM_VALUE.ENABLE_STREAM { PARAM_VALUE.ENABLE_STREAM } {
# Procedure called to update ENABLE_STREAM when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.ENABLE_STREAM { PARAM_VALUE.ENABLE_STREAM } {
# Procedure called to validate ENABLE_STREAM
return true
}
proc update_PARAM_VALUE.C_AXI_L_BASEADDR { PARAM_VALUE.C_AXI_L_BASEADDR } {
# Procedure called to update C_AXI_L_BASEADDR when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI_L_BASEADDR { PARAM_VALUE.C_AXI_L_BASEADDR } {
# Procedure called to validate C_AXI_L_BASEADDR
return true
}
proc update_PARAM_VALUE.C_AXI_L_HIGHADDR { PARAM_VALUE.C_AXI_L_HIGHADDR } {
# Procedure called to update C_AXI_L_HIGHADDR when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI_L_HIGHADDR { PARAM_VALUE.C_AXI_L_HIGHADDR } {
# Procedure called to validate C_AXI_L_HIGHADDR
return true
}
proc update_MODELPARAM_VALUE.C_DATA_WIDTH { MODELPARAM_VALUE.C_DATA_WIDTH PARAM_VALUE.C_DATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_DATA_WIDTH}] ${MODELPARAM_VALUE.C_DATA_WIDTH}
}
proc update_MODELPARAM_VALUE.C_AXI_STREAM_DATA_WIDTH { MODELPARAM_VALUE.C_AXI_STREAM_DATA_WIDTH PARAM_VALUE.C_AXI_STREAM_DATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI_STREAM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_AXI_STREAM_DATA_WIDTH}
}
proc update_MODELPARAM_VALUE.C_AXI_L_DATA_WIDTH { MODELPARAM_VALUE.C_AXI_L_DATA_WIDTH PARAM_VALUE.C_AXI_L_DATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI_L_DATA_WIDTH}] ${MODELPARAM_VALUE.C_AXI_L_DATA_WIDTH}
}
proc update_MODELPARAM_VALUE.C_AXI_L_ADDR_WIDTH { MODELPARAM_VALUE.C_AXI_L_ADDR_WIDTH PARAM_VALUE.C_AXI_L_ADDR_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI_L_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_AXI_L_ADDR_WIDTH}
}

BIN
hdmi-out-test/hdmi-out-test.runs/impl_1/design_1_wrapper.bit → hdmi-out-test/hdmi-out-test.runs/impl_1/dvi_top.bit
View File

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2020
hdmi-out-test/hdmi-out-test.srcs/sources_1/bd/design_1/design_1.bd → hdmi-out-test/hdmi-out-test.srcs/sources_1/bd/blinki_bd/blinki_bd.bd
View File

File diff suppressed because it is too large Load Diff

BIN
hdmi-out-test/hdmi-out-test.vitis/hdmi-out-test.files/Debug/hdmiout-test1.elf
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BIN
hdmi-out-test/hdmi-out-test.vitis/hdmi-out-test.files/Debug/test0.elf 100755
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20
hdmi-out-test/hdmi-out-test.vitis/hdmi-out-test.files/src/main.c → hdmi-out-test/hdmi-out-test.vitis/hdmi-out-test.files/src/helloworld.c
View File

@ -1,20 +1,20 @@
#include <stdio.h> #include <stdio.h>
//#include "platform.h"
#include "xil_printf.h" #include "xil_printf.h"
#include "xv_tpg.h" //#include "xv_tpg.h"
#include "xvtc.h" //#include "xvtc.h"
int main() int main()
{ {
//init_platform(); //init_platform();
int Status; int Status;
XV_tpg tpg_inst; // Instance of the TPG core //XV_tpg tpg_inst; // Instance of the TPG core
XVtc VtcInst; // Instance of the VTC core //XVtc VtcInst; // Instance of the VTC core
print("--- hdmi-out-test ---\n\r"); print("--- hdmi-in-test ---\n\r");
//--( TPG Initialization //--( TPG Initialization
/*
print("TPG Initialization\n\r"); print("TPG Initialization\n\r");
Status = XV_tpg_Initialize(&tpg_inst, XPAR_XV_TPG_0_DEVICE_ID); Status = XV_tpg_Initialize(&tpg_inst, XPAR_XV_TPG_0_DEVICE_ID);
if(Status!= XST_SUCCESS) if(Status!= XST_SUCCESS)
@ -37,9 +37,11 @@ int main()
XV_tpg_EnableAutoRestart(&tpg_inst); XV_tpg_EnableAutoRestart(&tpg_inst);
XV_tpg_Start(&tpg_inst); XV_tpg_Start(&tpg_inst);
xil_printf("TPG started!\r\n"); xil_printf("TPG started!\r\n");
*/
//--) //--)
//--( VTC Initialization //--( VTC Initialization
/*
print("VTC Initialization\n\r"); print("VTC Initialization\n\r");
XVtc_Config *Config; XVtc_Config *Config;
XVtc_Timing ti; XVtc_Timing ti;
@ -74,8 +76,14 @@ int main()
//Enable the vtc //Enable the vtc
XVtc_Enable(&VtcInst); XVtc_Enable(&VtcInst);
xil_printf("VTC enabled!\r\n"); xil_printf("VTC enabled!\r\n");
*/
//--) //--)
xil_printf("\r\nInstructions:\r\n");
xil_printf("1. connect HDMI_OUT to HDMI_IN\r\n");
xil_printf("2. Check LD1,LD0 are on\r\n");
xil_printf("3. open ila_1 on vivado (connected to hdmi input after tmds2rgb conversion\r\n");
xil_printf("4. trigger it and compare results with logs/hdmi-loop-test-ila.png \r\n");
while(1){ while(1){
} }

201
hdmi-out-test/hdmi-out-test.xpr
View File

@ -6,7 +6,7 @@
<Project Version="7" Minor="56" Path="/home/neyko/DEV/git/PYNQ-Z2_demos/hdmi-out-test/hdmi-out-test.xpr"> <Project Version="7" Minor="56" Path="/home/neyko/DEV/git/PYNQ-Z2_demos/hdmi-out-test/hdmi-out-test.xpr">
<DefaultLaunch Dir="$PRUNDIR"/> <DefaultLaunch Dir="$PRUNDIR"/>
<Configuration> <Configuration>
<Option Name="Id" Val="5c156bcd3bc547d9bbfae9bc18edebc6"/> <Option Name="Id" Val="d6151e6a6d144952893a332e45aaf36e"/>
<Option Name="Part" Val="xc7z020clg400-1"/> <Option Name="Part" Val="xc7z020clg400-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/> <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/> <Option Name="CompiledLibDirXSim" Val=""/>
@ -46,8 +46,8 @@
<Option Name="ActiveSimSet" Val="sim_1"/> <Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/> <Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/> <Option Name="ProjectType" Val="Default"/>
<Option Name="IPRepoPath" Val="$PPRDIR/hdmi-out-test.ipdefs"/>
<Option Name="IPRepoPath" Val="$PPRDIR/digilent.ipdefs"/> <Option Name="IPRepoPath" Val="$PPRDIR/digilent.ipdefs"/>
<Option Name="IPRepoPath" Val="$PPRDIR/hdmi-out-test.ipdefs"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/> <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/> <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
<Option Name="IPCachePermission" Val="read"/> <Option Name="IPCachePermission" Val="read"/>
@ -58,7 +58,7 @@
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/> <Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="pynq-z2"/> <Option Name="DSABoardId" Val="pynq-z2"/>
<Option Name="WTXSimLaunchSim" Val="0"/> <Option Name="WTXSimLaunchSim" Val="58"/>
<Option Name="WTModelSimLaunchSim" Val="0"/> <Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/> <Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/> <Option Name="WTIesLaunchSim" Val="0"/>
@ -88,25 +88,85 @@
<FileSets Version="1" Minor="31"> <FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1"> <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/> <Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/bd/design_1/design_1.bd"> <File Path="$PSRCDIR/sources_1/bd/blinki_bd/blinki_bd.bd">
<FileInfo> <FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../ARM_DMA_audio/Zedboard-DMA/Zedboard-DMA.srcs/sources_1/bd/design_1/design_1.bd"/> <Attr Name="ImportPath" Val="$PPRDIR/../hdmi-thru/hdmi-thru.srcs/sources_1/bd/blinki_bd/blinki_bd.bd"/>
<Attr Name="ImportTime" Val="1712656797"/> <Attr Name="ImportTime" Val="1723725422"/>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/> <Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xci"> <CompFileExtendedInfo CompFileName="blinki_bd.bd" FileRelPathName="ip/blinki_bd_axi_gpio_0_0/blinki_bd_axi_gpio_0_0.xci">
<Proxy FileSetName="design_1_processing_system7_0_0"/> <Proxy FileSetName="blinki_bd_axi_gpio_0_0"/>
</CompFileExtendedInfo> </CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_v_tc_0_0/design_1_v_tc_0_0.xci"> <CompFileExtendedInfo CompFileName="blinki_bd.bd" FileRelPathName="ip/blinki_bd_rst_ps7_0_100M_0/blinki_bd_rst_ps7_0_100M_0.xci">
<Proxy FileSetName="design_1_v_tc_0_0"/> <Proxy FileSetName="blinki_bd_rst_ps7_0_100M_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_rst_processing_system7_0_100M_1/design_1_rst_processing_system7_0_100M_1.xci">
<Proxy FileSetName="design_1_rst_processing_system7_0_100M_1"/>
</CompFileExtendedInfo> </CompFileExtendedInfo>
</File> </File>
<File Path="$PGENDIR/sources_1/bd/design_1/hdl/design_1_wrapper.v"> <File Path="$PPRDIR/v/async_reset.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PGENDIR/sources_1/bd/blinki_bd/hdl/blinki_bd_wrapper.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/v/display_clocks.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/v/display_demo_dvi.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/v/display_timings.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/v/dvi_generator.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/v/serializer_10to1.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/v/test_card_simple.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/v/tmds_encoder_dvi.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/v/dvi_top.v">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/> <Attr Name="UsedIn" Val="implementation"/>
@ -115,8 +175,7 @@
</File> </File>
<Config> <Config>
<Option Name="DesignMode" Val="RTL"/> <Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="design_1_wrapper"/> <Option Name="TopModule" Val="dvi_top"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config> </Config>
</FileSet> </FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1"> <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
@ -127,6 +186,12 @@
<Attr Name="UsedIn" Val="implementation"/> <Attr Name="UsedIn" Val="implementation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PPRDIR/xdc/timing.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config> <Config>
<Option Name="ConstrsType" Val="XDC"/> <Option Name="ConstrsType" Val="XDC"/>
</Config> </Config>
@ -135,7 +200,7 @@
<Filter Type="Srcs"/> <Filter Type="Srcs"/>
<Config> <Config>
<Option Name="DesignMode" Val="RTL"/> <Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="design_1_wrapper"/> <Option Name="TopModule" Val="dvi_top"/>
<Option Name="TopLib" Val="xil_defaultlib"/> <Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/> <Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/> <Option Name="TransportPathDelay" Val="0"/>
@ -150,14 +215,6 @@
</FileSet> </FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1"> <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/> <Filter Type="Utils"/>
<File Path="$PSRCDIR/utils_1/imports/synth_2/design_1_wrapper.dcp">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedInSteps" Val="synth_2"/>
<Attr Name="AutoDcp" Val="1"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/utils_1/imports/synth_1/design_1_wrapper.dcp"> <File Path="$PSRCDIR/utils_1/imports/synth_1/design_1_wrapper.dcp">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
@ -170,21 +227,15 @@
<Option Name="TopAutoSet" Val="TRUE"/> <Option Name="TopAutoSet" Val="TRUE"/>
</Config> </Config>
</FileSet> </FileSet>
<FileSet Name="design_1_processing_system7_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_processing_system7_0_0" RelGenDir="$PGENDIR/design_1_processing_system7_0_0"> <FileSet Name="blinki_bd_axi_gpio_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/blinki_bd_axi_gpio_0_0" RelGenDir="$PGENDIR/blinki_bd_axi_gpio_0_0">
<Config> <Config>
<Option Name="TopModule" Val="design_1_processing_system7_0_0"/> <Option Name="TopModule" Val="blinki_bd_axi_gpio_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/> <Option Name="UseBlackboxStub" Val="1"/>
</Config> </Config>
</FileSet> </FileSet>
<FileSet Name="design_1_rst_processing_system7_0_100M_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_rst_processing_system7_0_100M_1" RelGenDir="$PGENDIR/design_1_rst_processing_system7_0_100M_1"> <FileSet Name="blinki_bd_rst_ps7_0_100M_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/blinki_bd_rst_ps7_0_100M_0" RelGenDir="$PGENDIR/blinki_bd_rst_ps7_0_100M_0">
<Config> <Config>
<Option Name="TopModule" Val="design_1_rst_processing_system7_0_100M_1"/> <Option Name="TopModule" Val="blinki_bd_rst_ps7_0_100M_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="design_1_v_tc_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_v_tc_0_0" RelGenDir="$PGENDIR/design_1_v_tc_0_0">
<Config>
<Option Name="TopModule" Val="design_1_v_tc_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/> <Option Name="UseBlackboxStub" Val="1"/>
</Config> </Config>
</FileSet> </FileSet>
@ -211,7 +262,7 @@
</Simulator> </Simulator>
</Simulators> </Simulators>
<Runs Version="1" Minor="15"> <Runs Version="1" Minor="15">
<Run Id="synth_2" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_2/design_1_wrapper.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_2" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_2"> <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/design_1_wrapper.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/> <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/>
<Step Id="synth_design"/> <Step Id="synth_design"/>
@ -221,7 +272,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/> <RQSFiles/>
</Run> </Run>
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/design_1_wrapper.dcp" WriteIncrSynthDcp="false" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1"> <Run Id="synth_2" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" Dir="$PRUNDIR/synth_2" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_2">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/> <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/>
<Step Id="synth_design"/> <Step Id="synth_design"/>
@ -231,9 +282,11 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/> <RQSFiles/>
</Run> </Run>
<Run Id="design_1_processing_system7_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_processing_system7_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_processing_system7_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_processing_system7_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_processing_system7_0_0_synth_1"> <Run Id="blinki_bd_axi_gpio_0_0_synth_1" Type="Ft3:Synth" SrcSet="blinki_bd_axi_gpio_0_0" Part="xc7z020clg400-1" ConstrsSet="blinki_bd_axi_gpio_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/blinki_bd_axi_gpio_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/blinki_bd_axi_gpio_0_0_synth_1">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/> <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/> <Step Id="synth_design"/>
</Strategy> </Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@ -241,9 +294,11 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/> <RQSFiles/>
</Run> </Run>
<Run Id="design_1_rst_processing_system7_0_100M_1_synth_1" Type="Ft3:Synth" SrcSet="design_1_rst_processing_system7_0_100M_1" Part="xc7z020clg400-1" ConstrsSet="design_1_rst_processing_system7_0_100M_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_rst_processing_system7_0_100M_1_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_rst_processing_system7_0_100M_1_synth_1"> <Run Id="blinki_bd_rst_ps7_0_100M_0_synth_1" Type="Ft3:Synth" SrcSet="blinki_bd_rst_ps7_0_100M_0" Part="xc7z020clg400-1" ConstrsSet="blinki_bd_rst_ps7_0_100M_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/blinki_bd_rst_ps7_0_100M_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/blinki_bd_rst_ps7_0_100M_0_synth_1">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/> <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/> <Step Id="synth_design"/>
</Strategy> </Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@ -251,17 +306,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/> <RQSFiles/>
</Run> </Run>
<Run Id="design_1_v_tc_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_v_tc_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_v_tc_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_v_tc_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_v_tc_0_0_synth_1"> <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../hdmi-thru/hdmi-thru.srcs/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2021"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_2" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_2" SynthRun="synth_2" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_2">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/>
<Step Id="init_design"/> <Step Id="init_design"/>
@ -279,7 +324,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/> <RQSFiles/>
</Run> </Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1"> <Run Id="impl_2" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/impl_2" SynthRun="synth_2" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../hdmi-thru/hdmi-thru.srcs/utils_1/imports/impl_2">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/>
<Step Id="init_design"/> <Step Id="init_design"/>
@ -297,9 +342,11 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/> <RQSFiles/>
</Run> </Run>
<Run Id="design_1_processing_system7_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_processing_system7_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_processing_system7_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_processing_system7_0_0_impl_1"> <Run Id="blinki_bd_axi_gpio_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="blinki_bd_axi_gpio_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="blinki_bd_axi_gpio_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/blinki_bd_axi_gpio_0_0_impl_1">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/> <Step Id="init_design"/>
<Step Id="opt_design"/> <Step Id="opt_design"/>
<Step Id="power_opt_design"/> <Step Id="power_opt_design"/>
@ -314,26 +361,11 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/> <RQSFiles/>
</Run> </Run>
<Run Id="design_1_rst_processing_system7_0_100M_1_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_rst_processing_system7_0_100M_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_rst_processing_system7_0_100M_1_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_rst_processing_system7_0_100M_1_impl_1"> <Run Id="blinki_bd_rst_ps7_0_100M_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="blinki_bd_rst_ps7_0_100M_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="blinki_bd_rst_ps7_0_100M_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/blinki_bd_rst_ps7_0_100M_0_impl_1">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021">
<Step Id="init_design"/> <Desc>Default settings for Implementation.</Desc>
<Step Id="opt_design"/> </StratHandle>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2021"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="design_1_v_tc_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_v_tc_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_v_tc_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_v_tc_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/>
<Step Id="init_design"/> <Step Id="init_design"/>
<Step Id="opt_design"/> <Step Id="opt_design"/>
<Step Id="power_opt_design"/> <Step Id="power_opt_design"/>
@ -356,15 +388,26 @@
<Dashboards> <Dashboards>
<Dashboard Name="default_dashboard"> <Dashboard Name="default_dashboard">
<Gadgets> <Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0"/> <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1"/> <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0"/> </Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1"/> <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0"> <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/> <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/> <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget> </Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1"/> <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets> </Gadgets>
</Dashboard> </Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard> <CurrentDashboard>default_dashboard</CurrentDashboard>

25
hdmi-out-test/v/async_reset.v 100644
View File

@ -0,0 +1,25 @@
`timescale 1ns / 1ps
`default_nettype none
// Project F: Async Reset
// (C)2019 Will Green, Open source hardware released under the MIT License
// Learn more at https://projectf.io
module async_reset(
input wire i_clk, // clock
input wire i_rst, // reset (active high)
output reg o_rst // output reset
);
(* ASYNC_REG = "TRUE" *) reg [1:0] rst_shf; // reset shift reg
initial o_rst = 1'b1; // start off with reset asserted
initial rst_shf = 2'b11; // and reset shift reg populated
always @(posedge i_clk or posedge i_rst)
if (i_rst)
{o_rst, rst_shf} <= 3'b111;
else
{o_rst, rst_shf} <= {rst_shf, 1'b0};
endmodule

96
hdmi-out-test/v/display_clocks.v 100644
View File

@ -0,0 +1,96 @@
`timescale 1ns / 1ps
`default_nettype none
// Project F: Display Clocks
// (C)2019 Will Green, Open source hardware released under the MIT License
// Learn more at https://projectf.io
// Defaults to 25.2 and 126 MHz for 640x480 at 60 Hz
module display_clocks #(
MULT_MASTER=31.5, // master clock multiplier (2.000-64.000)
DIV_MASTER=5, // master clock divider (1-106)
DIV_5X=5.0, // 5x clock divider (1-128)
DIV_1X=25, // 1x clock divider (1-128)
IN_PERIOD=10.0 // period of i_clk in ns (100 MHz = 10.0 ns)
)
(
input wire i_clk, // input clock
input wire i_rst, // reset (active high)
output wire o_clk_1x, // pixel clock
output wire o_clk_5x, // 5x clock for 10:1 DDR SerDes
output wire o_locked // clock locked? (active high)
);
wire clk_fb; // internal clock feedback
wire clk_1x_pre;
wire clk_5x_pre;
MMCME2_BASE #(
.BANDWIDTH("OPTIMIZED"), // Jitter programming (OPTIMIZED, HIGH, LOW)
.CLKFBOUT_MULT_F(MULT_MASTER), // Multiply value for all CLKOUT (2.000-64.000).
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB (-360.000-360.000).
.CLKIN1_PERIOD(IN_PERIOD), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
// CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128)
.CLKOUT0_DIVIDE_F(DIV_5X), // Divide amount for CLKOUT0 (1.000-128.000).
.CLKOUT1_DIVIDE(DIV_1X),
.CLKOUT2_DIVIDE(1),
.CLKOUT3_DIVIDE(1),
.CLKOUT4_DIVIDE(1),
.CLKOUT5_DIVIDE(1),
.CLKOUT6_DIVIDE(1),
// CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99).
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT6_DUTY_CYCLE(0.5),
// CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.CLKOUT6_PHASE(0.0),
.CLKOUT4_CASCADE("FALSE"), // Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE)
.DIVCLK_DIVIDE(DIV_MASTER), // Master division value (1-106)
.REF_JITTER1(0.010), // Reference input jitter in UI (0.000-0.999).
.STARTUP_WAIT("FALSE") // Delays DONE until MMCM is locked (FALSE, TRUE)
)
MMCME2_BASE_inst (
/* verilator lint_off PINCONNECTEMPTY */
// Clock Outputs: 1-bit (each) output: User configurable clock outputs
.CLKOUT0(clk_5x_pre), // 1-bit output: CLKOUT0
.CLKOUT0B(), // 1-bit output: Inverted CLKOUT0
.CLKOUT1(clk_1x_pre), // 1-bit output: CLKOUT1
.CLKOUT1B(), // 1-bit output: Inverted CLKOUT1
.CLKOUT2(), // 1-bit output: CLKOUT2
.CLKOUT2B(), // 1-bit output: Inverted CLKOUT2
.CLKOUT3(), // 1-bit output: CLKOUT3
.CLKOUT3B(), // 1-bit output: Inverted CLKOUT3
.CLKOUT4(), // 1-bit output: CLKOUT4
.CLKOUT5(), // 1-bit output: CLKOUT5
.CLKOUT6(), // 1-bit output: CLKOUT6
// Feedback Clocks: 1-bit (each) output: Clock feedback ports
.CLKFBOUT(clk_fb), // 1-bit output: Feedback clock
.CLKFBOUTB(), // 1-bit output: Inverted CLKFBOUT
// Status Ports: 1-bit (each) output: MMCM status ports
.LOCKED(o_locked), // 1-bit output: LOCK
// Clock Inputs: 1-bit (each) input: Clock input
.CLKIN1(i_clk), // 1-bit input: Clock
// Control Ports: 1-bit (each) input: MMCM control ports
.PWRDWN(), // 1-bit input: Power-down
/* verilator lint_on PINCONNECTEMPTY */
.RST(i_rst), // 1-bit input: Reset
// Feedback Clocks: 1-bit (each) input: Clock feedback ports
.CLKFBIN(clk_fb) // 1-bit input: Feedback clock
);
// explicitly buffer output clocks
BUFG bufg_clk_pix(.I(clk_1x_pre), .O(o_clk_1x));
BUFG bufg_clk_pix_5x(.I(clk_5x_pre), .O(o_clk_5x));
endmodule

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`timescale 1ns / 1ps
//`default_nettype none
// Project F: Display Controller DVI Demo
// (C)2020 Will Green, Open source hardware released under the MIT License
// Learn more at https://projectf.io
// This demo requires the following Verilog modules:
// * display_clocks
// * display_timings
// * dvi_generator
// * serializer_10to1
// * async_reset
// * tmds_encoder_dvi
// * test_card_simple or another test card
module display_demo_dvi(
input wire [1:0] sel, // test card modifier. original output = 0
input wire CLK, // board clock: 100 MHz on Arty/Basys3/Nexys
input wire RST_BTN, // reset button
inout wire hdmi_tx_cec, // CE control bidirectional
input wire hdmi_tx_hpd, // hot-plug detect
inout wire hdmi_tx_rscl, // DDC bidirectional
inout wire hdmi_tx_rsda, // DDC bidirectional
output wire hdmi_tx_clk_n, // HDMI clock differential negative
output wire hdmi_tx_clk_p, // HDMI clock differential positive
output wire [2:0] hdmi_tx_n, // Three HDMI channels differential negative
output wire [2:0] hdmi_tx_p // Three HDMI channels differential positive
);
// Display Clocks
wire pix_clk; // pixel clock
wire pix_clk_5x; // 5x clock for 10:1 DDR SerDes
wire clk_lock; // clock locked?
display_clocks #( // 640x480 800x600 1280x720 1920x1080
.MULT_MASTER(37.125), // 31.5 10.0 37.125 37.125
.DIV_MASTER(5), // 5 1 5 5
.DIV_5X(2.0), // 5.0 5.0 2.0 1.0
.DIV_1X(10), // 25 25 10 5
.IN_PERIOD(10.0) // 100 MHz = 10 ns
)
display_clocks_inst
(
.i_clk(CLK),
.i_rst(~RST_BTN), // reset is active low on Arty & Nexys Video
.o_clk_1x(pix_clk),
.o_clk_5x(pix_clk_5x),
.o_locked(clk_lock)
);
// Display Timings
wire signed [15:0] sx; // horizontal screen position (signed)
wire signed [15:0] sy; // vertical screen position (signed)
wire h_sync; // horizontal sync
wire v_sync; // vertical sync
wire de; // display enable
wire frame; // frame start
display_timings #( // 640x480 800x600 1280x720 1920x1080
.H_RES(1280), // 640 800 1280 1920
.V_RES(720), // 480 600 720 1080
.H_FP(110), // 16 40 110 88
.H_SYNC(40), // 96 128 40 44
.H_BP(220), // 48 88 220 148
.V_FP(5), // 10 1 5 4
.V_SYNC(5), // 2 4 5 5
.V_BP(20), // 33 23 20 36
.H_POL(1), // 0 1 1 1
.V_POL(1) // 0 1 1 1
)
display_timings_inst (
.i_pix_clk(pix_clk),
.i_rst(!clk_lock),
.o_hs(h_sync),
.o_vs(v_sync),
.o_de(de),
.o_frame(frame),
.o_sx(sx),
.o_sy(sy)
);
// test card colour output
wire [7:0] w_red ,red ;
wire [7:0] w_green,green;
wire [7:0] w_blue ,blue ;
// Test Card: Simple - ENABLE ONE TEST CARD INSTANCE ONLY
test_card_simple #(
.H_RES(1280) // horizontal resolution
) test_card_inst (
.i_x (sx ),
.o_red (w_red ),
.o_green(w_green),
.o_blue (w_blue )
);
assign red = ( sel[0] )? ~w_red : w_red ;
assign green = ( sel[0] )? ~w_green: w_green;
assign blue = ( sel[0] )? ~w_blue : w_blue ;
// // Test Card: Squares - ENABLE ONE TEST CARD INSTANCE ONLY
// test_card_squares #(
// .H_RES(1280), // horizontal resolution
// .V_RES(720) // vertical resolution
// )
// test_card_inst (
// .i_x(sx),
// .i_y(sy),
// .o_red(red),
// .o_green(green),
// .o_blue(blue)
// );
// // Test Card: Gradient - ENABLE ONE TEST CARD INSTANCE ONLY
// localparam GRAD_STEP = 2; // step right shift: 480=2, 720=2, 1080=3
// test_card_gradient test_card_inst (
// .i_y(sy[GRAD_STEP+7:GRAD_STEP]),
// .i_x(sx[5:0]),
// .o_red(red),
// .o_green(green),
// .o_blue(blue)
// );
// TMDS Encoding and Serialization
wire tmds_ch0_serial, tmds_ch1_serial, tmds_ch2_serial, tmds_chc_serial;
dvi_generator dvi_out (
.i_pix_clk(pix_clk),
.i_pix_clk_5x(pix_clk_5x),
.i_rst(!clk_lock),
.i_de(de),
.i_data_ch0(blue),
.i_data_ch1(green),
.i_data_ch2(red),
.i_ctrl_ch0({v_sync, h_sync}),
.i_ctrl_ch1(2'b00),
.i_ctrl_ch2(2'b00),
.o_tmds_ch0_serial(tmds_ch0_serial),
.o_tmds_ch1_serial(tmds_ch1_serial),
.o_tmds_ch2_serial(tmds_ch2_serial),
.o_tmds_chc_serial(tmds_chc_serial) // encode pixel clock via same path
);
// TMDS Buffered Output
OBUFDS #(.IOSTANDARD("TMDS_33"))
tmds_buf_ch0 (.I(tmds_ch0_serial), .O(hdmi_tx_p[0]), .OB(hdmi_tx_n[0]));
OBUFDS #(.IOSTANDARD("TMDS_33"))
tmds_buf_ch1 (.I(tmds_ch1_serial), .O(hdmi_tx_p[1]), .OB(hdmi_tx_n[1]));
OBUFDS #(.IOSTANDARD("TMDS_33"))
tmds_buf_ch2 (.I(tmds_ch2_serial), .O(hdmi_tx_p[2]), .OB(hdmi_tx_n[2]));
OBUFDS #(.IOSTANDARD("TMDS_33"))
tmds_buf_chc (.I(tmds_chc_serial), .O(hdmi_tx_clk_p), .OB(hdmi_tx_clk_n));
assign hdmi_tx_cec = 1'bz;
assign hdmi_tx_rsda = 1'bz;
assign hdmi_tx_rscl = 1'b1;
endmodule

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`timescale 1ns / 1ps
`default_nettype none
// Project F: Display Timings
// (C)2019 Will Green, Open Source Hardware released under the MIT License
// Learn more at https://projectf.io
// Defaults to 640x480 at 60 Hz
module display_timings #(
H_RES=640, // horizontal resolution (pixels)
V_RES=480, // vertical resolution (lines)
H_FP=16, // horizontal front porch
H_SYNC=96, // horizontal sync
H_BP=48, // horizontal back porch
V_FP=10, // vertical front porch
V_SYNC=2, // vertical sync
V_BP=33, // vertical back porch
H_POL=0, // horizontal sync polarity (0:neg, 1:pos)
V_POL=0 // vertical sync polarity (0:neg, 1:pos)
)
(
input wire i_pix_clk, // pixel clock
input wire i_rst, // reset: restarts frame (active high)
output wire o_hs, // horizontal sync
output wire o_vs, // vertical sync
output wire o_de, // display enable: high during active video
output wire o_frame, // high for one tick at the start of each frame
output reg signed [15:0] o_sx, // horizontal beam position (including blanking)
output reg signed [15:0] o_sy // vertical beam position (including blanking)
);
// Horizontal: sync, active, and pixels
localparam signed H_STA = 0 - H_FP - H_SYNC - H_BP; // horizontal start
localparam signed HS_STA = H_STA + H_FP; // sync start
localparam signed HS_END = HS_STA + H_SYNC; // sync end
localparam signed HA_STA = 0; // active start
localparam signed HA_END = H_RES - 1; // active end
// Vertical: sync, active, and pixels
localparam signed V_STA = 0 - V_FP - V_SYNC - V_BP; // vertical start
localparam signed VS_STA = V_STA + V_FP; // sync start
localparam signed VS_END = VS_STA + V_SYNC; // sync end
localparam signed VA_STA = 0; // active start
localparam signed VA_END = V_RES - 1; // active end
// generate sync signals with correct polarity
assign o_hs = H_POL ? (o_sx > HS_STA && o_sx <= HS_END)
: ~(o_sx > HS_STA && o_sx <= HS_END);
assign o_vs = V_POL ? (o_sy > VS_STA && o_sy <= VS_END)
: ~(o_sy > VS_STA && o_sy <= VS_END);
// display enable: high during active period
assign o_de = (o_sx >= 0 && o_sy >= 0);
// o_frame: high for one tick at the start of each frame
assign o_frame = (o_sy == V_STA && o_sx == H_STA);
always @ (posedge i_pix_clk)
begin
if (i_rst) // reset to start of frame
begin
o_sx <= H_STA;
o_sy <= V_STA;
end
else
begin
if (o_sx == HA_END) // end of line
begin
o_sx <= H_STA;
if (o_sy == VA_END) // end of frame
o_sy <= V_STA;
else
o_sy <= o_sy + 16'sh1;
end
else
o_sx <= o_sx + 16'sh1;
end
end
endmodule

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`timescale 1ns / 1ps
`default_nettype none
// Project F: Display DVI Generator
// (C)2019 Will Green, Open Source Hardware released under the MIT License
// Learn more at https://projectf.io
module dvi_generator(
input wire i_pix_clk, // pixel clock
input wire i_pix_clk_5x, // 5 x pixel clock for DDR serialization
input wire i_rst, // reset (active high)
input wire i_de, // display enable (draw video)
input wire [7:0] i_data_ch0, // channel 0 - 8-bit colour data
input wire [7:0] i_data_ch1, // channel 1 - 8-bit colour data
input wire [7:0] i_data_ch2, // channel 2 - 8-bit colour data
input wire [1:0] i_ctrl_ch0, // channel 0 - 2-bit control data
input wire [1:0] i_ctrl_ch1, // channel 1 - 2-bit control data
input wire [1:0] i_ctrl_ch2, // channel 2 - 2-bit control data
output wire o_tmds_ch0_serial, // channel 0 - serial TMDS
output wire o_tmds_ch1_serial, // channel 1 - serial TMDS
output wire o_tmds_ch2_serial, // channel 2 - serial TMDS
output wire o_tmds_chc_serial // channel clock - serial TMDS
);
wire [9:0] tmds_ch0, tmds_ch1, tmds_ch2;
tmds_encoder_dvi encode_ch0 (
.i_clk(i_pix_clk),
.i_rst(i_rst),
.i_data(i_data_ch0),
.i_ctrl(i_ctrl_ch0),
.i_de(i_de),
.o_tmds(tmds_ch0)
);
tmds_encoder_dvi encode_ch1 (
.i_clk(i_pix_clk),
.i_rst(i_rst),
.i_data(i_data_ch1),
.i_ctrl(i_ctrl_ch1),
.i_de(i_de),
.o_tmds(tmds_ch1)
);
tmds_encoder_dvi encode_ch2 (
.i_clk(i_pix_clk),
.i_rst(i_rst),
.i_data(i_data_ch2),
.i_ctrl(i_ctrl_ch2),
.i_de(i_de),
.o_tmds(tmds_ch2)
);
// common async reset for serdes
wire rst_oserdes;
async_reset async_reset_instance (
.i_clk(i_pix_clk),
.i_rst(i_rst),
.o_rst(rst_oserdes)
);
serializer_10to1 serialize_ch0 (
.i_clk(i_pix_clk),
.i_clk_hs(i_pix_clk_5x),
.i_rst_oserdes(rst_oserdes),
.i_data(tmds_ch0),
.o_data(o_tmds_ch0_serial)
);
serializer_10to1 serialize_ch1 (
.i_clk(i_pix_clk),
.i_clk_hs(i_pix_clk_5x),
.i_rst_oserdes(rst_oserdes),
.i_data(tmds_ch1),
.o_data(o_tmds_ch1_serial)
);
serializer_10to1 serialize_ch2 (
.i_clk(i_pix_clk),
.i_clk_hs(i_pix_clk_5x),
.i_rst_oserdes(rst_oserdes),
.i_data(tmds_ch2),
.o_data(o_tmds_ch2_serial)
);
serializer_10to1 serialize_chc (
.i_clk(i_pix_clk),
.i_clk_hs(i_pix_clk_5x),
.i_rst_oserdes(rst_oserdes),
.i_data(10'b0000011111),
.o_data(o_tmds_chc_serial)
);
endmodule

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`default_nettype wire
module dvi_top(
output wire BCLK_O,
inout wire [14:0] DDR_addr,
inout wire [ 2:0] DDR_ba,
inout wire DDR_cas_n,
inout wire DDR_ck_n,
inout wire DDR_ck_p,
inout wire DDR_cke,
inout wire DDR_cs_n,
inout wire [ 3:0] DDR_dm,
inout wire [31:0] DDR_dq,
inout wire [ 3:0] DDR_dqs_n,
inout wire [ 3:0] DDR_dqs_p,
inout wire DDR_odt,
inout wire DDR_ras_n,
inout wire DDR_reset_n,
inout wire DDR_we_n,
inout wire FIXED_IO_ddr_vrn,
inout wire FIXED_IO_ddr_vrp,
inout wire [53:0] FIXED_IO_mio,
inout wire FIXED_IO_ps_clk,
inout wire FIXED_IO_ps_porb,
inout wire FIXED_IO_ps_srstb,
output wire LRCLK_O,
output wire MCLK_O,
input wire SDATA_I,
output wire SDATA_O,
input wire TMDS_Clk_n_1,
input wire TMDS_Clk_p_1,
input wire [2:0] TMDS_Data_n_1,
input wire [2:0] TMDS_Data_p_1,
output wire TMDS_Clk_n_0 ,
output wire TMDS_Clk_p_0 ,
output wire [2:0] TMDS_Data_n_0,
output wire [2:0] TMDS_Data_p_0,
input wire [3:0] btns_4bits_tri_i,
inout wire hdmi_in_ddc_scl_io,
inout wire hdmi_in_ddc_sda_io,
output wire [0:0] hdmi_rx_hpd ,
input wire hdmi_tx_hpd ,
inout wire iic_rtl_scl_io,
inout wire iic_rtl_sda_io,
output wire leds_4bits_tri_o_3,
output wire leds_4bits_tri_o_2,
output wire leds_4bits_tri_o_1,
output wire leds_4bits_tri_o_0,
input wire sws_2bits_tri_i_1,
input wire sws_2bits_tri_i_0
);
wire CLK ;
// wire RST_BTN ;
// wire hdmi_tx_cec ;
// wire hdmi_tx_hpd ;
// wire hdmi_tx_rscl ;
// wire hdmi_tx_rsda ;
// wire hdmi_tx_clk_n ;
// wire hdmi_tx_clk_p ;
// wire [2:0] hdmi_tx_n ;
// wire [2:0] hdmi_tx_p ;
blinki_bd_wrapper bd0 (
.FCLK_CLK0_0 (CLK),
.FCLK_CLK1_0 (),
//.leds_4bits_tri_io ({
.gpio_io_o_0 ({
//leds_4bits_tri_o_3,
1'bz,
leds_4bits_tri_o_2,
leds_4bits_tri_o_1,
leds_4bits_tri_o_0
})
);
assign leds_4bits_tri_o_3 = hdmi_tx_hpd;
display_demo_dvi u_demoDVI(
.CLK (CLK), // board clock: 100 MHz on Arty/Basys3/Nexys
.RST_BTN (~btns_4bits_tri_i[0]), // reset button
.hdmi_tx_cec (), // CE control bidirectional
.hdmi_tx_hpd (hdmi_tx_hpd ), // hot-plug detect
.hdmi_tx_rscl (hdmi_in_ddc_scl_io), // DDC bidirectional
.hdmi_tx_rsda (hdmi_in_ddc_sda_io), // DDC bidirectional
.hdmi_tx_clk_n(TMDS_Clk_n_0 ), // HDMI clock differential negative
.hdmi_tx_clk_p(TMDS_Clk_p_0 ), // HDMI clock differential positive
.hdmi_tx_n (TMDS_Data_n_0 ), // Three HDMI channels differential negative
.hdmi_tx_p (TMDS_Data_p_0 ), // Three HDMI channels differential positive
.sel ({ sws_2bits_tri_i_1,
sws_2bits_tri_i_0
}) // Three HDMI channels differential positive
);
endmodule

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`timescale 1ns / 1ps
`default_nettype none
// Project F: Display 10:1 Serializer
// (C)2019 Will Green, Open source hardware released under the MIT License
// Learn more at https://projectf.io
module serializer_10to1(
input wire i_clk, // parallel clock
input wire i_clk_hs, // high-speed clock (5 x i_clk when using DDR)
input wire i_rst_oserdes, // reset from async reset (active high)
input wire [9:0] i_data, // input parallel data
output wire o_data // output serial data
);
// use two OSERDES2 to serialize 10-bit TMDS data
wire shift1, shift2; // wires between oserdes master and slave
OSERDESE2 #(
.DATA_RATE_OQ("DDR"), // DDR, SDR
.DATA_RATE_TQ("SDR"), // DDR, BUF, SDR
.DATA_WIDTH(10), // Parallel data width (2-8,10,14)
.INIT_OQ(1'b1), // Initial value of OQ output (1'b0,1'b1)
.INIT_TQ(1'b1), // Initial value of TQ output (1'b0,1'b1)
.SERDES_MODE("MASTER"), // MASTER, SLAVE
.SRVAL_OQ(1'b0), // OQ output value when SR is used (1'b0,1'b1)
.SRVAL_TQ(1'b0), // TQ output value when SR is used (1'b0,1'b1)
.TBYTE_CTL("FALSE"), // Enable tristate byte operation (FALSE, TRUE)
.TBYTE_SRC("FALSE"), // Tristate byte source (FALSE, TRUE)
.TRISTATE_WIDTH(1) // 3-state converter width (1,4)
)
master10 (
/* verilator lint_off PINCONNECTEMPTY */
.OFB(), // 1-bit output: Feedback path for data
.OQ(o_data), // 1-bit output: Data path output
// SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
.SHIFTOUT1(),
.SHIFTOUT2(),
.TBYTEOUT(), // 1-bit output: Byte group tristate
.TFB(), // 1-bit output: 3-state control
.TQ(), // 1-bit output: 3-state control
.CLK(i_clk_hs), // 1-bit input: High speed clock
.CLKDIV(i_clk), // 1-bit input: Divided clock
/* verilator lint_on PINCONNECTEMPTY */
// D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
.D1(i_data[0]),
.D2(i_data[1]),
.D3(i_data[2]),
.D4(i_data[3]),
.D5(i_data[4]),
.D6(i_data[5]),
.D7(i_data[6]),
.D8(i_data[7]),
.OCE(1'b1), // 1-bit input: Output data clock enable
.RST(i_rst_oserdes), // 1-bit input: Reset
// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
.SHIFTIN1(shift1),
.SHIFTIN2(shift2),
// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
.T1(1'b0),
.T2(1'b0),
.T3(1'b0),
.T4(1'b0),
.TBYTEIN(1'b0), // 1-bit input: Byte group tristate
.TCE(1'b0) // 1-bit input: 3-state clock enable
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"), // DDR, SDR
.DATA_RATE_TQ("SDR"), // DDR, BUF, SDR
.DATA_WIDTH(10), // Parallel data width (2-8,10,14)
.INIT_OQ(1'b1), // Initial value of OQ output (1'b0,1'b1)
.INIT_TQ(1'b1), // Initial value of TQ output (1'b0,1'b1)
.SERDES_MODE("SLAVE"), // MASTER, SLAVE
.SRVAL_OQ(1'b0), // OQ output value when SR is used (1'b0,1'b1)
.SRVAL_TQ(1'b0), // TQ output value when SR is used (1'b0,1'b1)
.TBYTE_CTL("FALSE"), // Enable tristate byte operation (FALSE, TRUE)
.TBYTE_SRC("FALSE"), // Tristate byte source (FALSE, TRUE)
.TRISTATE_WIDTH(1) // 3-state converter width (1,4)
)
slave10 (
/* verilator lint_off PINCONNECTEMPTY */
.OFB(), // 1-bit output: Feedback path for data
.OQ(), // 1-bit output: Data path output
// SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
.SHIFTOUT1(shift1),
.SHIFTOUT2(shift2),
.TBYTEOUT(), // 1-bit output: Byte group tristate
.TFB(), // 1-bit output: 3-state control
.TQ(), // 1-bit output: 3-state control
.CLK(i_clk_hs), // 1-bit input: High speed clock
.CLKDIV(i_clk), // 1-bit input: Divided clock
/* verilator lint_on PINCONNECTEMPTY */
// D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
.D1(1'b0),
.D2(1'b0),
.D3(i_data[8]),
.D4(i_data[9]),
.D5(1'b0),
.D6(1'b0),
.D7(1'b0),
.D8(1'b0),
.OCE(1'b1), // 1-bit input: Output data clock enable
.RST(i_rst_oserdes), // 1-bit input: Reset
// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
.SHIFTIN1(1'b0),
.SHIFTIN2(1'b0),
// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
.T1(1'b0),
.T2(1'b0),
.T3(1'b0),
.T4(1'b0),
.TBYTEIN(1'b0), // 1-bit input: Byte group tristate
.TCE(1'b0) // 1-bit input: 3-state clock enable
);
endmodule

31
hdmi-out-test/v/test_card_simple.v 100644
View File

@ -0,0 +1,31 @@
`timescale 1ns / 1ps
`default_nettype none
// Project F: Display Controller Simple Test Card
// (C)2019 Will Green, Open Source Hardware released under the MIT License
// Learn more at https://projectf.io
module test_card_simple #(H_RES=640) (
input wire signed [15:0] i_x,
output wire [7:0] o_red,
output wire [7:0] o_green,
output wire [7:0] o_blue
);
localparam HW = H_RES >> 3; // horizontal colour width = H_RES / 8
// Bands
wire b0 = (i_x >= 0 ) & (i_x < HW );
wire b1 = (i_x >= HW ) & (i_x < HW * 2);
wire b2 = (i_x >= HW * 2) & (i_x < HW * 3);
wire b3 = (i_x >= HW * 3) & (i_x < HW * 4);
wire b4 = (i_x >= HW * 4) & (i_x < HW * 5);
wire b5 = (i_x >= HW * 5) & (i_x < HW * 6);
wire b6 = (i_x >= HW * 6) & (i_x < HW * 7);
wire b7 = (i_x >= HW * 7) & (i_x < HW * 8);
// Colour Output
assign o_red = {8{b0 | b1 | b5}} + {2'b0,{6{b6}}} + {b7, 7'b0};
assign o_green = {8{b1 | b2 | b3}} + {2'b0,{6{b6}}} + {b7, 7'b0};
assign o_blue = {8{b3 | b4 | b5}} + {2'b0,{6{b6}}} + {b7, 7'b0};
endmodule

95
hdmi-out-test/v/tmds_encoder_dvi.v 100644
View File

@ -0,0 +1,95 @@
`timescale 1ns / 1ps
`default_nettype none
// Project F: Display TMDS Encoder for DVI
// (C)2019 Will Green, Open source hardware released under the MIT License
// Learn more at https://projectf.io
module tmds_encoder_dvi(
input wire i_clk, // clock
input wire i_rst, // reset (active high)
input wire [7:0] i_data, // colour data
input wire [1:0] i_ctrl, // control data
input wire i_de, // display enable (active high)
output reg [9:0] o_tmds // encoded TMDS data
);
// select basic encoding based on the ones in the input data
wire [3:0] d_ones = {3'b0,i_data[0]} + {3'b0,i_data[1]} + {3'b0,i_data[2]}
+ {3'b0,i_data[3]} + {3'b0,i_data[4]} + {3'b0,i_data[5]}
+ {3'b0,i_data[6]} + {3'b0,i_data[7]};
wire use_xnor = (d_ones > 4'd4) || ((d_ones == 4'd4) && (i_data[0] == 0));
// encode colour data with xor/xnor
/* verilator lint_off UNOPTFLAT */
wire [8:0] enc_qm;
assign enc_qm[0] = i_data[0];
assign enc_qm[1] = (use_xnor) ? (enc_qm[0] ~^ i_data[1]) : (enc_qm[0] ^ i_data[1]);
assign enc_qm[2] = (use_xnor) ? (enc_qm[1] ~^ i_data[2]) : (enc_qm[1] ^ i_data[2]);
assign enc_qm[3] = (use_xnor) ? (enc_qm[2] ~^ i_data[3]) : (enc_qm[2] ^ i_data[3]);
assign enc_qm[4] = (use_xnor) ? (enc_qm[3] ~^ i_data[4]) : (enc_qm[3] ^ i_data[4]);
assign enc_qm[5] = (use_xnor) ? (enc_qm[4] ~^ i_data[5]) : (enc_qm[4] ^ i_data[5]);
assign enc_qm[6] = (use_xnor) ? (enc_qm[5] ~^ i_data[6]) : (enc_qm[5] ^ i_data[6]);
assign enc_qm[7] = (use_xnor) ? (enc_qm[6] ~^ i_data[7]) : (enc_qm[6] ^ i_data[7]);
assign enc_qm[8] = (use_xnor) ? 0 : 1;
/* verilator lint_on UNOPTFLAT */
// disparity in encoded data for DC balancing: needs to cover -8 to +8
wire signed [4:0] ones = {4'b0,enc_qm[0]} + {4'b0,enc_qm[1]}
+ {4'b0,enc_qm[2]} + {4'b0,enc_qm[3]} + {4'b0,enc_qm[4]}
+ {4'b0,enc_qm[5]} + {4'b0,enc_qm[6]} + {4'b0,enc_qm[7]};
wire signed [4:0] zeros = 5'b01000 - ones;
wire signed [4:0] balance = ones - zeros;
// record ongoing DC bias
reg signed [4:0] bias;
always @ (posedge i_clk)
begin
if (i_rst)
begin
o_tmds <= 10'b1101010100; // equivalent to ctrl 2'b00
bias <= 5'sb00000;
end
else if (i_de == 0) // send control data in blanking interval
begin
case (i_ctrl) // ctrl sequences (always have 7 transitions)
2'b00: o_tmds <= 10'b1101010100;
2'b01: o_tmds <= 10'b0010101011;
2'b10: o_tmds <= 10'b0101010100;
default: o_tmds <= 10'b1010101011;
endcase
bias <= 5'sb00000;
end
else // send pixel colour data (at most 5 transitions)
begin
if (bias == 0 || balance == 0) // no prior bias or disparity
begin
if (enc_qm[8] == 0)
begin
$display("\t%d %b %d, %d, A1", i_data, enc_qm, ones, bias);
o_tmds[9:0] <= {2'b10, ~enc_qm[7:0]};
bias <= bias - balance;
end
else begin
$display("\t%d %b %d, %d, A0", i_data, enc_qm, ones, bias);
o_tmds[9:0] <= {2'b01, enc_qm[7:0]};
bias <= bias + balance;
end
end
else if ((bias > 0 && balance > 0) || (bias < 0 && balance < 0))
begin
$display("\t%d %b %d, %d, B1", i_data, enc_qm, ones, bias);
o_tmds[9:0] <= {1'b1, enc_qm[8], ~enc_qm[7:0]};
bias <= bias + {3'b0, enc_qm[8], 1'b0} - balance;
end
else
begin
$display("\t%d %b %d, %d, B0", i_data, enc_qm, ones, bias);
o_tmds[9:0] <= {1'b0, enc_qm[8], enc_qm[7:0]};
bias <= bias - {3'b0, ~enc_qm[8], 1'b0} + balance;
end
end
end
endmodule

91
hdmi-out-test/xdc/pynqz2.xdc
View File

@ -1,13 +1,13 @@
#set_property IOSTANDARD LVCMOS33 [get_ports {btns_4bits_tri_i_0}] set_property IOSTANDARD LVCMOS33 [get_ports {btns_4bits_tri_i[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {btns_4bits_tri_i_1}] set_property IOSTANDARD LVCMOS33 [get_ports {btns_4bits_tri_i[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {btns_4bits_tri_i_2}] set_property IOSTANDARD LVCMOS33 [get_ports {btns_4bits_tri_i[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {btns_4bits_tri_i_3}] set_property IOSTANDARD LVCMOS33 [get_ports {btns_4bits_tri_i[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {leds_4bits_tri_o_0}] set_property IOSTANDARD LVCMOS33 [get_ports {leds_4bits_tri_o_0}]
#set_property IOSTANDARD LVCMOS33 [get_ports {leds_4bits_tri_o_1}] set_property IOSTANDARD LVCMOS33 [get_ports {leds_4bits_tri_o_1}]
#set_property IOSTANDARD LVCMOS33 [get_ports {leds_4bits_tri_o_2}] set_property IOSTANDARD LVCMOS33 [get_ports {leds_4bits_tri_o_2}]
#set_property IOSTANDARD LVCMOS33 [get_ports {leds_4bits_tri_o_3}] set_property IOSTANDARD LVCMOS33 [get_ports {leds_4bits_tri_o_3}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sws_2bits_tri_i_0}] set_property IOSTANDARD LVCMOS33 [get_ports {sws_2bits_tri_i_0}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sws_2bits_tri_i_1}] set_property IOSTANDARD LVCMOS33 [get_ports {sws_2bits_tri_i_1}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sys_clk}] #set_property IOSTANDARD LVCMOS33 [get_ports {sys_clk}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA1}] #set_property IOSTANDARD LVCMOS33 [get_ports {JA1}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA2}] #set_property IOSTANDARD LVCMOS33 [get_ports {JA2}]
@ -76,26 +76,26 @@
#set_property IOSTANDARD LVCMOS33 [get_ports {spi_mosi_i}] #set_property IOSTANDARD LVCMOS33 [get_ports {spi_mosi_i}]
#set_property IOSTANDARD LVCMOS33 [get_ports {spi_sclk_i}] #set_property IOSTANDARD LVCMOS33 [get_ports {spi_sclk_i}]
#set_property IOSTANDARD LVCMOS33 [get_ports {spi_ss_i}] #set_property IOSTANDARD LVCMOS33 [get_ports {spi_ss_i}]
#set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_rx_hpd}] set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_rx_hpd}]
#set_property IOSTANDARD TMDS_33 [get_ports {TMDS_IN_clk_p}] set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Clk_p_1}]
#set_property IOSTANDARD TMDS_33 [get_ports {TMDS_IN_clk_n}] set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Clk_n_1}]
#set_property IOSTANDARD TMDS_33 [get_ports {TMDS_IN_data_p_0}] set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Data_p_1[0]}]
#set_property IOSTANDARD TMDS_33 [get_ports {TMDS_IN_data_p_1}] set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Data_p_1[1]}]
#set_property IOSTANDARD TMDS_33 [get_ports {TMDS_IN_data_p_2}] set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Data_p_1[2]}]
#set_property IOSTANDARD TMDS_33 [get_ports {TMDS_IN_data_n_0}] set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Data_n_1[0]}]
#set_property IOSTANDARD TMDS_33 [get_ports {TMDS_IN_data_n_1}] set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Data_n_1[1]}]
#set_property IOSTANDARD TMDS_33 [get_ports {TMDS_IN_data_n_2}] set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Data_n_1[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_tx_hpd}] set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_tx_hpd}]
set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Clk_n_0}]
set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Clk_p_0}] set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Clk_p_0}]
set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Clk_n_0}]
set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Data_p_0[0]}] set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Data_p_0[0]}]
set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Data_p_0[1]}] set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Data_p_0[1]}]
set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Data_p_0[2]}] set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Data_p_0[2]}]
set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Data_n_0[0]}] set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Data_n_0[0]}]
set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Data_n_0[1]}] set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Data_n_0[1]}]
set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Data_n_0[2]}] set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Data_n_0[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_in_ddc_scl}] set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_in_ddc_scl_io}]
#set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_in_ddc_sda}] set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_in_ddc_sda_io}]
#set_property IOSTANDARD LVCMOS33 [get_ports {respberry_sd_i}] #set_property IOSTANDARD LVCMOS33 [get_ports {respberry_sd_i}]
#set_property IOSTANDARD LVCMOS33 [get_ports {respberry_sc_i}] #set_property IOSTANDARD LVCMOS33 [get_ports {respberry_sc_i}]
#set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_tx_cec}] #set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_tx_cec}]
@ -117,16 +117,16 @@ set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Data_n_0[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sdada_out_i}] #set_property IOSTANDARD LVCMOS33 [get_ports {sdada_out_i}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sdata_in_i}] #set_property IOSTANDARD LVCMOS33 [get_ports {sdata_in_i}]
#set_property PACKAGE_PIN D19 [get_ports {btns_4bits_tri_i_0}] set_property PACKAGE_PIN D19 [get_ports {btns_4bits_tri_i[0]}]
#set_property PACKAGE_PIN D20 [get_ports {btns_4bits_tri_i_1}] set_property PACKAGE_PIN D20 [get_ports {btns_4bits_tri_i[1]}]
#set_property PACKAGE_PIN L20 [get_ports {btns_4bits_tri_i_2}] set_property PACKAGE_PIN L20 [get_ports {btns_4bits_tri_i[2]}]
#set_property PACKAGE_PIN L19 [get_ports {btns_4bits_tri_i_3}] set_property PACKAGE_PIN L19 [get_ports {btns_4bits_tri_i[3]}]
#set_property PACKAGE_PIN R14 [get_ports {leds_4bits_tri_o_0}] set_property PACKAGE_PIN R14 [get_ports {leds_4bits_tri_o_0}]
#set_property PACKAGE_PIN P14 [get_ports {leds_4bits_tri_o_1}] set_property PACKAGE_PIN P14 [get_ports {leds_4bits_tri_o_1}]
#set_property PACKAGE_PIN N16 [get_ports {leds_4bits_tri_o_2}] set_property PACKAGE_PIN N16 [get_ports {leds_4bits_tri_o_2}]
#set_property PACKAGE_PIN M14 [get_ports {leds_4bits_tri_o_3}] set_property PACKAGE_PIN M14 [get_ports {leds_4bits_tri_o_3}]
#set_property PACKAGE_PIN M20 [get_ports {sws_2bits_tri_i_0}] set_property PACKAGE_PIN M20 [get_ports {sws_2bits_tri_i_0}]
#set_property PACKAGE_PIN M19 [get_ports {sws_2bits_tri_i_1}] set_property PACKAGE_PIN M19 [get_ports {sws_2bits_tri_i_1}]
#set_property PACKAGE_PIN H16 [get_ports {sys_clk}] #set_property PACKAGE_PIN H16 [get_ports {sys_clk}]
#set_property PACKAGE_PIN Y18 [get_ports {JA1}] #set_property PACKAGE_PIN Y18 [get_ports {JA1}]
#set_property PACKAGE_PIN Y19 [get_ports {JA2}] #set_property PACKAGE_PIN Y19 [get_ports {JA2}]
@ -195,17 +195,16 @@ set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Data_n_0[2]}]
#set_property PACKAGE_PIN T12 [get_ports {spi_mosi_i}] #set_property PACKAGE_PIN T12 [get_ports {spi_mosi_i}]
#set_property PACKAGE_PIN H15 [get_ports {spi_sclk_i}] #set_property PACKAGE_PIN H15 [get_ports {spi_sclk_i}]
#set_property PACKAGE_PIN F16 [get_ports {spi_ss_i}] #set_property PACKAGE_PIN F16 [get_ports {spi_ss_i}]
#set_property PACKAGE_PIN T19 [get_ports {hdmi_rx_hpd}] set_property PACKAGE_PIN T19 [get_ports {hdmi_rx_hpd}]
#set_property PACKAGE_PIN N18 [get_ports {TMDS_IN_clk_p}] set_property PACKAGE_PIN N18 [get_ports {TMDS_Clk_p_1}]
#set_property PACKAGE_PIN P19 [get_ports {TMDS_IN_clk_n}] set_property PACKAGE_PIN P19 [get_ports {TMDS_Clk_n_1}]
#set_property PACKAGE_PIN V20 [get_ports {TMDS_IN_data_p_0}] set_property PACKAGE_PIN V20 [get_ports {TMDS_Data_p_1[0]}]
#set_property PACKAGE_PIN T20 [get_ports {TMDS_IN_data_p_1}] set_property PACKAGE_PIN T20 [get_ports {TMDS_Data_p_1[1]}]
#set_property PACKAGE_PIN N20 [get_ports {TMDS_IN_data_p_2}] set_property PACKAGE_PIN N20 [get_ports {TMDS_Data_p_1[2]}]
#set_property PACKAGE_PIN W20 [get_ports {TMDS_IN_data_n_0}] set_property PACKAGE_PIN W20 [get_ports {TMDS_Data_n_1[0]}]
#set_property PACKAGE_PIN U20 [get_ports {TMDS_IN_data_n_1}] set_property PACKAGE_PIN U20 [get_ports {TMDS_Data_n_1[1]}]
#set_property PACKAGE_PIN P20 [get_ports {TMDS_IN_data_n_2}] set_property PACKAGE_PIN P20 [get_ports {TMDS_Data_n_1[2]}]
#set_property PACKAGE_PIN R19 [get_ports {hdmi_tx_hpd}] set_property PACKAGE_PIN R19 [get_ports {hdmi_tx_hpd}]
set_property PACKAGE_PIN L16 [get_ports {TMDS_Clk_p_0}] set_property PACKAGE_PIN L16 [get_ports {TMDS_Clk_p_0}]
set_property PACKAGE_PIN L17 [get_ports {TMDS_Clk_n_0}] set_property PACKAGE_PIN L17 [get_ports {TMDS_Clk_n_0}]
set_property PACKAGE_PIN K17 [get_ports {TMDS_Data_p_0[0]}] set_property PACKAGE_PIN K17 [get_ports {TMDS_Data_p_0[0]}]
@ -214,8 +213,8 @@ set_property PACKAGE_PIN J18 [get_ports {TMDS_Data_p_0[2]}]
set_property PACKAGE_PIN K18 [get_ports {TMDS_Data_n_0[0]}] set_property PACKAGE_PIN K18 [get_ports {TMDS_Data_n_0[0]}]
set_property PACKAGE_PIN J19 [get_ports {TMDS_Data_n_0[1]}] set_property PACKAGE_PIN J19 [get_ports {TMDS_Data_n_0[1]}]
set_property PACKAGE_PIN H18 [get_ports {TMDS_Data_n_0[2]}] set_property PACKAGE_PIN H18 [get_ports {TMDS_Data_n_0[2]}]
#set_property PACKAGE_PIN U14 [get_ports {hdmi_in_ddc_scl}] set_property PACKAGE_PIN U14 [get_ports {hdmi_in_ddc_scl_io}]
#set_property PACKAGE_PIN U15 [get_ports {hdmi_in_ddc_sda}] set_property PACKAGE_PIN U15 [get_ports {hdmi_in_ddc_sda_io}]
#set_property PACKAGE_PIN Y16 [get_ports {respberry_sd_i}] #set_property PACKAGE_PIN Y16 [get_ports {respberry_sd_i}]
#set_property PACKAGE_PIN Y17 [get_ports {respberry_sc_i}] #set_property PACKAGE_PIN Y17 [get_ports {respberry_sc_i}]
#set_property PACKAGE_PIN G15 [get_ports {hdmi_tx_cec}] #set_property PACKAGE_PIN G15 [get_ports {hdmi_tx_cec}]

8
hdmi-out-test/xdc/timing.xdc 100644
View File

@ -0,0 +1,8 @@
#create_clock -period 13.468 -waveform {0.000 5.000} [get_ports hdmi_rx_clk_p]
#from digilent datasheet. Compile OK
create_clock -period 13.468 -waveform {0.000 5.000} [get_ports TMDS_Clk_p_1]
#from pynq ref design. compile failed due to VCO issues
#create_clock -period 8.334 -waveform {0.000 4.167} [get_ports TMDS_Clk_p_1]