diff --git a/hdmi-in-test/design_1_wrapper.xsa b/hdmi-in-test/design_1_wrapper.xsa new file mode 100644 index 0000000..3bcc843 Binary files /dev/null and b/hdmi-in-test/design_1_wrapper.xsa differ diff --git a/hdmi-in-test/docs/dvi2rgb.pdf b/hdmi-in-test/docs/dvi2rgb.pdf new file mode 100644 index 0000000..6b2fcc1 Binary files /dev/null and b/hdmi-in-test/docs/dvi2rgb.pdf differ diff --git a/hdmi-in-test/docs/rgb2dvi.pdf b/hdmi-in-test/docs/rgb2dvi.pdf new file mode 100644 index 0000000..090ff75 Binary files /dev/null and b/hdmi-in-test/docs/rgb2dvi.pdf differ diff --git a/hdmi-in-test/hdmi-in-test.runs/impl_1/design_1_wrapper.bit b/hdmi-in-test/hdmi-in-test.runs/impl_1/design_1_wrapper.bit new file mode 100644 index 0000000..9ab2a8f Binary files /dev/null and b/hdmi-in-test/hdmi-in-test.runs/impl_1/design_1_wrapper.bit differ diff --git a/hdmi-in-test/hdmi-in-test.srcs/sources_1/bd/design_1/design_1.bd b/hdmi-in-test/hdmi-in-test.srcs/sources_1/bd/design_1/design_1.bd new file mode 100644 index 0000000..608ecd9 --- /dev/null +++ b/hdmi-in-test/hdmi-in-test.srcs/sources_1/bd/design_1/design_1.bd @@ -0,0 +1,4563 @@ +{ + "design": { + "design_info": { + "boundary_crc": "0x2C555445ADF34B05", + "device": "xc7z020clg400-1", + "gen_directory": "../../../../hdmi-in-test.gen/sources_1/bd/design_1", + "name": "design_1", + "rev_ctrl_bd_flag": "RevCtrlBdOff", + "synth_flow_mode": "Hierarchical", + "tool_version": "2021.2", + "validated": "true" + }, + "design_tree": { + "axi_dma_0": "", + "axi_gpio_0": "", + "axi_iic_0": "", + "axi_mem_intercon": { + "xbar": "", + "s00_couplers": {}, + "s01_couplers": {}, + "m00_couplers": { + "auto_pc": "" + } + }, + "processing_system7_0": "", + "processing_system7_0_axi_periph": { + "xbar": "", + "s00_couplers": { + "auto_pc": "" + }, + "m00_couplers": {}, + "m01_couplers": {}, + "m02_couplers": {}, + "m03_couplers": {}, + "m04_couplers": {}, + "m05_couplers": {}, + "m06_couplers": {} + }, + "rst_processing_system7_0_100M": "", + "xlconcat_0": "", + "d_axi_i2s_audio_0": "", + "CONST0": "", + "hier_0": { + "v_tpg_0": "", + "rgb2dvi_0": "", + "CONST1": "", + "v_axi4s_vid_out_0": "", + "v_tc_0": "", + "rst_processing_system7_0_100M1": "" + }, + "hier_1": { + "v_vid_in_axi4s_0": "", + "CONST1": "", + "v_tc_0": "", + "rst_processing_system7_0_100M1": "", + "dvi2rgb_0": "", + "system_ila_0": "" + } + }, + "interface_ports": { + "DDR": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:ddrx:1.0", + "vlnv": "xilinx.com:interface:ddrx_rtl:1.0", + "parameters": { + "AXI_ARBITRATION_SCHEME": { + "value": "TDM", + "value_src": "default" + }, + "BURST_LENGTH": { + "value": "8", + "value_src": "default" + }, + "CAN_DEBUG": { + "value": "false", + "value_src": "default" + }, + "CAS_LATENCY": { + "value": "11", + "value_src": "default" + }, + "CAS_WRITE_LATENCY": { + "value": "11", + "value_src": "default" + }, + "CS_ENABLED": { + "value": "true", + "value_src": "default" + }, + "DATA_MASK_ENABLED": { + "value": "true", + "value_src": "default" + }, + "DATA_WIDTH": { + "value": "8", + "value_src": "default" + }, + "MEMORY_TYPE": { + "value": "COMPONENTS", + "value_src": "default" + }, + "MEM_ADDR_MAP": { + "value": "ROW_COLUMN_BANK", + "value_src": "default" + }, + "SLOT": { + "value": "Single", + "value_src": "default" + }, + "TIMEPERIOD_PS": { + "value": "1250", + "value_src": "default" + } + } + }, + "FIXED_IO": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:display_processing_system7:fixedio:1.0", + "vlnv": "xilinx.com:display_processing_system7:fixedio_rtl:1.0", + "parameters": { + "CAN_DEBUG": { + "value": "false", + "value_src": "default" + } + } + }, + "btns_4bits": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:gpio:1.0", + "vlnv": "xilinx.com:interface:gpio_rtl:1.0" + }, + "iic_rtl": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:iic:1.0", + "vlnv": "xilinx.com:interface:iic_rtl:1.0" + } + }, + "ports": { + "MCLK_O": { + "direction": "O" + }, + "BCLK_O": { + "direction": "O" + }, + "LRCLK_O": { + "direction": "O" + }, + "SDATA_O": { + "direction": "O" + }, + "SDATA_I": { + "direction": "I" + }, + "TMDS_Clk_n_0": { + "type": "clk", + "direction": "O", + "parameters": { + "FREQ_HZ": { + "value": "100000000", + "value_src": "default" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + } + } + }, + "TMDS_Data_p_0": { + "direction": "O", + "left": "2", + "right": "0" + }, + "TMDS_Clk_p_0": { + "type": "clk", + "direction": "O", + "parameters": { + "FREQ_HZ": { + "value": "100000000", + "value_src": "default" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + } + } + }, + "TMDS_Data_n_0": { + "direction": "O", + "left": "2", + "right": "0" + }, + "TMDS_Clk_p_1": { + "type": "clk", + "direction": "I", + "parameters": { + "CLK_DOMAIN": { + "value": "design_1_TMDS_Clk_p_1", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "default" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + } + } + }, + "TMDS_Clk_n_1": { + "type": "clk", + "direction": "I", + "parameters": { + "CLK_DOMAIN": { + "value": "design_1_TMDS_Clk_n_1", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "default" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + } + } + }, + "TMDS_Data_p_1": { + "direction": "I", + "left": "2", + "right": "0" + }, + "TMDS_Data_n_1": { + "direction": "I", + "left": "2", + "right": "0" + }, + "leds_4bits_tri_o_0": { + "direction": "O" + }, + "leds_4bits_tri_o_1": { + "direction": "O" + } + }, + "components": { + "axi_dma_0": { + "vlnv": "xilinx.com:ip:axi_dma:7.1", + "xci_name": "design_1_axi_dma_0_0", + "xci_path": "ip/design_1_axi_dma_0_0/design_1_axi_dma_0_0.xci", + "inst_hier_path": "axi_dma_0", + "parameters": { + "c_include_mm2s_dre": { + "value": "0" + }, + "c_include_s2mm_dre": { + "value": "0" + }, + "c_include_sg": { + "value": "0" + }, + "c_micro_dma": { + "value": "0" + }, + "c_mm2s_burst_size": { + "value": "8" + }, + "c_s2mm_burst_size": { + "value": "8" + }, + "c_sg_length_width": { + "value": "23" + } + }, + "interface_ports": { + "M_AXI_MM2S": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Master", + "address_space_ref": "Data_MM2S", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFF", + "width": "32" + } + }, + "M_AXI_S2MM": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Master", + "address_space_ref": "Data_S2MM", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFF", + "width": "32" + } + } + }, + "addressing": { + "address_spaces": { + "Data_MM2S": { + "range": "4G", + "width": "32" + }, + "Data_S2MM": { + "range": "4G", + "width": "32" + } + } + } + }, + "axi_gpio_0": { + "vlnv": "xilinx.com:ip:axi_gpio:2.0", + "xci_name": "design_1_axi_gpio_0_0", + "xci_path": "ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xci", + "inst_hier_path": "axi_gpio_0", + "parameters": { + "C_INTERRUPT_PRESENT": { + "value": "1" + }, + "GPIO2_BOARD_INTERFACE": { + "value": "Custom" + }, + "GPIO_BOARD_INTERFACE": { + "value": "btns_4bits" + }, + "USE_BOARD_FLOW": { + "value": "true" + } + } + }, + "axi_iic_0": { + "vlnv": "xilinx.com:ip:axi_iic:2.1", + "xci_name": "design_1_axi_iic_0_0", + "xci_path": "ip/design_1_axi_iic_0_0/design_1_axi_iic_0_0.xci", + "inst_hier_path": "axi_iic_0", + "parameters": { + "IIC_BOARD_INTERFACE": { + "value": "audio_i2c" + }, + "USE_BOARD_FLOW": { + "value": "true" + } + } + }, + "axi_mem_intercon": { + "vlnv": "xilinx.com:ip:axi_interconnect:2.1", + "xci_path": "ip/design_1_axi_mem_intercon_0/design_1_axi_mem_intercon_0.xci", + "inst_hier_path": "axi_mem_intercon", + "xci_name": "design_1_axi_mem_intercon_0", + "parameters": { + "NUM_MI": { + "value": "1" + }, + "NUM_SI": { + "value": "2" + }, + "S01_HAS_DATA_FIFO": { + "value": "0" + }, + "S02_HAS_DATA_FIFO": { + "value": "1" + }, + "SYNCHRONIZATION_STAGES": { + "value": "2" + } + }, + "interface_ports": { + "S00_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S01_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M00_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_RESET": { + "value": "ARESETN" + } + } + }, + "ARESETN": { + "type": "rst", + "direction": "I" + }, + "S00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S00_ARESETN" + } + } + }, + "S00_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S01_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S01_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S01_ARESETN" + } + } + }, + "S01_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M00_ARESETN" + } + } + }, + "M00_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "xbar": { + "vlnv": "xilinx.com:ip:axi_crossbar:2.1", + "xci_name": "design_1_xbar_0", + "xci_path": "ip/design_1_xbar_0/design_1_xbar_0.xci", + "inst_hier_path": "axi_mem_intercon/xbar", + "parameters": { + "NUM_MI": { + "value": "1" + }, + "NUM_SI": { + "value": "2" + }, + "STRATEGY": { + "value": "0" + } + }, + "interface_ports": { + "S00_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M00_AXI" + ] + }, + "S01_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M00_AXI" + ] + } + } + }, + "s00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "s00_couplers_to_s00_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "s01_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "s01_couplers_to_s01_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "auto_pc": { + "vlnv": "xilinx.com:ip:axi_protocol_converter:2.1", + "xci_name": "design_1_auto_pc_0", + "xci_path": "ip/design_1_auto_pc_0/design_1_auto_pc_0.xci", + "inst_hier_path": "axi_mem_intercon/m00_couplers/auto_pc", + "parameters": { + "MI_PROTOCOL": { + "value": "AXI3" + }, + "SI_PROTOCOL": { + "value": "AXI4" + } + }, + "interface_ports": { + "S_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "auto_pc_to_m00_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] + }, + "m00_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] + } + }, + "nets": { + "S_ACLK_1": { + "ports": [ + "S_ACLK", + "auto_pc/aclk" + ] + }, + "S_ARESETN_1": { + "ports": [ + "S_ARESETN", + "auto_pc/aresetn" + ] + } + } + } + }, + "interface_nets": { + "axi_mem_intercon_to_s00_couplers": { + "interface_ports": [ + "S00_AXI", + "s00_couplers/S_AXI" + ] + }, + "axi_mem_intercon_to_s01_couplers": { + "interface_ports": [ + "S01_AXI", + "s01_couplers/S_AXI" + ] + }, + "m00_couplers_to_axi_mem_intercon": { + "interface_ports": [ + "M00_AXI", + "m00_couplers/M_AXI" + ] + }, + "s00_couplers_to_xbar": { + "interface_ports": [ + "s00_couplers/M_AXI", + "xbar/S00_AXI" + ] + }, + "s01_couplers_to_xbar": { + "interface_ports": [ + "s01_couplers/M_AXI", + "xbar/S01_AXI" + ] + }, + "xbar_to_m00_couplers": { + "interface_ports": [ + "xbar/M00_AXI", + "m00_couplers/S_AXI" + ] + } + }, + "nets": { + "M00_ACLK_1": { + "ports": [ + "M00_ACLK", + "m00_couplers/M_ACLK" + ] + }, + "M00_ARESETN_1": { + "ports": [ + "M00_ARESETN", + "m00_couplers/M_ARESETN" + ] + }, + "S00_ACLK_1": { + "ports": [ + "S00_ACLK", + "s00_couplers/S_ACLK" + ] + }, + "S00_ARESETN_1": { + "ports": [ + "S00_ARESETN", + "s00_couplers/S_ARESETN" + ] + }, + "S01_ACLK_1": { + "ports": [ + "S01_ACLK", + "s01_couplers/S_ACLK" + ] + }, + "S01_ARESETN_1": { + "ports": [ + "S01_ARESETN", + "s01_couplers/S_ARESETN" + ] + }, + "axi_mem_intercon_ACLK_net": { + "ports": [ + "ACLK", + "xbar/aclk", + "s00_couplers/M_ACLK", + "s01_couplers/M_ACLK", + "m00_couplers/S_ACLK" + ] + }, + "axi_mem_intercon_ARESETN_net": { + "ports": [ + "ARESETN", + "xbar/aresetn", + "s00_couplers/M_ARESETN", + "s01_couplers/M_ARESETN", + "m00_couplers/S_ARESETN" + ] + } + } + }, + "processing_system7_0": { + "vlnv": "xilinx.com:ip:processing_system7:5.5", + "xci_name": "design_1_processing_system7_0_0", + "xci_path": "ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xci", + "inst_hier_path": "processing_system7_0", + "parameters": { + "PCW_ACT_APU_PERIPHERAL_FREQMHZ": { + "value": "650.000000" + }, + "PCW_ACT_CAN0_PERIPHERAL_FREQMHZ": { + "value": "23.8095" + }, + "PCW_ACT_CAN1_PERIPHERAL_FREQMHZ": { + "value": "23.8095" + }, + "PCW_ACT_CAN_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_DCI_PERIPHERAL_FREQMHZ": { + "value": "10.096154" + }, + "PCW_ACT_ENET0_PERIPHERAL_FREQMHZ": { + "value": "125.000000" + }, + "PCW_ACT_ENET1_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": { + "value": "100.000000" + }, + "PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": { + "value": "76.923080" + }, + "PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ": { + "value": "200.000000" + }, + "PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_I2C_PERIPHERAL_FREQMHZ": { + "value": "50" + }, + "PCW_ACT_PCAP_PERIPHERAL_FREQMHZ": { + "value": "200.000000" + }, + "PCW_ACT_QSPI_PERIPHERAL_FREQMHZ": { + "value": "200.000000" + }, + "PCW_ACT_SDIO_PERIPHERAL_FREQMHZ": { + "value": "50.000000" + }, + "PCW_ACT_SMC_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_SPI_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_TPIU_PERIPHERAL_FREQMHZ": { + "value": "200.000000" + }, + "PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ": { + "value": "108.333336" + }, + "PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ": { + "value": "108.333336" + }, + "PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ": { + "value": "108.333336" + }, + "PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ": { + "value": "108.333336" + }, + "PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ": { + "value": "108.333336" + }, + "PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ": { + "value": "108.333336" + }, + "PCW_ACT_TTC_PERIPHERAL_FREQMHZ": { + "value": "50" + }, + "PCW_ACT_UART_PERIPHERAL_FREQMHZ": { + "value": "100.000000" + }, + "PCW_ACT_USB0_PERIPHERAL_FREQMHZ": { + "value": "60" + }, + "PCW_ACT_USB1_PERIPHERAL_FREQMHZ": { + "value": "60" + }, + "PCW_ACT_WDT_PERIPHERAL_FREQMHZ": { + "value": "108.333336" + }, + "PCW_APU_CLK_RATIO_ENABLE": { + "value": "6:2:1" + }, + "PCW_APU_PERIPHERAL_FREQMHZ": { + "value": "650" + }, + "PCW_CAN0_PERIPHERAL_CLKSRC": { + "value": "External" + }, + "PCW_CAN0_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_CAN1_PERIPHERAL_CLKSRC": { + "value": "External" + }, + "PCW_CAN1_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_CAN_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_CAN_PERIPHERAL_VALID": { + "value": "0" + }, + "PCW_CLK0_FREQ": { + "value": "100000000" + }, + "PCW_CLK1_FREQ": { + "value": "76923080" + }, + "PCW_CLK2_FREQ": { + "value": "200000000" + }, + "PCW_CLK3_FREQ": { + "value": "10000000" + }, + "PCW_CORE0_FIQ_INTR": { + "value": "0" + }, + "PCW_CORE0_IRQ_INTR": { + "value": "0" + }, + "PCW_CORE1_FIQ_INTR": { + "value": "0" + }, + "PCW_CORE1_IRQ_INTR": { + "value": "0" + }, + "PCW_CPU_CPU_6X4X_MAX_RANGE": { + "value": "667" + }, + "PCW_CPU_PERIPHERAL_CLKSRC": { + "value": "ARM PLL" + }, + "PCW_CRYSTAL_PERIPHERAL_FREQMHZ": { + "value": "50" + }, + "PCW_DCI_PERIPHERAL_CLKSRC": { + "value": "DDR PLL" + }, + "PCW_DCI_PERIPHERAL_FREQMHZ": { + "value": "10.159" + }, + "PCW_DDR_PERIPHERAL_CLKSRC": { + "value": "DDR PLL" + }, + "PCW_DDR_RAM_BASEADDR": { + "value": "0x00100000" + }, + "PCW_DDR_RAM_HIGHADDR": { + "value": "0x1FFFFFFF" + }, + "PCW_DM_WIDTH": { + "value": "4" + }, + "PCW_DQS_WIDTH": { + "value": "4" + }, + "PCW_DQ_WIDTH": { + "value": "32" + }, + "PCW_ENET0_BASEADDR": { + "value": "0xE000B000" + }, + "PCW_ENET0_ENET0_IO": { + "value": "MIO 16 .. 27" + }, + "PCW_ENET0_GRP_MDIO_ENABLE": { + "value": "1" + }, + "PCW_ENET0_GRP_MDIO_IO": { + "value": "MIO 52 .. 53" + }, + "PCW_ENET0_HIGHADDR": { + "value": "0xE000BFFF" + }, + "PCW_ENET0_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_ENET0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_ENET0_PERIPHERAL_FREQMHZ": { + "value": "1000 Mbps" + }, + "PCW_ENET0_RESET_ENABLE": { + "value": "1" + }, + "PCW_ENET0_RESET_IO": { + "value": "MIO 9" + }, + "PCW_ENET1_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_ENET1_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_ENET_RESET_ENABLE": { + "value": "1" + }, + "PCW_ENET_RESET_POLARITY": { + "value": "Active Low" + }, + "PCW_ENET_RESET_SELECT": { + "value": "Share reset pin" + }, + "PCW_EN_4K_TIMER": { + "value": "0" + }, + "PCW_EN_CAN0": { + "value": "0" + }, + "PCW_EN_CAN1": { + "value": "0" + }, + "PCW_EN_CLK0_PORT": { + "value": "1" + }, + "PCW_EN_CLK1_PORT": { + "value": "1" + }, + "PCW_EN_CLK2_PORT": { + "value": "1" + }, + "PCW_EN_CLK3_PORT": { + "value": "0" + }, + "PCW_EN_CLKTRIG0_PORT": { + "value": "0" + }, + "PCW_EN_CLKTRIG1_PORT": { + "value": "0" + }, + "PCW_EN_CLKTRIG2_PORT": { + "value": "0" + }, + "PCW_EN_CLKTRIG3_PORT": { + "value": "0" + }, + "PCW_EN_DDR": { + "value": "1" + }, + "PCW_EN_EMIO_CAN0": { + "value": "0" + }, + "PCW_EN_EMIO_CAN1": { + "value": "0" + }, + "PCW_EN_EMIO_CD_SDIO0": { + "value": "0" + }, + "PCW_EN_EMIO_CD_SDIO1": { + "value": "0" + }, + "PCW_EN_EMIO_ENET0": { + "value": "0" + }, + "PCW_EN_EMIO_ENET1": { + "value": "0" + }, + "PCW_EN_EMIO_GPIO": { + "value": "0" + }, + "PCW_EN_EMIO_I2C0": { + "value": "0" + }, + "PCW_EN_EMIO_I2C1": { + "value": "0" + }, + "PCW_EN_EMIO_MODEM_UART0": { + "value": "0" + }, + "PCW_EN_EMIO_MODEM_UART1": { + "value": "0" + }, + "PCW_EN_EMIO_PJTAG": { + "value": "0" + }, + "PCW_EN_EMIO_SDIO0": { + "value": "0" + }, + "PCW_EN_EMIO_SDIO1": { + "value": "0" + }, + "PCW_EN_EMIO_SPI0": { + "value": "0" + }, + "PCW_EN_EMIO_SPI1": { + "value": "0" + }, + "PCW_EN_EMIO_SRAM_INT": { + "value": "0" + }, + "PCW_EN_EMIO_TRACE": { + "value": "0" + }, + "PCW_EN_EMIO_TTC0": { + "value": "1" + }, + "PCW_EN_EMIO_TTC1": { + "value": "0" + }, + "PCW_EN_EMIO_UART0": { + "value": "0" + }, + "PCW_EN_EMIO_UART1": { + "value": "0" + }, + "PCW_EN_EMIO_WDT": { + "value": "0" + }, + "PCW_EN_EMIO_WP_SDIO0": { + "value": "0" + }, + "PCW_EN_EMIO_WP_SDIO1": { + "value": "0" + }, + "PCW_EN_ENET0": { + "value": "1" + }, + "PCW_EN_ENET1": { + "value": "0" + }, + "PCW_EN_GPIO": { + "value": "1" + }, + "PCW_EN_I2C0": { + "value": "0" + }, + "PCW_EN_I2C1": { + "value": "0" + }, + "PCW_EN_MODEM_UART0": { + "value": "0" + }, + "PCW_EN_MODEM_UART1": { + "value": "0" + }, + "PCW_EN_PJTAG": { + "value": "0" + }, + "PCW_EN_PTP_ENET0": { + "value": "0" + }, + "PCW_EN_PTP_ENET1": { + "value": "0" + }, + "PCW_EN_QSPI": { + "value": "1" + }, + "PCW_EN_RST0_PORT": { + "value": "1" + }, + "PCW_EN_RST1_PORT": { + "value": "0" + }, + "PCW_EN_RST2_PORT": { + "value": "0" + }, + "PCW_EN_RST3_PORT": { + "value": "0" + }, + "PCW_EN_SDIO0": { + "value": "1" + }, + "PCW_EN_SDIO1": { + "value": "0" + }, + "PCW_EN_SMC": { + "value": "0" + }, + "PCW_EN_SPI0": { + "value": "0" + }, + "PCW_EN_SPI1": { + "value": "0" + }, + "PCW_EN_TRACE": { + "value": "0" + }, + "PCW_EN_TTC0": { + "value": "1" + }, + "PCW_EN_TTC1": { + "value": "0" + }, + "PCW_EN_UART0": { + "value": "1" + }, + "PCW_EN_UART1": { + "value": "0" + }, + "PCW_EN_USB0": { + "value": "1" + }, + "PCW_EN_USB1": { + "value": "0" + }, + "PCW_EN_WDT": { + "value": "0" + }, + "PCW_FCLK0_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_FCLK1_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_FCLK2_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_FCLK3_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_FCLK_CLK0_BUF": { + "value": "TRUE" + }, + "PCW_FCLK_CLK1_BUF": { + "value": "FALSE" + }, + "PCW_FCLK_CLK2_BUF": { + "value": "TRUE" + }, + "PCW_FPGA0_PERIPHERAL_FREQMHZ": { + "value": "100" + }, + "PCW_FPGA1_PERIPHERAL_FREQMHZ": { + "value": "74.250" + }, + "PCW_FPGA2_PERIPHERAL_FREQMHZ": { + "value": "200" + }, + "PCW_FPGA3_PERIPHERAL_FREQMHZ": { + "value": "50" + }, + "PCW_FPGA_FCLK0_ENABLE": { + "value": "1" + }, + "PCW_FPGA_FCLK1_ENABLE": { + "value": "1" + }, + "PCW_FPGA_FCLK2_ENABLE": { + "value": "1" + }, + "PCW_GP0_EN_MODIFIABLE_TXN": { + "value": "0" + }, + "PCW_GP0_NUM_READ_THREADS": { + "value": "4" + }, + "PCW_GP0_NUM_WRITE_THREADS": { + "value": "4" + }, + "PCW_GP1_EN_MODIFIABLE_TXN": { + "value": "0" + }, + "PCW_GP1_NUM_READ_THREADS": { + "value": "4" + }, + "PCW_GP1_NUM_WRITE_THREADS": { + "value": "4" + }, + "PCW_GPIO_BASEADDR": { + "value": "0xE000A000" + }, + "PCW_GPIO_EMIO_GPIO_ENABLE": { + "value": "0" + }, + "PCW_GPIO_HIGHADDR": { + "value": "0xE000AFFF" + }, + "PCW_GPIO_MIO_GPIO_ENABLE": { + "value": "1" + }, + "PCW_GPIO_MIO_GPIO_IO": { + "value": "MIO" + }, + "PCW_GPIO_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_I2C0_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_I2C1_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_I2C_RESET_ENABLE": { + "value": "1" + }, + "PCW_I2C_RESET_POLARITY": { + "value": "Active Low" + }, + "PCW_IMPORT_BOARD_PRESET": { + "value": "None" + }, + "PCW_INCLUDE_ACP_TRANS_CHECK": { + "value": "0" + }, + "PCW_IRQ_F2P_INTR": { + "value": "1" + }, + "PCW_IRQ_F2P_MODE": { + "value": "DIRECT" + }, + "PCW_MIO_0_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_0_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_0_SLEW": { + "value": "slow" + }, + "PCW_MIO_10_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_10_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_10_SLEW": { + "value": "slow" + }, + "PCW_MIO_11_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_11_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_11_SLEW": { + "value": "slow" + }, + "PCW_MIO_12_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_12_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_12_SLEW": { + "value": "slow" + }, + "PCW_MIO_13_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_13_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_13_SLEW": { + "value": "slow" + }, + "PCW_MIO_14_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_14_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_14_SLEW": { + "value": "slow" + }, + "PCW_MIO_15_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_15_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_15_SLEW": { + "value": "slow" + }, + "PCW_MIO_16_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_16_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_16_SLEW": { + "value": "slow" + }, + "PCW_MIO_17_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_17_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_17_SLEW": { + "value": "slow" + }, + "PCW_MIO_18_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_18_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_18_SLEW": { + "value": "slow" + }, + "PCW_MIO_19_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_19_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_19_SLEW": { + "value": "slow" + }, + "PCW_MIO_1_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_1_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_1_SLEW": { + "value": "slow" + }, + "PCW_MIO_20_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_20_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_20_SLEW": { + "value": "slow" + }, + "PCW_MIO_21_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_21_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_21_SLEW": { + "value": "slow" + }, + "PCW_MIO_22_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_22_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_22_SLEW": { + "value": "slow" + }, + "PCW_MIO_23_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_23_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_23_SLEW": { + "value": "slow" + }, + "PCW_MIO_24_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_24_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_24_SLEW": { + "value": "slow" + }, + "PCW_MIO_25_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_25_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_25_SLEW": { + "value": "slow" + }, + "PCW_MIO_26_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_26_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_26_SLEW": { + "value": "slow" + }, + "PCW_MIO_27_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_27_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_27_SLEW": { + "value": "slow" + }, + "PCW_MIO_28_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_28_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_28_SLEW": { + "value": "slow" + }, + "PCW_MIO_29_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_29_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_29_SLEW": { + "value": "slow" + }, + "PCW_MIO_2_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_2_SLEW": { + "value": "slow" + }, + "PCW_MIO_30_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_30_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_30_SLEW": { + "value": "slow" + }, + "PCW_MIO_31_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_31_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_31_SLEW": { + "value": "slow" + }, + "PCW_MIO_32_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_32_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_32_SLEW": { + "value": "slow" + }, + "PCW_MIO_33_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_33_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_33_SLEW": { + "value": "slow" + }, + "PCW_MIO_34_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_34_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_34_SLEW": { + "value": "slow" + }, + "PCW_MIO_35_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_35_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_35_SLEW": { + "value": "slow" + }, + "PCW_MIO_36_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_36_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_36_SLEW": { + "value": "slow" + }, + "PCW_MIO_37_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_37_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_37_SLEW": { + "value": "slow" + }, + "PCW_MIO_38_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_38_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_38_SLEW": { + "value": "slow" + }, + "PCW_MIO_39_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_39_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_39_SLEW": { + "value": "slow" + }, + "PCW_MIO_3_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_3_SLEW": { + "value": "slow" + }, + "PCW_MIO_40_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_40_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_40_SLEW": { + "value": "slow" + }, + "PCW_MIO_41_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_41_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_41_SLEW": { + "value": "slow" + }, + "PCW_MIO_42_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_42_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_42_SLEW": { + "value": "slow" + }, + "PCW_MIO_43_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_43_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_43_SLEW": { + "value": "slow" + }, + "PCW_MIO_44_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_44_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_44_SLEW": { + "value": "slow" + }, + "PCW_MIO_45_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_45_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_45_SLEW": { + "value": "slow" + }, + "PCW_MIO_46_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_46_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_46_SLEW": { + "value": "slow" + }, + "PCW_MIO_47_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_47_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_47_SLEW": { + "value": "slow" + }, + "PCW_MIO_48_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_48_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_48_SLEW": { + "value": "slow" + }, + "PCW_MIO_49_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_49_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_49_SLEW": { + "value": "slow" + }, + "PCW_MIO_4_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_4_SLEW": { + "value": "slow" + }, + "PCW_MIO_50_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_50_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_50_SLEW": { + "value": "slow" + }, + "PCW_MIO_51_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_51_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_51_SLEW": { + "value": "slow" + }, + "PCW_MIO_52_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_52_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_52_SLEW": { + "value": "slow" + }, + "PCW_MIO_53_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_53_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_53_SLEW": { + "value": "slow" + }, + "PCW_MIO_5_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_5_SLEW": { + "value": "slow" + }, + "PCW_MIO_6_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_6_SLEW": { + "value": "slow" + }, + "PCW_MIO_7_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_7_SLEW": { + "value": "slow" + }, + "PCW_MIO_8_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_8_SLEW": { + "value": "slow" + }, + "PCW_MIO_9_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_9_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_9_SLEW": { + "value": "slow" + }, + "PCW_MIO_PRIMITIVE": { + "value": "54" + }, + "PCW_MIO_TREE_PERIPHERALS": { + "value": "GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#ENET Reset#GPIO#GPIO#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0" + }, + "PCW_MIO_TREE_SIGNALS": { + "value": "gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#reset#gpio[10]#gpio[11]#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#gpio[48]#gpio[49]#gpio[50]#gpio[51]#mdc#mdio" + }, + "PCW_M_AXI_GP0_ENABLE_STATIC_REMAP": { + "value": "0" + }, + "PCW_M_AXI_GP0_ID_WIDTH": { + "value": "12" + }, + "PCW_M_AXI_GP0_SUPPORT_NARROW_BURST": { + "value": "0" + }, + "PCW_M_AXI_GP0_THREAD_ID_WIDTH": { + "value": "12" + }, + "PCW_NAND_CYCLES_T_AR": { + "value": "1" + }, + "PCW_NAND_CYCLES_T_CLR": { + "value": "1" + }, + "PCW_NAND_CYCLES_T_RC": { + "value": "11" + }, + "PCW_NAND_CYCLES_T_REA": { + "value": "1" + }, + "PCW_NAND_CYCLES_T_RR": { + "value": "1" + }, + "PCW_NAND_CYCLES_T_WC": { + "value": "11" + }, + "PCW_NAND_CYCLES_T_WP": { + "value": "1" + }, + "PCW_NOR_CS0_T_CEOE": { + "value": "1" + }, + "PCW_NOR_CS0_T_PC": { + "value": "1" + }, + "PCW_NOR_CS0_T_RC": { + "value": "11" + }, + "PCW_NOR_CS0_T_TR": { + "value": "1" + }, + "PCW_NOR_CS0_T_WC": { + "value": "11" + }, + "PCW_NOR_CS0_T_WP": { + "value": "1" + }, + "PCW_NOR_CS0_WE_TIME": { + "value": "0" + }, + "PCW_NOR_CS1_T_CEOE": { + "value": "1" + }, + "PCW_NOR_CS1_T_PC": { + "value": "1" + }, + "PCW_NOR_CS1_T_RC": { + "value": "11" + }, + "PCW_NOR_CS1_T_TR": { + "value": "1" + }, + "PCW_NOR_CS1_T_WC": { + "value": "11" + }, + "PCW_NOR_CS1_T_WP": { + "value": "1" + }, + "PCW_NOR_CS1_WE_TIME": { + "value": "0" + }, + "PCW_NOR_SRAM_CS0_T_CEOE": { + "value": "1" + }, + "PCW_NOR_SRAM_CS0_T_PC": { + "value": "1" + }, + "PCW_NOR_SRAM_CS0_T_RC": { + "value": "11" + }, + "PCW_NOR_SRAM_CS0_T_TR": { + "value": "1" + }, + "PCW_NOR_SRAM_CS0_T_WC": { + "value": "11" + }, + "PCW_NOR_SRAM_CS0_T_WP": { + "value": "1" + }, + "PCW_NOR_SRAM_CS0_WE_TIME": { + "value": "0" + }, + "PCW_NOR_SRAM_CS1_T_CEOE": { + "value": "1" + }, + "PCW_NOR_SRAM_CS1_T_PC": { + "value": "1" + }, + "PCW_NOR_SRAM_CS1_T_RC": { + "value": "11" + }, + "PCW_NOR_SRAM_CS1_T_TR": { + "value": "1" + }, + "PCW_NOR_SRAM_CS1_T_WC": { + "value": "11" + }, + "PCW_NOR_SRAM_CS1_T_WP": { + "value": "1" + }, + "PCW_NOR_SRAM_CS1_WE_TIME": { + "value": "0" + }, + "PCW_OVERRIDE_BASIC_CLOCK": { + "value": "0" + }, + "PCW_P2F_ENET0_INTR": { + "value": "0" + }, + "PCW_P2F_GPIO_INTR": { + "value": "0" + }, + "PCW_P2F_QSPI_INTR": { + "value": "0" + }, + "PCW_P2F_SDIO0_INTR": { + "value": "0" + }, + "PCW_P2F_UART0_INTR": { + "value": "0" + }, + "PCW_P2F_USB0_INTR": { + "value": "0" + }, + "PCW_PACKAGE_DDR_BOARD_DELAY0": { + "value": "0.279" + }, + "PCW_PACKAGE_DDR_BOARD_DELAY1": { + "value": "0.260" + }, + "PCW_PACKAGE_DDR_BOARD_DELAY2": { + "value": "0.085" + }, + "PCW_PACKAGE_DDR_BOARD_DELAY3": { + "value": "0.092" + }, + "PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0": { + "value": "-0.051" + }, + "PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1": { + "value": "-0.006" + }, + "PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2": { + "value": "-0.009" + }, + "PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3": { + "value": "-0.033" + }, + "PCW_PACKAGE_NAME": { + "value": "clg400" + }, + "PCW_PCAP_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_PCAP_PERIPHERAL_FREQMHZ": { + "value": "200" + }, + "PCW_PERIPHERAL_BOARD_PRESET": { + "value": "part0" + }, + "PCW_PJTAG_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_PLL_BYPASSMODE_ENABLE": { + "value": "0" + }, + "PCW_PRESET_BANK0_VOLTAGE": { + "value": "LVCMOS 3.3V" + }, + "PCW_PRESET_BANK1_VOLTAGE": { + "value": "LVCMOS 1.8V" + }, + "PCW_PS7_SI_REV": { + "value": "PRODUCTION" + }, + "PCW_QSPI_GRP_FBCLK_ENABLE": { + "value": "1" + }, + "PCW_QSPI_GRP_FBCLK_IO": { + "value": "MIO 8" + }, + "PCW_QSPI_GRP_IO1_ENABLE": { + "value": "0" + }, + "PCW_QSPI_GRP_SINGLE_SS_ENABLE": { + "value": "1" + }, + "PCW_QSPI_GRP_SINGLE_SS_IO": { + "value": "MIO 1 .. 6" + }, + "PCW_QSPI_GRP_SS1_ENABLE": { + "value": "0" + }, + "PCW_QSPI_INTERNAL_HIGHADDRESS": { + "value": "0xFCFFFFFF" + }, + "PCW_QSPI_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_QSPI_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_QSPI_PERIPHERAL_FREQMHZ": { + "value": "200" + }, + "PCW_QSPI_QSPI_IO": { + "value": "MIO 1 .. 6" + }, + "PCW_SD0_GRP_CD_ENABLE": { + "value": "1" + }, + "PCW_SD0_GRP_CD_IO": { + "value": "MIO 47" + }, + "PCW_SD0_GRP_POW_ENABLE": { + "value": "0" + }, + "PCW_SD0_GRP_WP_ENABLE": { + "value": "0" + }, + "PCW_SD0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_SD0_SD0_IO": { + "value": "MIO 40 .. 45" + }, + "PCW_SD1_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_SDIO0_BASEADDR": { + "value": "0xE0100000" + }, + "PCW_SDIO0_HIGHADDR": { + "value": "0xE0100FFF" + }, + "PCW_SDIO_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_SDIO_PERIPHERAL_FREQMHZ": { + "value": "50" + }, + "PCW_SDIO_PERIPHERAL_VALID": { + "value": "1" + }, + "PCW_SINGLE_QSPI_DATA_MODE": { + "value": "x4" + }, + "PCW_SMC_CYCLE_T0": { + "value": "NA" + }, + "PCW_SMC_CYCLE_T1": { + "value": "NA" + }, + "PCW_SMC_CYCLE_T2": { + "value": "NA" + }, + "PCW_SMC_CYCLE_T3": { + "value": "NA" + }, + "PCW_SMC_CYCLE_T4": { + "value": "NA" + }, + "PCW_SMC_CYCLE_T5": { + "value": "NA" + }, + "PCW_SMC_CYCLE_T6": { + "value": "NA" + }, + "PCW_SMC_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_SMC_PERIPHERAL_VALID": { + "value": "0" + }, + "PCW_SPI0_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_SPI1_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_SPI_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_SPI_PERIPHERAL_VALID": { + "value": "0" + }, + "PCW_S_AXI_HP0_DATA_WIDTH": { + "value": "32" + }, + "PCW_S_AXI_HP0_ID_WIDTH": { + "value": "6" + }, + "PCW_S_AXI_HP1_DATA_WIDTH": { + "value": "64" + }, + "PCW_S_AXI_HP2_DATA_WIDTH": { + "value": "64" + }, + "PCW_S_AXI_HP3_DATA_WIDTH": { + "value": "64" + }, + "PCW_TPIU_PERIPHERAL_CLKSRC": { + "value": "External" + }, + "PCW_TRACE_INTERNAL_WIDTH": { + "value": "2" + }, + "PCW_TRACE_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_TTC0_BASEADDR": { + "value": "0xE0104000" + }, + "PCW_TTC0_CLK0_PERIPHERAL_CLKSRC": { + "value": "CPU_1X" + }, + "PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0": { + "value": "1" + }, + "PCW_TTC0_CLK1_PERIPHERAL_CLKSRC": { + "value": "CPU_1X" + }, + "PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0": { + "value": "1" + }, + "PCW_TTC0_CLK2_PERIPHERAL_CLKSRC": { + "value": "CPU_1X" + }, + "PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0": { + "value": "1" + }, + "PCW_TTC0_HIGHADDR": { + "value": "0xE0104fff" + }, + "PCW_TTC0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_TTC0_TTC0_IO": { + "value": "EMIO" + }, + "PCW_TTC1_CLK0_PERIPHERAL_CLKSRC": { + "value": "CPU_1X" + }, + "PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0": { + "value": "1" + }, + "PCW_TTC1_CLK1_PERIPHERAL_CLKSRC": { + "value": "CPU_1X" + }, + "PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0": { + "value": "1" + }, + "PCW_TTC1_CLK2_PERIPHERAL_CLKSRC": { + "value": "CPU_1X" + }, + "PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0": { + "value": "1" + }, + "PCW_TTC1_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_TTC_PERIPHERAL_FREQMHZ": { + "value": "50" + }, + "PCW_UART0_BASEADDR": { + "value": "0xE0000000" + }, + "PCW_UART0_BAUD_RATE": { + "value": "115200" + }, + "PCW_UART0_GRP_FULL_ENABLE": { + "value": "0" + }, + "PCW_UART0_HIGHADDR": { + "value": "0xE0000FFF" + }, + "PCW_UART0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_UART0_UART0_IO": { + "value": "MIO 14 .. 15" + }, + "PCW_UART1_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_UART_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_UART_PERIPHERAL_FREQMHZ": { + "value": "100" + }, + "PCW_UART_PERIPHERAL_VALID": { + "value": "1" + }, + "PCW_UIPARAM_ACT_DDR_FREQ_MHZ": { + "value": "525.000000" + }, + "PCW_UIPARAM_DDR_ADV_ENABLE": { + "value": "0" + }, + "PCW_UIPARAM_DDR_AL": { + "value": "0" + }, + "PCW_UIPARAM_DDR_BL": { + "value": "8" + }, + "PCW_UIPARAM_DDR_BOARD_DELAY0": { + "value": "0.279" + }, + "PCW_UIPARAM_DDR_BOARD_DELAY1": { + "value": "0.260" + }, + "PCW_UIPARAM_DDR_BOARD_DELAY2": { + "value": "0.085" + }, + "PCW_UIPARAM_DDR_BOARD_DELAY3": { + "value": "0.092" + }, + "PCW_UIPARAM_DDR_BUS_WIDTH": { + "value": "16 Bit" + }, + "PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM": { + "value": "27.95" + }, + "PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH": { + "value": "80.4535" + }, + "PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM": { + "value": "27.95" + }, + "PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH": { + "value": "80.4535" + }, + "PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM": { + "value": "0" + }, + "PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH": { + "value": "80.4535" + }, + "PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM": { + "value": "0" + }, + "PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH": { + "value": "80.4535" + }, + "PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_CLOCK_STOP_EN": { + "value": "0" + }, + "PCW_UIPARAM_DDR_DQS_0_LENGTH_MM": { + "value": "32.14" + }, + "PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH": { + "value": "105.056" + }, + "PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQS_1_LENGTH_MM": { + "value": "31.12" + }, + "PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH": { + "value": "66.904" + }, + "PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQS_2_LENGTH_MM": { + "value": "0" + }, + "PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH": { + "value": "89.1715" + }, + "PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQS_3_LENGTH_MM": { + "value": "0" + }, + "PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH": { + "value": "113.63" + }, + "PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0": { + "value": "-0.051" + }, + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1": { + "value": "-0.006" + }, + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2": { + "value": "-0.009" + }, + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3": { + "value": "-0.033" + }, + "PCW_UIPARAM_DDR_DQ_0_LENGTH_MM": { + "value": "32.2" + }, + "PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH": { + "value": "98.503" + }, + "PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQ_1_LENGTH_MM": { + "value": "31.08" + }, + "PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH": { + "value": "68.5855" + }, + "PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQ_2_LENGTH_MM": { + "value": "0" + }, + "PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH": { + "value": "90.295" + }, + "PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQ_3_LENGTH_MM": { + "value": "0" + }, + "PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH": { + "value": "103.977" + }, + "PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_ECC": { + "value": "Disabled" + }, + "PCW_UIPARAM_DDR_ENABLE": { + "value": "1" + }, + "PCW_UIPARAM_DDR_FREQ_MHZ": { + "value": "525" + }, + "PCW_UIPARAM_DDR_HIGH_TEMP": { + "value": "Normal (0-85)" + }, + "PCW_UIPARAM_DDR_MEMORY_TYPE": { + "value": "DDR 3" + }, + "PCW_UIPARAM_DDR_PARTNO": { + "value": "MT41J256M16 RE-125" + }, + "PCW_UIPARAM_DDR_TRAIN_DATA_EYE": { + "value": "1" + }, + "PCW_UIPARAM_DDR_TRAIN_READ_GATE": { + "value": "1" + }, + "PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL": { + "value": "1" + }, + "PCW_UIPARAM_DDR_USE_INTERNAL_VREF": { + "value": "0" + }, + "PCW_UIPARAM_GENERATE_SUMMARY": { + "value": "NA" + }, + "PCW_USB0_BASEADDR": { + "value": "0xE0102000" + }, + "PCW_USB0_HIGHADDR": { + "value": "0xE0102fff" + }, + "PCW_USB0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_USB0_RESET_ENABLE": { + "value": "1" + }, + "PCW_USB0_RESET_IO": { + "value": "MIO 46" + }, + "PCW_USB0_USB0_IO": { + "value": "MIO 28 .. 39" + }, + "PCW_USB1_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_USB_RESET_ENABLE": { + "value": "1" + }, + "PCW_USB_RESET_POLARITY": { + "value": "Active Low" + }, + "PCW_USB_RESET_SELECT": { + "value": "Share reset pin" + }, + "PCW_USE_AXI_FABRIC_IDLE": { + "value": "0" + }, + "PCW_USE_AXI_NONSECURE": { + "value": "0" + }, + "PCW_USE_CORESIGHT": { + "value": "0" + }, + "PCW_USE_CROSS_TRIGGER": { + "value": "0" + }, + "PCW_USE_CR_FABRIC": { + "value": "1" + }, + "PCW_USE_DDR_BYPASS": { + "value": "0" + }, + "PCW_USE_DEBUG": { + "value": "0" + }, + "PCW_USE_DMA0": { + "value": "0" + }, + "PCW_USE_DMA1": { + "value": "0" + }, + "PCW_USE_DMA2": { + "value": "0" + }, + "PCW_USE_DMA3": { + "value": "0" + }, + "PCW_USE_EXPANDED_IOP": { + "value": "0" + }, + "PCW_USE_FABRIC_INTERRUPT": { + "value": "1" + }, + "PCW_USE_HIGH_OCM": { + "value": "0" + }, + "PCW_USE_M_AXI_GP0": { + "value": "1" + }, + "PCW_USE_M_AXI_GP1": { + "value": "0" + }, + "PCW_USE_PROC_EVENT_BUS": { + "value": "0" + }, + "PCW_USE_PS_SLCR_REGISTERS": { + "value": "0" + }, + "PCW_USE_S_AXI_ACP": { + "value": "0" + }, + "PCW_USE_S_AXI_GP0": { + "value": "0" + }, + "PCW_USE_S_AXI_GP1": { + "value": "0" + }, + "PCW_USE_S_AXI_HP0": { + "value": "1" + }, + "PCW_USE_S_AXI_HP1": { + "value": "0" + }, + "PCW_USE_S_AXI_HP2": { + "value": "0" + }, + "PCW_USE_S_AXI_HP3": { + "value": "0" + }, + "PCW_USE_TRACE": { + "value": "0" + }, + "PCW_VALUE_SILVERSION": { + "value": "3" + }, + "PCW_WDT_PERIPHERAL_CLKSRC": { + "value": "CPU_1X" + }, + "PCW_WDT_PERIPHERAL_DIVISOR0": { + "value": "1" + }, + "PCW_WDT_PERIPHERAL_ENABLE": { + "value": "0" + }, + "preset": { + "value": "ZedBoard" + } + }, + "interface_ports": { + "M_AXI_GP0": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Master", + "address_space_ref": "Data", + "base_address": { + "minimum": "0x40000000", + "maximum": "0x7FFFFFFF", + "width": "32" + } + }, + "S_AXI_HP0": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "memory_map_ref": "S_AXI_HP0" + } + }, + "addressing": { + "address_spaces": { + "Data": { + "range": "4G", + "width": "32", + "local_memory_map": { + "name": "Data", + "description": "Address Space Segments", + "address_blocks": { + "segment1": { + "name": "segment1", + "display_name": "segment1", + "base_address": "0x00000000", + "range": "256K", + "width": "18", + "usage": "register" + }, + "segment2": { + "name": "segment2", + "display_name": "segment2", + "base_address": "0x00040000", + "range": "256K", + "width": "19", + "usage": "register" + }, + "segment3": { + "name": "segment3", + "display_name": "segment3", + "base_address": "0x00080000", + "range": "512K", + "width": "20", + "usage": "register" + }, + "segment4": { + "name": "segment4", + "display_name": "segment4", + "base_address": "0x00100000", + "range": "1023M", + "width": "30", + "usage": "register" + }, + "M_AXI_GP0": { + "name": "M_AXI_GP0", + "display_name": "M_AXI_GP0", + "base_address": "0x40000000", + "range": "1G", + "width": "31", + "usage": "register" + }, + "M_AXI_GP1": { + "name": "M_AXI_GP1", + "display_name": "M_AXI_GP1", + "base_address": "0x80000000", + "range": "1G", + "width": "32", + "usage": "register" + }, + "IO_Peripheral_Registers": { + "name": "IO_Peripheral_Registers", + "display_name": "IO Peripheral Registers", + "base_address": "0xE0000000", + "range": "3M", + "width": "32", + "usage": "register" + }, + "SMC_Memories": { + "name": "SMC_Memories", + "display_name": "SMC Memories", + "base_address": "0xE1000000", + "range": "80M", + "width": "32", + "usage": "register" + }, + "SLCR_Registers": { + "name": "SLCR_Registers", + "display_name": "SLCR Registers", + "base_address": "0xF8000000", + "range": "3K", + "width": "32", + "usage": "register" + }, + "PS_System_Registers": { + "name": "PS_System_Registers", + "display_name": "PS System Registers", + "base_address": "0xF8001000", + "range": "8252K", + "width": "32", + "usage": "register" + }, + "CPU_Private_Registers": { + "name": "CPU_Private_Registers", + "display_name": "CPU Private Registers", + "base_address": "0xF8900000", + "range": "6156K", + "width": "32", + "usage": "register" + }, + "segment5": { + "name": "segment5", + "display_name": "segment5", + "base_address": "0xFC000000", + "range": "32M", + "width": "32", + "usage": "register" + }, + "segment6": { + "name": "segment6", + "display_name": "segment6", + "base_address": "0xFFFC0000", + "range": "256K", + "width": "32", + "usage": "register" + } + } + } + } + } + } + }, + "processing_system7_0_axi_periph": { + "vlnv": "xilinx.com:ip:axi_interconnect:2.1", + "xci_path": "ip/design_1_processing_system7_0_axi_periph_0/design_1_processing_system7_0_axi_periph_0.xci", + "inst_hier_path": "processing_system7_0_axi_periph", + "xci_name": "design_1_processing_system7_0_axi_periph_0", + "parameters": { + "NUM_MI": { + "value": "7" + }, + "SYNCHRONIZATION_STAGES": { + "value": "2" + } + }, + "interface_ports": { + "S00_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M00_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M01_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M02_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M03_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M04_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M05_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M06_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_RESET": { + "value": "ARESETN" + } + } + }, + "ARESETN": { + "type": "rst", + "direction": "I" + }, + "S00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S00_ARESETN" + } + } + }, + "S00_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M00_ARESETN" + } + } + }, + "M00_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M01_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M01_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M01_ARESETN" + } + } + }, + "M01_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M02_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M02_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M02_ARESETN" + } + } + }, + "M02_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M03_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M03_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M03_ARESETN" + } + } + }, + "M03_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M04_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M04_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M04_ARESETN" + } + } + }, + "M04_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M05_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M05_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M05_ARESETN" + } + } + }, + "M05_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M06_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M06_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M06_ARESETN" + } + } + }, + "M06_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "xbar": { + "vlnv": "xilinx.com:ip:axi_crossbar:2.1", + "xci_name": "design_1_xbar_1", + "xci_path": "ip/design_1_xbar_1/design_1_xbar_1.xci", + "inst_hier_path": "processing_system7_0_axi_periph/xbar", + "parameters": { + "NUM_MI": { + "value": "7" + }, + "NUM_SI": { + "value": "1" + }, + "STRATEGY": { + "value": "0" + } + }, + "interface_ports": { + "S00_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M00_AXI", + "M01_AXI", + "M02_AXI", + "M03_AXI", + "M04_AXI", + "M05_AXI", + "M06_AXI" + ] + } + } + }, + "s00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "auto_pc": { + "vlnv": "xilinx.com:ip:axi_protocol_converter:2.1", + "xci_name": "design_1_auto_pc_1", + "xci_path": "ip/design_1_auto_pc_1/design_1_auto_pc_1.xci", + "inst_hier_path": "processing_system7_0_axi_periph/s00_couplers/auto_pc", + "parameters": { + "MI_PROTOCOL": { + "value": "AXI4LITE" + }, + "SI_PROTOCOL": { + "value": "AXI3" + } + }, + "interface_ports": { + "S_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "auto_pc_to_s00_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] + }, + "s00_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] + } + }, + "nets": { + "S_ACLK_1": { + "ports": [ + "S_ACLK", + "auto_pc/aclk" + ] + }, + "S_ARESETN_1": { + "ports": [ + "S_ARESETN", + "auto_pc/aresetn" + ] + } + } + }, + "m00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m00_couplers_to_m00_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m01_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m01_couplers_to_m01_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m02_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m02_couplers_to_m02_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m03_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m03_couplers_to_m03_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m04_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m04_couplers_to_m04_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m05_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m05_couplers_to_m05_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m06_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m06_couplers_to_m06_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "m00_couplers_to_processing_system7_0_axi_periph": { + "interface_ports": [ + "M00_AXI", + "m00_couplers/M_AXI" + ] + }, + "m01_couplers_to_processing_system7_0_axi_periph": { + "interface_ports": [ + "M01_AXI", + "m01_couplers/M_AXI" + ] + }, + "m02_couplers_to_processing_system7_0_axi_periph": { + "interface_ports": [ + "M02_AXI", + "m02_couplers/M_AXI" + ] + }, + "m03_couplers_to_processing_system7_0_axi_periph": { + "interface_ports": [ + "M03_AXI", + "m03_couplers/M_AXI" + ] + }, + "m04_couplers_to_processing_system7_0_axi_periph": { + "interface_ports": [ + "M04_AXI", + "m04_couplers/M_AXI" + ] + }, + "m05_couplers_to_processing_system7_0_axi_periph": { + "interface_ports": [ + "M05_AXI", + "m05_couplers/M_AXI" + ] + }, + "m06_couplers_to_processing_system7_0_axi_periph": { + "interface_ports": [ + "M06_AXI", + "m06_couplers/M_AXI" + ] + }, + "processing_system7_0_axi_periph_to_s00_couplers": { + "interface_ports": [ + "S00_AXI", + "s00_couplers/S_AXI" + ] + }, + "s00_couplers_to_xbar": { + "interface_ports": [ + "s00_couplers/M_AXI", + "xbar/S00_AXI" + ] + }, + "xbar_to_m00_couplers": { + "interface_ports": [ + "xbar/M00_AXI", + "m00_couplers/S_AXI" + ] + }, + "xbar_to_m01_couplers": { + "interface_ports": [ + "xbar/M01_AXI", + "m01_couplers/S_AXI" + ] + }, + "xbar_to_m02_couplers": { + "interface_ports": [ + "xbar/M02_AXI", + "m02_couplers/S_AXI" + ] + }, + "xbar_to_m03_couplers": { + "interface_ports": [ + "xbar/M03_AXI", + "m03_couplers/S_AXI" + ] + }, + "xbar_to_m04_couplers": { + "interface_ports": [ + "xbar/M04_AXI", + "m04_couplers/S_AXI" + ] + }, + "xbar_to_m05_couplers": { + "interface_ports": [ + "xbar/M05_AXI", + "m05_couplers/S_AXI" + ] + }, + "xbar_to_m06_couplers": { + "interface_ports": [ + "xbar/M06_AXI", + "m06_couplers/S_AXI" + ] + } + }, + "nets": { + "M00_ACLK_1": { + "ports": [ + "M00_ACLK", + "m00_couplers/M_ACLK" + ] + }, + "M00_ARESETN_1": { + "ports": [ + "M00_ARESETN", + "m00_couplers/M_ARESETN" + ] + }, + "M01_ACLK_1": { + "ports": [ + "M01_ACLK", + "m01_couplers/M_ACLK" + ] + }, + "M01_ARESETN_1": { + "ports": [ + "M01_ARESETN", + "m01_couplers/M_ARESETN" + ] + }, + "M02_ACLK_1": { + "ports": [ + "M02_ACLK", + "m02_couplers/M_ACLK" + ] + }, + "M02_ARESETN_1": { + "ports": [ + "M02_ARESETN", + "m02_couplers/M_ARESETN" + ] + }, + "M03_ACLK_1": { + "ports": [ + "M03_ACLK", + "m03_couplers/M_ACLK" + ] + }, + "M03_ARESETN_1": { + "ports": [ + "M03_ARESETN", + "m03_couplers/M_ARESETN" + ] + }, + "M04_ACLK_1": { + "ports": [ + "M04_ACLK", + "m04_couplers/M_ACLK" + ] + }, + "M04_ARESETN_1": { + "ports": [ + "M04_ARESETN", + "m04_couplers/M_ARESETN" + ] + }, + "M05_ACLK_1": { + "ports": [ + "M05_ACLK", + "m05_couplers/M_ACLK" + ] + }, + "M05_ARESETN_1": { + "ports": [ + "M05_ARESETN", + "m05_couplers/M_ARESETN" + ] + }, + "M06_ACLK_1": { + "ports": [ + "M06_ACLK", + "m06_couplers/M_ACLK" + ] + }, + "M06_ARESETN_1": { + "ports": [ + "M06_ARESETN", + "m06_couplers/M_ARESETN" + ] + }, + "S00_ACLK_1": { + "ports": [ + "S00_ACLK", + "s00_couplers/S_ACLK" + ] + }, + "S00_ARESETN_1": { + "ports": [ + "S00_ARESETN", + "s00_couplers/S_ARESETN" + ] + }, + "processing_system7_0_axi_periph_ACLK_net": { + "ports": [ + "ACLK", + "xbar/aclk", + "s00_couplers/M_ACLK", + "m00_couplers/S_ACLK", + "m01_couplers/S_ACLK", + "m02_couplers/S_ACLK", + "m03_couplers/S_ACLK", + "m04_couplers/S_ACLK", + "m05_couplers/S_ACLK", + "m06_couplers/S_ACLK" + ] + }, + "processing_system7_0_axi_periph_ARESETN_net": { + "ports": [ + "ARESETN", + "xbar/aresetn", + "s00_couplers/M_ARESETN", + "m00_couplers/S_ARESETN", + "m01_couplers/S_ARESETN", + "m02_couplers/S_ARESETN", + "m03_couplers/S_ARESETN", + "m04_couplers/S_ARESETN", + "m05_couplers/S_ARESETN", + "m06_couplers/S_ARESETN" + ] + } + } + }, + "rst_processing_system7_0_100M": { + "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", + "xci_name": "design_1_rst_processing_system7_0_100M_0", + "xci_path": "ip/design_1_rst_processing_system7_0_100M_0/design_1_rst_processing_system7_0_100M_0.xci", + "inst_hier_path": "rst_processing_system7_0_100M" + }, + "xlconcat_0": { + "vlnv": "xilinx.com:ip:xlconcat:2.1", + "xci_name": "design_1_xlconcat_0_0", + "xci_path": "ip/design_1_xlconcat_0_0/design_1_xlconcat_0_0.xci", + "inst_hier_path": "xlconcat_0", + "parameters": { + "NUM_PORTS": { + "value": "4" + }, + "dout_width": { + "value": "4" + } + } + }, + "d_axi_i2s_audio_0": { + "vlnv": "digilentinc.com:user:d_axi_i2s_audio:2.0", + "xci_name": "design_1_d_axi_i2s_audio_0_0", + "xci_path": "ip/design_1_d_axi_i2s_audio_0_0/design_1_d_axi_i2s_audio_0_0.xci", + "inst_hier_path": "d_axi_i2s_audio_0", + "parameters": { + "ENABLE_STREAM": { + "value": "true" + } + } + }, + "CONST0": { + "vlnv": "xilinx.com:ip:xlconstant:1.1", + "xci_name": "design_1_CONST0_0", + "xci_path": "ip/design_1_CONST0_0/design_1_CONST0_0.xci", + "inst_hier_path": "CONST0", + "parameters": { + "CONST_VAL": { + "value": "0" + } + } + }, + "hier_0": { + "interface_ports": { + "s_axi_CTRL": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "ctrl": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "PixelClk": { + "type": "clk", + "direction": "I" + }, + "TMDS_Clk_p_0": { + "type": "clk", + "direction": "O" + }, + "TMDS_Clk_n_0": { + "type": "clk", + "direction": "O" + }, + "TMDS_Data_p_0": { + "direction": "O", + "left": "2", + "right": "0" + }, + "TMDS_Data_n_0": { + "direction": "O", + "left": "2", + "right": "0" + }, + "ext_reset_in": { + "type": "rst", + "direction": "I" + }, + "clk_0": { + "type": "clk", + "direction": "I" + }, + "interconnect_aresetn": { + "type": "rst", + "direction": "O", + "left": "0", + "right": "0" + }, + "overflow": { + "direction": "O" + }, + "underflow": { + "direction": "O" + }, + "fifo_read_level": { + "direction": "O", + "left": "10", + "right": "0" + } + }, + "components": { + "v_tpg_0": { + "vlnv": "xilinx.com:ip:v_tpg:8.2", + "xci_name": "design_1_v_tpg_0_0", + "xci_path": "ip/design_1_v_tpg_0_0/design_1_v_tpg_0_0.xci", + "inst_hier_path": "hier_0/v_tpg_0", + "parameters": { + "FOREGROUND": { + "value": "1" + } + }, + "interface_ports": { + "s_axi_CTRL": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "memory_map_ref": "s_axi_CTRL" + } + }, + "addressing": { + "memory_maps": { + "s_axi_CTRL": { + "address_blocks": { + "Reg": { + "base_address": "0", + "range": "64K", + "width": "16", + "usage": "register", + "offset_base_param": "C_S_AXI_CTRL_BASEADDR", + "offset_high_param": "C_S_AXI_CTRL_HIGHADDR" + } + } + } + } + } + }, + "rgb2dvi_0": { + "vlnv": "digilentinc.com:ip:rgb2dvi:1.4", + "xci_name": "design_1_rgb2dvi_0_0", + "xci_path": "ip/design_1_rgb2dvi_0_0/design_1_rgb2dvi_0_0.xci", + "inst_hier_path": "hier_0/rgb2dvi_0", + "parameters": { + "kClkRange": { + "value": "3" + } + } + }, + "CONST1": { + "vlnv": "xilinx.com:ip:xlconstant:1.1", + "xci_name": "design_1_CONST1_0", + "xci_path": "ip/design_1_CONST1_0/design_1_CONST1_0.xci", + "inst_hier_path": "hier_0/CONST1" + }, + "v_axi4s_vid_out_0": { + "vlnv": "xilinx.com:ip:v_axi4s_vid_out:4.0", + "xci_name": "design_1_v_axi4s_vid_out_0_0", + "xci_path": "ip/design_1_v_axi4s_vid_out_0_0/design_1_v_axi4s_vid_out_0_0.xci", + "inst_hier_path": "hier_0/v_axi4s_vid_out_0", + "parameters": { + "C_HAS_ASYNC_CLK": { + "value": "1" + } + } + }, + "v_tc_0": { + "vlnv": "xilinx.com:ip:v_tc:6.2", + "xci_name": "design_1_v_tc_0_0", + "xci_path": "ip/design_1_v_tc_0_0/design_1_v_tc_0_0.xci", + "inst_hier_path": "hier_0/v_tc_0", + "parameters": { + "active_chroma_generation": { + "value": "false" + }, + "enable_detection": { + "value": "false" + }, + "horizontal_blank_generation": { + "value": "true" + }, + "vertical_blank_generation": { + "value": "true" + } + } + }, + "rst_processing_system7_0_100M1": { + "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", + "xci_name": "design_1_rst_processing_system7_0_100M1_0", + "xci_path": "ip/design_1_rst_processing_system7_0_100M1_0/design_1_rst_processing_system7_0_100M1_0.xci", + "inst_hier_path": "hier_0/rst_processing_system7_0_100M1" + } + }, + "interface_nets": { + "processing_system7_0_axi_periph_M04_AXI": { + "interface_ports": [ + "s_axi_CTRL", + "v_tpg_0/s_axi_CTRL" + ] + }, + "processing_system7_0_axi_periph_M05_AXI": { + "interface_ports": [ + "ctrl", + "v_tc_0/ctrl" + ] + }, + "v_axi4s_vid_out_0_vid_io_out": { + "interface_ports": [ + "rgb2dvi_0/RGB", + "v_axi4s_vid_out_0/vid_io_out" + ] + }, + "v_tc_0_vtiming_out": { + "interface_ports": [ + "v_tc_0/vtiming_out", + "v_axi4s_vid_out_0/vtiming_in" + ] + }, + "v_tpg_0_m_axis_video": { + "interface_ports": [ + "v_tpg_0/m_axis_video", + "v_axi4s_vid_out_0/video_in" + ] + } + }, + "nets": { + "CONST1_dout": { + "ports": [ + "CONST1/dout", + "v_tc_0/resetn", + "v_tc_0/s_axi_aclken", + "v_axi4s_vid_out_0/aclken", + "v_axi4s_vid_out_0/aresetn", + "v_axi4s_vid_out_0/vid_io_out_ce", + "v_tc_0/clken" + ] + }, + "clk_0_1": { + "ports": [ + "clk_0", + "v_tc_0/s_axi_aclk", + "v_tpg_0/ap_clk", + "v_axi4s_vid_out_0/aclk" + ] + }, + "fifo_read_level": { + "ports": [ + "v_axi4s_vid_out_0/fifo_read_level", + "fifo_read_level" + ] + }, + "overflow": { + "ports": [ + "v_axi4s_vid_out_0/overflow", + "overflow" + ] + }, + "processing_system7_0_FCLK_CLK1": { + "ports": [ + "PixelClk", + "rgb2dvi_0/PixelClk", + "rst_processing_system7_0_100M1/slowest_sync_clk", + "v_axi4s_vid_out_0/vid_io_out_clk", + "v_tc_0/clk" + ] + }, + "processing_system7_0_FCLK_RESET0_N": { + "ports": [ + "ext_reset_in", + "rst_processing_system7_0_100M1/ext_reset_in" + ] + }, + "rgb2dvi_0_TMDS_Clk_n": { + "ports": [ + "rgb2dvi_0/TMDS_Clk_n", + "TMDS_Clk_n_0" + ] + }, + "rgb2dvi_0_TMDS_Clk_p": { + "ports": [ + "rgb2dvi_0/TMDS_Clk_p", + "TMDS_Clk_p_0" + ] + }, + "rgb2dvi_0_TMDS_Data_n": { + "ports": [ + "rgb2dvi_0/TMDS_Data_n", + "TMDS_Data_n_0" + ] + }, + "rgb2dvi_0_TMDS_Data_p": { + "ports": [ + "rgb2dvi_0/TMDS_Data_p", + "TMDS_Data_p_0" + ] + }, + "rst_processing_system7_0_100M1_interconnect_aresetn": { + "ports": [ + "rst_processing_system7_0_100M1/interconnect_aresetn", + "interconnect_aresetn" + ] + }, + "rst_processing_system7_0_100M1_peripheral_reset": { + "ports": [ + "rst_processing_system7_0_100M1/peripheral_reset", + "rgb2dvi_0/aRst", + "v_axi4s_vid_out_0/vid_io_out_reset" + ] + }, + "underflow": { + "ports": [ + "v_axi4s_vid_out_0/underflow", + "underflow" + ] + }, + "v_axi4s_vid_out_0_sof_state_out": { + "ports": [ + "v_axi4s_vid_out_0/sof_state_out", + "v_tc_0/sof_state" + ] + }, + "vtg_ce": { + "ports": [ + "v_axi4s_vid_out_0/vtg_ce", + "v_tc_0/gen_clken" + ] + } + } + }, + "hier_1": { + "interface_ports": { + "ctrl": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "TMDS_Clk_p_1": { + "type": "clk", + "direction": "I" + }, + "TMDS_Clk_n_1": { + "type": "clk", + "direction": "I" + }, + "TMDS_Data_p_1": { + "direction": "I", + "left": "2", + "right": "0" + }, + "TMDS_Data_n_1": { + "direction": "I", + "left": "2", + "right": "0" + }, + "s_axi_aclk": { + "type": "clk", + "direction": "I" + }, + "s_axi_aresetn": { + "type": "rst", + "direction": "I" + }, + "RefClk": { + "type": "clk", + "direction": "I" + }, + "ext_reset_in": { + "type": "rst", + "direction": "I" + }, + "aPixelClkLckd_0": { + "direction": "O" + }, + "pLocked_0": { + "direction": "O" + } + }, + "components": { + "v_vid_in_axi4s_0": { + "vlnv": "xilinx.com:ip:v_vid_in_axi4s:5.0", + "xci_name": "design_1_v_vid_in_axi4s_0_0", + "xci_path": "ip/design_1_v_vid_in_axi4s_0_0/design_1_v_vid_in_axi4s_0_0.xci", + "inst_hier_path": "hier_1/v_vid_in_axi4s_0", + "parameters": { + "C_HAS_ASYNC_CLK": { + "value": "1" + } + } + }, + "CONST1": { + "vlnv": "xilinx.com:ip:xlconstant:1.1", + "xci_name": "design_1_CONST1_1", + "xci_path": "ip/design_1_CONST1_1/design_1_CONST1_1.xci", + "inst_hier_path": "hier_1/CONST1" + }, + "v_tc_0": { + "vlnv": "xilinx.com:ip:v_tc:6.2", + "xci_name": "design_1_v_tc_0_1", + "xci_path": "ip/design_1_v_tc_0_1/design_1_v_tc_0_1.xci", + "inst_hier_path": "hier_1/v_tc_0", + "parameters": { + "auto_generation_mode": { + "value": "true" + }, + "enable_generation": { + "value": "true" + } + } + }, + "rst_processing_system7_0_100M1": { + "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", + "xci_name": "design_1_rst_processing_system7_0_100M_1", + "xci_path": "ip/design_1_rst_processing_system7_0_100M_1/design_1_rst_processing_system7_0_100M_1.xci", + "inst_hier_path": "hier_1/rst_processing_system7_0_100M1" + }, + "dvi2rgb_0": { + "vlnv": "digilentinc.com:ip:dvi2rgb:2.0", + "xci_name": "design_1_dvi2rgb_0_1", + "xci_path": "ip/design_1_dvi2rgb_0_1/design_1_dvi2rgb_0_1.xci", + "inst_hier_path": "hier_1/dvi2rgb_0", + "parameters": { + "kClkRange": { + "value": "3" + }, + "kEmulateDDC": { + "value": "false" + } + } + }, + "system_ila_0": { + "vlnv": "xilinx.com:ip:system_ila:1.1", + "xci_name": "design_1_system_ila_0_1", + "xci_path": "ip/design_1_system_ila_0_1/design_1_system_ila_0_1.xci", + "inst_hier_path": "hier_1/system_ila_0", + "parameters": { + "C_MON_TYPE": { + "value": "INTERFACE" + }, + "C_NUM_MONITOR_SLOTS": { + "value": "1" + }, + "C_SLOT_0_INTF_TYPE": { + "value": "xilinx.com:interface:vid_io_rtl:1.0" + }, + "C_SLOT_0_TYPE": { + "value": "0" + } + }, + "interface_ports": { + "SLOT_0_VID_IO": { + "mode": "Monitor", + "vlnv_bus_definition": "xilinx.com:interface:vid_io:1.0", + "vlnv": "xilinx.com:interface:vid_io_rtl:1.0" + } + } + } + }, + "interface_nets": { + "Conn1": { + "interface_ports": [ + "ctrl", + "v_tc_0/ctrl" + ] + }, + "dvi2rgb_0_RGB": { + "interface_ports": [ + "dvi2rgb_0/RGB", + "v_vid_in_axi4s_0/vid_io_in", + "system_ila_0/SLOT_0_VID_IO" + ], + "hdl_attributes": { + "DEBUG": { + "value": "true" + }, + "MARK_DEBUG": { + "value": "true" + } + } + }, + "v_vid_in_axi4s_0_vtiming_out": { + "interface_ports": [ + "v_tc_0/vtiming_in", + "v_vid_in_axi4s_0/vtiming_out" + ] + } + }, + "nets": { + "CONST1_dout": { + "ports": [ + "CONST1/dout", + "v_vid_in_axi4s_0/aclken", + "v_vid_in_axi4s_0/axis_enable", + "v_vid_in_axi4s_0/aresetn" + ] + }, + "RefClk_0_1": { + "ports": [ + "RefClk", + "rst_processing_system7_0_100M1/slowest_sync_clk", + "dvi2rgb_0/RefClk" + ] + }, + "TMDS_Clk_n_1_1": { + "ports": [ + "TMDS_Clk_n_1", + "dvi2rgb_0/TMDS_Clk_n" + ] + }, + "TMDS_Clk_p_1_1": { + "ports": [ + "TMDS_Clk_p_1", + "dvi2rgb_0/TMDS_Clk_p" + ] + }, + "TMDS_Data_n_1_1": { + "ports": [ + "TMDS_Data_n_1", + "dvi2rgb_0/TMDS_Data_n" + ] + }, + "TMDS_Data_p_1_1": { + "ports": [ + "TMDS_Data_p_1", + "dvi2rgb_0/TMDS_Data_p" + ] + }, + "dvi2rgb_0_PixelClk": { + "ports": [ + "dvi2rgb_0/PixelClk", + "v_vid_in_axi4s_0/vid_io_in_clk", + "system_ila_0/clk" + ] + }, + "dvi2rgb_0_aPixelClkLckd": { + "ports": [ + "dvi2rgb_0/aPixelClkLckd", + "aPixelClkLckd_0", + "v_vid_in_axi4s_0/vid_io_in_ce" + ] + }, + "dvi2rgb_0_pLocked": { + "ports": [ + "dvi2rgb_0/pLocked", + "pLocked_0" + ] + }, + "ext_reset_in_1": { + "ports": [ + "ext_reset_in", + "rst_processing_system7_0_100M1/ext_reset_in" + ] + }, + "s_axi_aclk_1": { + "ports": [ + "s_axi_aclk", + "v_tc_0/s_axi_aclk", + "v_vid_in_axi4s_0/aclk", + "v_tc_0/clk" + ] + }, + "s_axi_aresetn_1": { + "ports": [ + "s_axi_aresetn", + "v_tc_0/s_axi_aresetn" + ] + } + } + } + }, + "interface_nets": { + "axi_dma_0_M_AXIS_MM2S": { + "interface_ports": [ + "axi_dma_0/M_AXIS_MM2S", + "d_axi_i2s_audio_0/AXI_MM2S" + ] + }, + "axi_dma_0_M_AXI_MM2S": { + "interface_ports": [ + "axi_dma_0/M_AXI_MM2S", + "axi_mem_intercon/S00_AXI" + ] + }, + "axi_dma_0_M_AXI_S2MM": { + "interface_ports": [ + "axi_dma_0/M_AXI_S2MM", + "axi_mem_intercon/S01_AXI" + ] + }, + "axi_gpio_0_GPIO": { + "interface_ports": [ + "btns_4bits", + "axi_gpio_0/GPIO" + ] + }, + "axi_iic_0_IIC": { + "interface_ports": [ + "iic_rtl", + "axi_iic_0/IIC" + ] + }, + "axi_mem_intercon_M00_AXI": { + "interface_ports": [ + "axi_mem_intercon/M00_AXI", + "processing_system7_0/S_AXI_HP0" + ] + }, + "d_axi_i2s_audio_0_AXI_S2MM": { + "interface_ports": [ + "axi_dma_0/S_AXIS_S2MM", + "d_axi_i2s_audio_0/AXI_S2MM" + ] + }, + "processing_system7_0_DDR": { + "interface_ports": [ + "DDR", + "processing_system7_0/DDR" + ] + }, + "processing_system7_0_FIXED_IO": { + "interface_ports": [ + "FIXED_IO", + "processing_system7_0/FIXED_IO" + ] + }, + "processing_system7_0_M_AXI_GP0": { + "interface_ports": [ + "processing_system7_0/M_AXI_GP0", + "processing_system7_0_axi_periph/S00_AXI" + ] + }, + "processing_system7_0_axi_periph_M00_AXI": { + "interface_ports": [ + "axi_dma_0/S_AXI_LITE", + "processing_system7_0_axi_periph/M00_AXI" + ] + }, + "processing_system7_0_axi_periph_M01_AXI": { + "interface_ports": [ + "d_axi_i2s_audio_0/AXI_L", + "processing_system7_0_axi_periph/M01_AXI" + ] + }, + "processing_system7_0_axi_periph_M02_AXI": { + "interface_ports": [ + "axi_iic_0/S_AXI", + "processing_system7_0_axi_periph/M02_AXI" + ] + }, + "processing_system7_0_axi_periph_M03_AXI": { + "interface_ports": [ + "axi_gpio_0/S_AXI", + "processing_system7_0_axi_periph/M03_AXI" + ] + }, + "processing_system7_0_axi_periph_M04_AXI": { + "interface_ports": [ + "processing_system7_0_axi_periph/M04_AXI", + "hier_0/s_axi_CTRL" + ] + }, + "processing_system7_0_axi_periph_M05_AXI": { + "interface_ports": [ + "processing_system7_0_axi_periph/M05_AXI", + "hier_0/ctrl" + ] + }, + "processing_system7_0_axi_periph_M06_AXI": { + "interface_ports": [ + "processing_system7_0_axi_periph/M06_AXI", + "hier_1/ctrl" + ] + } + }, + "nets": { + "SDATA_I_0_1": { + "ports": [ + "SDATA_I", + "d_axi_i2s_audio_0/SDATA_I" + ] + }, + "TMDS_Clk_n_1_1": { + "ports": [ + "TMDS_Clk_n_1", + "hier_1/TMDS_Clk_n_1" + ] + }, + "TMDS_Clk_p_1_1": { + "ports": [ + "TMDS_Clk_p_1", + "hier_1/TMDS_Clk_p_1" + ] + }, + "TMDS_Data_n_1_1": { + "ports": [ + "TMDS_Data_n_1", + "hier_1/TMDS_Data_n_1" + ] + }, + "TMDS_Data_p_1_1": { + "ports": [ + "TMDS_Data_p_1", + "hier_1/TMDS_Data_p_1" + ] + }, + "axi_dma_0_mm2s_introut": { + "ports": [ + "axi_dma_0/mm2s_introut", + "xlconcat_0/In0" + ] + }, + "axi_dma_0_s2mm_introut": { + "ports": [ + "axi_dma_0/s2mm_introut", + "xlconcat_0/In1" + ] + }, + "axi_gpio_0_ip2intc_irpt": { + "ports": [ + "axi_gpio_0/ip2intc_irpt", + "xlconcat_0/In3" + ] + }, + "axi_iic_0_iic2intc_irpt": { + "ports": [ + "axi_iic_0/iic2intc_irpt", + "xlconcat_0/In2" + ] + }, + "d_axi_i2s_audio_0_BCLK_O": { + "ports": [ + "d_axi_i2s_audio_0/BCLK_O", + "BCLK_O" + ] + }, + "d_axi_i2s_audio_0_LRCLK_O": { + "ports": [ + "d_axi_i2s_audio_0/LRCLK_O", + "LRCLK_O" + ] + }, + "d_axi_i2s_audio_0_MCLK_O": { + "ports": [ + "d_axi_i2s_audio_0/MCLK_O", + "MCLK_O" + ] + }, + "d_axi_i2s_audio_0_SDATA_O": { + "ports": [ + "d_axi_i2s_audio_0/SDATA_O", + "SDATA_O" + ] + }, + "hier_1_aPixelClkLckd_0": { + "ports": [ + "hier_1/aPixelClkLckd_0", + "leds_4bits_tri_o_0" + ] + }, + "hier_1_pLocked_0": { + "ports": [ + "hier_1/pLocked_0", + "leds_4bits_tri_o_1" + ] + }, + "processing_system7_0_FCLK_CLK0": { + "ports": [ + "processing_system7_0/FCLK_CLK0", + "axi_dma_0/s_axi_lite_aclk", + "axi_dma_0/m_axi_mm2s_aclk", + "axi_dma_0/m_axi_s2mm_aclk", + "axi_gpio_0/s_axi_aclk", + "axi_iic_0/s_axi_aclk", + "axi_mem_intercon/ACLK", + "axi_mem_intercon/S00_ACLK", + "axi_mem_intercon/S01_ACLK", + "axi_mem_intercon/M00_ACLK", + "processing_system7_0/M_AXI_GP0_ACLK", + "processing_system7_0_axi_periph/ACLK", + "processing_system7_0_axi_periph/S00_ACLK", + "processing_system7_0_axi_periph/M00_ACLK", + "processing_system7_0_axi_periph/M01_ACLK", + "processing_system7_0_axi_periph/M02_ACLK", + "processing_system7_0_axi_periph/M03_ACLK", + "rst_processing_system7_0_100M/slowest_sync_clk", + "processing_system7_0/S_AXI_HP0_ACLK", + "d_axi_i2s_audio_0/CLK_100MHZ_I", + "d_axi_i2s_audio_0/S_AXIS_MM2S_ACLK", + "d_axi_i2s_audio_0/M_AXIS_S2MM_ACLK", + "d_axi_i2s_audio_0/AXI_L_aclk", + "hier_0/clk_0", + "processing_system7_0_axi_periph/M04_ACLK", + "processing_system7_0_axi_periph/M05_ACLK", + "hier_1/s_axi_aclk", + "processing_system7_0_axi_periph/M06_ACLK" + ] + }, + "processing_system7_0_FCLK_CLK1": { + "ports": [ + "processing_system7_0/FCLK_CLK1", + "hier_0/PixelClk" + ] + }, + "processing_system7_0_FCLK_CLK2": { + "ports": [ + "processing_system7_0/FCLK_CLK2", + "hier_1/RefClk" + ] + }, + "processing_system7_0_FCLK_RESET0_N": { + "ports": [ + "processing_system7_0/FCLK_RESET0_N", + "rst_processing_system7_0_100M/ext_reset_in", + "hier_0/ext_reset_in", + "hier_1/ext_reset_in" + ] + }, + "rgb2dvi_0_TMDS_Clk_n": { + "ports": [ + "hier_0/TMDS_Clk_n_0", + "TMDS_Clk_n_0" + ] + }, + "rgb2dvi_0_TMDS_Clk_p": { + "ports": [ + "hier_0/TMDS_Clk_p_0", + "TMDS_Clk_p_0" + ] + }, + "rgb2dvi_0_TMDS_Data_n": { + "ports": [ + "hier_0/TMDS_Data_n_0", + "TMDS_Data_n_0" + ] + }, + "rgb2dvi_0_TMDS_Data_p": { + "ports": [ + "hier_0/TMDS_Data_p_0", + "TMDS_Data_p_0" + ] + }, + "rst_processing_system7_0_100M_interconnect_aresetn": { + "ports": [ + "rst_processing_system7_0_100M/interconnect_aresetn", + "axi_mem_intercon/ARESETN", + "processing_system7_0_axi_periph/ARESETN" + ] + }, + "rst_processing_system7_0_100M_peripheral_aresetn": { + "ports": [ + "rst_processing_system7_0_100M/peripheral_aresetn", + "axi_dma_0/axi_resetn", + "axi_gpio_0/s_axi_aresetn", + "axi_iic_0/s_axi_aresetn", + "axi_mem_intercon/S00_ARESETN", + "axi_mem_intercon/S01_ARESETN", + "axi_mem_intercon/M00_ARESETN", + "processing_system7_0_axi_periph/S00_ARESETN", + "processing_system7_0_axi_periph/M00_ARESETN", + "processing_system7_0_axi_periph/M01_ARESETN", + "processing_system7_0_axi_periph/M02_ARESETN", + "processing_system7_0_axi_periph/M03_ARESETN", + "d_axi_i2s_audio_0/S_AXIS_MM2S_ARESETN", + "d_axi_i2s_audio_0/M_AXIS_S2MM_ARESETN", + "d_axi_i2s_audio_0/AXI_L_aresetn", + "processing_system7_0_axi_periph/M04_ARESETN", + "processing_system7_0_axi_periph/M05_ARESETN", + "hier_1/s_axi_aresetn", + "processing_system7_0_axi_periph/M06_ARESETN" + ] + }, + "xlconcat_0_dout": { + "ports": [ + "xlconcat_0/dout", + "processing_system7_0/IRQ_F2P" + ] + } + }, + "addressing": { + "/axi_dma_0": { + "address_spaces": { + "Data_MM2S": { + "segments": { + "SEG_processing_system7_0_HP0_DDR_LOWOCM": { + "address_block": "/processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM", + "offset": "0x00000000", + "range": "512M" + } + } + }, + "Data_S2MM": { + "segments": { + "SEG_processing_system7_0_HP0_DDR_LOWOCM": { + "address_block": "/processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM", + "offset": "0x00000000", + "range": "512M" + } + } + } + } + }, + "/processing_system7_0": { + "address_spaces": { + "Data": { + "segments": { + "SEG_axi_dma_0_Reg": { + "address_block": "/axi_dma_0/S_AXI_LITE/Reg", + "offset": "0x40400000", + "range": "64K" + }, + "SEG_axi_gpio_0_Reg": { + "address_block": "/axi_gpio_0/S_AXI/Reg", + "offset": "0x41200000", + "range": "64K" + }, + "SEG_axi_iic_0_Reg": { + "address_block": "/axi_iic_0/S_AXI/Reg", + "offset": "0x41600000", + "range": "64K" + }, + "SEG_d_axi_i2s_audio_0_AXI_L_reg": { + "address_block": "/d_axi_i2s_audio_0/AXI_L/AXI_L_reg", + "offset": "0x43C00000", + "range": "64K", + "offset_base_param": "C_AXI_L_BASEADDR", + "offset_high_param": "C_AXI_L_HIGHADDR" + }, + "SEG_v_tc_0_Reg": { + "address_block": "/hier_0/v_tc_0/ctrl/Reg", + "offset": "0x43C20000", + "range": "64K" + }, + "SEG_v_tc_0_Reg_1": { + "address_block": "/hier_1/v_tc_0/ctrl/Reg", + "offset": "0x43C30000", + "range": "64K" + }, + "SEG_v_tpg_0_Reg": { + "address_block": "/hier_0/v_tpg_0/s_axi_CTRL/Reg", + "offset": "0x43C10000", + "range": "64K", + "offset_base_param": "C_S_AXI_CTRL_BASEADDR", + "offset_high_param": "C_S_AXI_CTRL_HIGHADDR" + } + } + } + } + } + } + } +} \ No newline at end of file diff --git a/hdmi-in-test/hdmi-in-test.vitis/hdmi-in-test.files/Debug/hworld.elf b/hdmi-in-test/hdmi-in-test.vitis/hdmi-in-test.files/Debug/hworld.elf new file mode 100755 index 0000000..fb43d40 Binary files /dev/null and b/hdmi-in-test/hdmi-in-test.vitis/hdmi-in-test.files/Debug/hworld.elf differ diff --git a/hdmi-in-test/hdmi-in-test.vitis/hdmi-in-test.files/src/helloworld.c b/hdmi-in-test/hdmi-in-test.vitis/hdmi-in-test.files/src/helloworld.c new file mode 100644 index 0000000..82b0040 --- /dev/null +++ b/hdmi-in-test/hdmi-in-test.vitis/hdmi-in-test.files/src/helloworld.c @@ -0,0 +1,90 @@ +#include +//#include "platform.h" +#include "xil_printf.h" +#include "xv_tpg.h" +#include "xvtc.h" + +int main() +{ + //init_platform(); + + int Status; + XV_tpg tpg_inst; // Instance of the TPG core + XVtc VtcInst; // Instance of the VTC core + + print("--- hdmi-in-test ---\n\r"); + + //--( TPG Initialization + print("TPG Initialization\n\r"); + Status = XV_tpg_Initialize(&tpg_inst, XPAR_XV_TPG_0_DEVICE_ID); + if(Status!= XST_SUCCESS) + { + xil_printf("TPG configuration failed\r\n"); + return(XST_FAILURE); + } + + // Set Resolution to 1280x720 + XV_tpg_Set_height(&tpg_inst, 720); + XV_tpg_Set_width(&tpg_inst, 1280); + + // Set Color Space to RGB + XV_tpg_Set_colorFormat(&tpg_inst, 0x0); + + //Set pattern to color bar + XV_tpg_Set_bckgndId(&tpg_inst, XTPG_BKGND_COLOR_BARS); + + //Start the TPG + XV_tpg_EnableAutoRestart(&tpg_inst); + XV_tpg_Start(&tpg_inst); + xil_printf("TPG started!\r\n"); + //--) + + //--( VTC Initialization + print("VTC Initialization\n\r"); + XVtc_Config *Config; + XVtc_Timing ti; + XVtc_Signal si; + XVtc_HoriOffsets ho; + XVtc_Polarity po; + + //Initialize the VTC driver so that it's ready to use look up + //configuration in the config table, then initialize it. + Config = XVtc_LookupConfig(XPAR_VTC_0_DEVICE_ID); + if (NULL == Config) { + return (XST_FAILURE); + } + + //Initialize the VTC core + Status = XVtc_CfgInitialize(&VtcInst, Config, Config->BaseAddress); + if (Status != (XST_SUCCESS)) { + return (XST_FAILURE); + } + + //Perform a self-test + Status = XVtc_SelfTest(&VtcInst); + if (Status != (XST_SUCCESS)) { + return (XST_FAILURE); + } + + //Set our configuration as 1280x720 + XVtc_ConvVideoMode2Timing(&VtcInst, XVTC_VMODE_720P, &ti); + XVtc_ConvTiming2Signal(&VtcInst, &ti, &si, &ho, &po); + XVtc_SetGenerator(&VtcInst, &si); + + //Enable the vtc + XVtc_Enable(&VtcInst); + xil_printf("VTC enabled!\r\n"); + //--) + + xil_printf("\r\nInstructions:\r\n"); + xil_printf("1. connect HDMI_OUT to HDMI_IN\r\n"); + xil_printf("2. Check LD1,LD0 are on\r\n"); + xil_printf("3. open ila_1 on vivado (connected to hdmi input after tmds2rgb conversion\r\n"); + xil_printf("4. trigger it and compare results with logs/hdmi-loop-test-ila.png \r\n"); + + while(1){ + } + + cleanup_platform(); + return 0; +} diff --git a/hdmi-in-test/hdmi-in-test.xpr b/hdmi-in-test/hdmi-in-test.xpr new file mode 100644 index 0000000..e0b2987 --- /dev/null +++ b/hdmi-in-test/hdmi-in-test.xpr @@ -0,0 +1,923 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/hdmi-in-test/logs/hdmi-loop-test-ila.png b/hdmi-in-test/logs/hdmi-loop-test-ila.png new file mode 100644 index 0000000..f17aee7 Binary files /dev/null and b/hdmi-in-test/logs/hdmi-loop-test-ila.png differ diff --git a/hdmi-in-test/logs/hdmi-loop-test-ila2.png b/hdmi-in-test/logs/hdmi-loop-test-ila2.png new file mode 100644 index 0000000..6d80b88 Binary files /dev/null and b/hdmi-in-test/logs/hdmi-loop-test-ila2.png differ diff --git a/hdmi-in-test/xdc/pynqz2.xdc b/hdmi-in-test/xdc/pynqz2.xdc new file mode 100644 index 0000000..53a11c5 --- /dev/null +++ b/hdmi-in-test/xdc/pynqz2.xdc @@ -0,0 +1,265 @@ +#set_property IOSTANDARD LVCMOS33 [get_ports {btns_4bits_tri_i_0}] +#set_property IOSTANDARD LVCMOS33 [get_ports {btns_4bits_tri_i_1}] +#set_property IOSTANDARD LVCMOS33 [get_ports {btns_4bits_tri_i_2}] +#set_property IOSTANDARD LVCMOS33 [get_ports {btns_4bits_tri_i_3}] +set_property IOSTANDARD LVCMOS33 [get_ports {leds_4bits_tri_o_0}] +set_property IOSTANDARD LVCMOS33 [get_ports {leds_4bits_tri_o_1}] +set_property IOSTANDARD LVCMOS33 [get_ports {leds_4bits_tri_o_2}] +set_property IOSTANDARD LVCMOS33 [get_ports {leds_4bits_tri_o_3}] +#set_property IOSTANDARD LVCMOS33 [get_ports {sws_2bits_tri_i_0}] +#set_property IOSTANDARD LVCMOS33 [get_ports {sws_2bits_tri_i_1}] +#set_property IOSTANDARD LVCMOS33 [get_ports {sys_clk}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JA1}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JA2}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JA3}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JA4}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JA7}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JA8}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JA9}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JA10}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JB1}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JB2}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JB3}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JB4}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JB7}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JB8}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JB9}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JB10}] +#set_property IOSTANDARD LVCMOS33 [get_ports {i2c_scl_i}] +#set_property IOSTANDARD LVCMOS33 [get_ports {i2c_sda_i}] +#set_property IOSTANDARD LVCMOS33 [get_ports {rgb_led_tri_o_0}] +#set_property IOSTANDARD LVCMOS33 [get_ports {rgb_led_tri_o_1}] +#set_property IOSTANDARD LVCMOS33 [get_ports {rgb_led_tri_o_2}] +#set_property IOSTANDARD LVCMOS33 [get_ports {rgb_led_tri_o_3}] +#set_property IOSTANDARD LVCMOS33 [get_ports {rgb_led_tri_o_4}] +#set_property IOSTANDARD LVCMOS33 [get_ports {rgb_led_tri_o_5}] +#set_property IOSTANDARD LVCMOS33 [get_ports {arduino_a0_a13_tri_i_0}] +#set_property IOSTANDARD LVCMOS33 [get_ports {arduino_a0_a13_tri_i_1}] +#set_property IOSTANDARD LVCMOS33 [get_ports {arduino_a0_a13_tri_i_2}] +#set_property IOSTANDARD LVCMOS33 [get_ports {arduino_a0_a13_tri_i_3}] +#set_property IOSTANDARD LVCMOS33 [get_ports {arduino_a0_a13_tri_i_4}] +#set_property IOSTANDARD LVCMOS33 [get_ports {arduino_a0_a13_tri_i_5}] +#set_property IOSTANDARD LVCMOS33 [get_ports {arduino_a0_a13_tri_i_6}] +#set_property IOSTANDARD LVCMOS33 [get_ports {arduino_a0_a13_tri_i_7}] +#set_property IOSTANDARD LVCMOS33 [get_ports {arduino_a0_a13_tri_i_8}] +#set_property IOSTANDARD LVCMOS33 [get_ports {arduino_a0_a13_tri_i_9}] +#set_property IOSTANDARD LVCMOS33 [get_ports {arduino_a0_a13_tri_i_10}] +#set_property IOSTANDARD LVCMOS33 [get_ports {arduino_a0_a13_tri_i_11}] +#set_property IOSTANDARD LVCMOS33 [get_ports {arduino_a0_a13_tri_i_12}] +#set_property IOSTANDARD LVCMOS33 [get_ports {arduino_a0_a13_tri_i_13}] +#set_property IOSTANDARD LVCMOS33 [get_ports {raspberry_pi_tri_i_0}] +#set_property IOSTANDARD LVCMOS33 [get_ports {raspberry_pi_tri_i_1}] +#set_property IOSTANDARD LVCMOS33 [get_ports {raspberry_pi_tri_i_2}] +#set_property IOSTANDARD LVCMOS33 [get_ports {raspberry_pi_tri_i_3}] +#set_property IOSTANDARD LVCMOS33 [get_ports {raspberry_pi_tri_i_4}] +#set_property IOSTANDARD LVCMOS33 [get_ports {raspberry_pi_tri_i_5}] +#set_property IOSTANDARD LVCMOS33 [get_ports {raspberry_pi_tri_i_6}] +#set_property IOSTANDARD LVCMOS33 [get_ports {raspberry_pi_tri_i_7}] +#set_property IOSTANDARD LVCMOS33 [get_ports {raspberry_pi_tri_i_8}] +#set_property IOSTANDARD LVCMOS33 [get_ports {raspberry_pi_tri_i_9}] +#set_property IOSTANDARD LVCMOS33 [get_ports {raspberry_pi_tri_i_10}] +#set_property IOSTANDARD LVCMOS33 [get_ports {raspberry_pi_tri_i_11}] +#set_property IOSTANDARD LVCMOS33 [get_ports {raspberry_pi_tri_i_12}] +#set_property IOSTANDARD LVCMOS33 [get_ports {raspberry_pi_tri_i_13}] +#set_property IOSTANDARD LVCMOS33 [get_ports {raspberry_pi_tri_i_14}] +#set_property IOSTANDARD LVCMOS33 [get_ports {raspberry_pi_tri_i_15}] +#set_property IOSTANDARD LVCMOS33 [get_ports {raspberry_pi_tri_i_16}] +#set_property IOSTANDARD LVCMOS33 [get_ports {raspberry_pi_tri_i_17}] +#set_property IOSTANDARD LVCMOS33 [get_ports {raspberry_pi_tri_i_18}] +#set_property IOSTANDARD LVCMOS33 [get_ports {raspberry_pi_tri_i_19}] +#set_property IOSTANDARD LVCMOS33 [get_ports {raspberry_pi_tri_i_20}] +#set_property IOSTANDARD LVCMOS33 [get_ports {raspberry_pi_tri_i_21}] +#set_property IOSTANDARD LVCMOS33 [get_ports {raspberry_pi_tri_i_22}] +#set_property IOSTANDARD LVCMOS33 [get_ports {raspberry_pi_tri_i_23}] +#set_property IOSTANDARD LVCMOS33 [get_ports {raspberry_pi_tri_i_24}] +#set_property IOSTANDARD LVCMOS33 [get_ports {spi_miso_i}] +#set_property IOSTANDARD LVCMOS33 [get_ports {spi_mosi_i}] +#set_property IOSTANDARD LVCMOS33 [get_ports {spi_sclk_i}] +#set_property IOSTANDARD LVCMOS33 [get_ports {spi_ss_i}] +#set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_rx_hpd}] +set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Clk_p_1}] +set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Clk_n_1}] +set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Data_p_1[0]}] +set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Data_p_1[1]}] +set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Data_p_1[2]}] +set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Data_n_1[0]}] +set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Data_n_1[1]}] +set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Data_n_1[2]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_tx_hpd}] +set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Clk_p_0}] +set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Clk_n_0}] +set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Data_p_0[0]}] +set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Data_p_0[1]}] +set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Data_p_0[2]}] +set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Data_n_0[0]}] +set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Data_n_0[1]}] +set_property IOSTANDARD TMDS_33 [get_ports {TMDS_Data_n_0[2]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_in_ddc_scl}] +#set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_in_ddc_sda}] +#set_property IOSTANDARD LVCMOS33 [get_ports {respberry_sd_i}] +#set_property IOSTANDARD LVCMOS33 [get_ports {respberry_sc_i}] +#set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_tx_cec}] +#set_property IOSTANDARD LVCMOS33 [get_ports {arduino_a0}] +#set_property IOSTANDARD LVCMOS33 [get_ports {arduino_a1}] +#set_property IOSTANDARD LVCMOS33 [get_ports {arduino_a2}] +#set_property IOSTANDARD LVCMOS33 [get_ports {arduino_a3}] +#set_property IOSTANDARD LVCMOS33 [get_ports {arduino_a4}] +#set_property IOSTANDARD LVCMOS33 [get_ports {arduino_a5}] + +#set_property IOSTANDARD LVCMOS33 [get_ports {audio_sd_i}] +#set_property IOSTANDARD LVCMOS33 [get_ports {audio_sc_i}] +#set_property IOSTANDARD LVCMOS33 [get_ports {audio_adr_0}] +#set_property IOSTANDARD LVCMOS33 [get_ports {audio_adr_1}] +#set_property IOSTANDARD LVCMOS33 [get_ports {audio_clk}] +# +#set_property IOSTANDARD LVCMOS33 [get_ports {bclk_i}] +#set_property IOSTANDARD LVCMOS33 [get_ports {wclk_i}] +#set_property IOSTANDARD LVCMOS33 [get_ports {sdada_out_i}] +#set_property IOSTANDARD LVCMOS33 [get_ports {sdata_in_i}] + +#set_property PACKAGE_PIN D19 [get_ports {btns_4bits_tri_i_0}] +#set_property PACKAGE_PIN D20 [get_ports {btns_4bits_tri_i_1}] +#set_property PACKAGE_PIN L20 [get_ports {btns_4bits_tri_i_2}] +#set_property PACKAGE_PIN L19 [get_ports {btns_4bits_tri_i_3}] +set_property PACKAGE_PIN R14 [get_ports {leds_4bits_tri_o_0}] +set_property PACKAGE_PIN P14 [get_ports {leds_4bits_tri_o_1}] +set_property PACKAGE_PIN N16 [get_ports {leds_4bits_tri_o_2}] +set_property PACKAGE_PIN M14 [get_ports {leds_4bits_tri_o_3}] +#set_property PACKAGE_PIN M20 [get_ports {sws_2bits_tri_i_0}] +#set_property PACKAGE_PIN M19 [get_ports {sws_2bits_tri_i_1}] +#set_property PACKAGE_PIN H16 [get_ports {sys_clk}] +#set_property PACKAGE_PIN Y18 [get_ports {JA1}] +#set_property PACKAGE_PIN Y19 [get_ports {JA2}] +#set_property PACKAGE_PIN Y16 [get_ports {JA3}] +#set_property PACKAGE_PIN Y17 [get_ports {JA4}] +#set_property PACKAGE_PIN U18 [get_ports {JA7}] +#set_property PACKAGE_PIN U19 [get_ports {JA8}] +#set_property PACKAGE_PIN W18 [get_ports {JA9}] +#set_property PACKAGE_PIN W19 [get_ports {JA10}] +#set_property PACKAGE_PIN W14 [get_ports {JB1}] +#set_property PACKAGE_PIN Y14 [get_ports {JB2}] +#set_property PACKAGE_PIN T11 [get_ports {JB3}] +#set_property PACKAGE_PIN T10 [get_ports {JB4}] +#set_property PACKAGE_PIN V16 [get_ports {JB7}] +#set_property PACKAGE_PIN W16 [get_ports {JB8}] +#set_property PACKAGE_PIN V12 [get_ports {JB9}] +#set_property PACKAGE_PIN W13 [get_ports {JB10}] +#set_property PACKAGE_PIN P15 [get_ports {i2c_scl_i}] +#set_property PACKAGE_PIN P16 [get_ports {i2c_sda_i}] +#set_property PACKAGE_PIN L15 [get_ports {rgb_led_tri_o_0}] +#set_property PACKAGE_PIN G17 [get_ports {rgb_led_tri_o_1}] +#set_property PACKAGE_PIN N15 [get_ports {rgb_led_tri_o_2}] +#set_property PACKAGE_PIN G14 [get_ports {rgb_led_tri_o_3}] +#set_property PACKAGE_PIN L14 [get_ports {rgb_led_tri_o_4}] +#set_property PACKAGE_PIN M15 [get_ports {rgb_led_tri_o_5}] +#set_property PACKAGE_PIN T14 [get_ports {arduino_a0_a13_tri_i_0}] +#set_property PACKAGE_PIN U12 [get_ports {arduino_a0_a13_tri_i_1}] +#set_property PACKAGE_PIN U13 [get_ports {arduino_a0_a13_tri_i_2}] +#set_property PACKAGE_PIN V13 [get_ports {arduino_a0_a13_tri_i_3}] +#set_property PACKAGE_PIN V15 [get_ports {arduino_a0_a13_tri_i_4}] +#set_property PACKAGE_PIN T15 [get_ports {arduino_a0_a13_tri_i_5}] +#set_property PACKAGE_PIN R16 [get_ports {arduino_a0_a13_tri_i_6}] +#set_property PACKAGE_PIN U17 [get_ports {arduino_a0_a13_tri_i_7}] +#set_property PACKAGE_PIN V17 [get_ports {arduino_a0_a13_tri_i_8}] +#set_property PACKAGE_PIN V18 [get_ports {arduino_a0_a13_tri_i_9}] +#set_property PACKAGE_PIN T16 [get_ports {arduino_a0_a13_tri_i_10}] +#set_property PACKAGE_PIN R17 [get_ports {arduino_a0_a13_tri_i_11}] +#set_property PACKAGE_PIN P18 [get_ports {arduino_a0_a13_tri_i_12}] +#set_property PACKAGE_PIN N17 [get_ports {arduino_a0_a13_tri_i_13}] +#set_property PACKAGE_PIN W18 [get_ports {raspberry_pi_tri_i_0}] +#set_property PACKAGE_PIN W19 [get_ports {raspberry_pi_tri_i_1}] +#set_property PACKAGE_PIN Y18 [get_ports {raspberry_pi_tri_i_2}] +#set_property PACKAGE_PIN Y19 [get_ports {raspberry_pi_tri_i_3}] +#set_property PACKAGE_PIN U18 [get_ports {raspberry_pi_tri_i_4}] +#set_property PACKAGE_PIN U19 [get_ports {raspberry_pi_tri_i_5}] +#set_property PACKAGE_PIN F19 [get_ports {raspberry_pi_tri_i_6}] +#set_property PACKAGE_PIN V10 [get_ports {raspberry_pi_tri_i_7}] +#set_property PACKAGE_PIN V8 [get_ports {raspberry_pi_tri_i_8}] +#set_property PACKAGE_PIN W10 [get_ports {raspberry_pi_tri_i_9}] +#set_property PACKAGE_PIN B20 [get_ports {raspberry_pi_tri_i_10}] +#set_property PACKAGE_PIN W8 [get_ports {raspberry_pi_tri_i_11}] +#set_property PACKAGE_PIN V6 [get_ports {raspberry_pi_tri_i_12}] +#set_property PACKAGE_PIN Y6 [get_ports {raspberry_pi_tri_i_13}] +#set_property PACKAGE_PIN B19 [get_ports {raspberry_pi_tri_i_14}] +#set_property PACKAGE_PIN U7 [get_ports {raspberry_pi_tri_i_15}] +#set_property PACKAGE_PIN C20 [get_ports {raspberry_pi_tri_i_16}] +#set_property PACKAGE_PIN Y8 [get_ports {raspberry_pi_tri_i_17}] +#set_property PACKAGE_PIN A20 [get_ports {raspberry_pi_tri_i_18}] +#set_property PACKAGE_PIN Y9 [get_ports {raspberry_pi_tri_i_19}] +#set_property PACKAGE_PIN U8 [get_ports {raspberry_pi_tri_i_20}] +#set_property PACKAGE_PIN W6 [get_ports {raspberry_pi_tri_i_21}] +#set_property PACKAGE_PIN Y7 [get_ports {raspberry_pi_tri_i_22}] +#set_property PACKAGE_PIN F20 [get_ports {raspberry_pi_tri_i_23}] +#set_property PACKAGE_PIN W9 [get_ports {raspberry_pi_tri_i_24}] +#set_property PACKAGE_PIN W15 [get_ports {spi_miso_i}] +#set_property PACKAGE_PIN T12 [get_ports {spi_mosi_i}] +#set_property PACKAGE_PIN H15 [get_ports {spi_sclk_i}] +#set_property PACKAGE_PIN F16 [get_ports {spi_ss_i}] +#set_property PACKAGE_PIN T19 [get_ports {hdmi_rx_hpd}] +set_property PACKAGE_PIN N18 [get_ports {TMDS_Clk_p_1}] +set_property PACKAGE_PIN P19 [get_ports {TMDS_Clk_n_1}] +set_property PACKAGE_PIN V20 [get_ports {TMDS_Data_p_1[0]}] +set_property PACKAGE_PIN T20 [get_ports {TMDS_Data_p_1[1]}] +set_property PACKAGE_PIN N20 [get_ports {TMDS_Data_p_1[2]}] +set_property PACKAGE_PIN W20 [get_ports {TMDS_Data_n_1[0]}] +set_property PACKAGE_PIN U20 [get_ports {TMDS_Data_n_1[1]}] +set_property PACKAGE_PIN P20 [get_ports {TMDS_Data_n_1[2]}] +#set_property PACKAGE_PIN R19 [get_ports {hdmi_tx_hpd}] +set_property PACKAGE_PIN L16 [get_ports {TMDS_Clk_p_0}] +set_property PACKAGE_PIN L17 [get_ports {TMDS_Clk_n_0}] +set_property PACKAGE_PIN K17 [get_ports {TMDS_Data_p_0[0]}] +set_property PACKAGE_PIN K19 [get_ports {TMDS_Data_p_0[1]}] +set_property PACKAGE_PIN J18 [get_ports {TMDS_Data_p_0[2]}] +set_property PACKAGE_PIN K18 [get_ports {TMDS_Data_n_0[0]}] +set_property PACKAGE_PIN J19 [get_ports {TMDS_Data_n_0[1]}] +set_property PACKAGE_PIN H18 [get_ports {TMDS_Data_n_0[2]}] +#set_property PACKAGE_PIN U14 [get_ports {hdmi_in_ddc_scl}] +#set_property PACKAGE_PIN U15 [get_ports {hdmi_in_ddc_sda}] +#set_property PACKAGE_PIN Y16 [get_ports {respberry_sd_i}] +#set_property PACKAGE_PIN Y17 [get_ports {respberry_sc_i}] +#set_property PACKAGE_PIN G15 [get_ports {hdmi_tx_cec}] +#set_property PACKAGE_PIN Y11 [get_ports {arduino_a0}] +#set_property PACKAGE_PIN Y12 [get_ports {arduino_a1}] +#set_property PACKAGE_PIN W11 [get_ports {arduino_a2}] +#set_property PACKAGE_PIN V11 [get_ports {arduino_a3}] +#set_property PACKAGE_PIN T5 [get_ports {arduino_a4}] +#set_property PACKAGE_PIN U10 [get_ports {arduino_a5}] + +#AU_SDA_R AU_SCL_R ADR0 ADR1 AU_MCLK_R +#set_property PACKAGE_PIN T9 [get_ports {audio_sd_i}] +#set_property PACKAGE_PIN U9 [get_ports {audio_sc_i}] +#set_property PACKAGE_PIN M17 [get_ports {audio_adr_0}] +#set_property PACKAGE_PIN M18 [get_ports {audio_adr_1}] +#set_property PACKAGE_PIN U5 [get_ports {audio_clk}] +#AU_BCLK_R AU_WCLK_R AU_DIN_R AU_DOUT_R +#set_property PACKAGE_PIN R18 [get_ports {bclk_i}] +#set_property PACKAGE_PIN T17 [get_ports {wclk_i}] +#set_property PACKAGE_PIN G18 [get_ports {sdada_out_i}] +#set_property PACKAGE_PIN F17 [get_ports {sdata_in_i}] + +#AU_SDA +#AU_SCL +#ADR0 +#ADR1 +#AU_MCLK + +#AU_BCLK +#AU_WCLK +#AU_DOUT +#AU_DIN + +set_property PACKAGE_PIN G18 [get_ports {SDATA_O}] +set_property PACKAGE_PIN F17 [get_ports {SDATA_I}] +set_property PACKAGE_PIN R18 [get_ports {BCLK_O}] +set_property PACKAGE_PIN T17 [get_ports {LRCLK_O}] +set_property PACKAGE_PIN U5 [get_ports {MCLK_O}] +set_property PACKAGE_PIN U9 [get_ports {iic_rtl_scl_io}] +set_property PACKAGE_PIN T9 [get_ports {iic_rtl_sda_io}] + +set_property IOSTANDARD LVCMOS33 [get_ports {SDATA_O}] +set_property IOSTANDARD LVCMOS33 [get_ports {SDATA_I}] +set_property IOSTANDARD LVCMOS33 [get_ports {BCLK_O}] +set_property IOSTANDARD LVCMOS33 [get_ports {LRCLK_O}] +set_property IOSTANDARD LVCMOS33 [get_ports {MCLK_O}] +set_property IOSTANDARD LVCMOS33 [get_ports {iic_rtl_scl_io}] +set_property IOSTANDARD LVCMOS33 [get_ports {iic_rtl_sda_io}] diff --git a/hdmi-in-test/xdc/timing.xdc b/hdmi-in-test/xdc/timing.xdc new file mode 100644 index 0000000..f1dcace --- /dev/null +++ b/hdmi-in-test/xdc/timing.xdc @@ -0,0 +1,6 @@ + +#create_clock -period 13.468 -waveform {0.000 5.000} [get_ports hdmi_rx_clk_p] +#from digilent datasheet. Compile OK +create_clock -period 13.468 -waveform {0.000 5.000} [get_ports TMDS_Clk_p_1] +#from pynq ref design. compile failed due to VCO issues +#create_clock -period 8.334 -waveform {0.000 4.167} [get_ports TMDS_Clk_p_1]