commented out all unnecessary zynq code
cleaned rgb_opmodule, and added counters to verify active,hsync,vsync
for some reason, vsync lasts only 5 lines.
i suspect this is wrong, but since dvi2rgb and rgb2dvi probably use the same convention, hdmi thru is
possible
however i find it confusing.
so, maybe i will focus on dvi2rgb only. Starting with simulation
added hpd fsm. not sure if compliant with the standard.
hdmi_in is the only allowed to srst the fsm.
on lock loss (e.g. resolution change)
hdmi_out is checked only after hdmi_in is locked, just once
so, if hdmi_out is disconnected, design will continue tx
design requires both FPGA .bit and PS7 .elf, to work correctly
previous commit needs both FPGA and PS7 as well.
basically connected HDMI_IN -> dvi2rgb -> rgb_op0 -> rgb2dvi -> HDMI_OUT
rgb_op0 operation:
SW0[0] | Description
0 | Normal color
1 | inverted color
can get image correctly from my laptop
This demo only needs the FPGA bit file to run (no need for vitis apparently)
moved all vitis project files to be tracked to "Blinki.files"
Blinki.files/src:
link this dir to an empty c vitis project workspac
Blinki.files/Debug:
save Debug outputs here that you want to commit.
Not necessary to recreate the project
1. i recommend to follow the same naming convention, i.e. Blinki.files
should be used in a project named "Blinki"
2. use *.vitis as vitis workspace (classic)
neyko3