Commit Graph

3 Commits (3fa8109f96b5f085fab11b0b394e02c290739361)

Author SHA1 Message Date
neyko3 3fa8109f96 hdmi-thru geneal cleanup
commented out all unnecessary zynq code
cleaned rgb_opmodule, and added counters to verify active,hsync,vsync
for some reason, vsync lasts only 5 lines.

i suspect this is wrong, but since dvi2rgb and rgb2dvi probably use the same convention, hdmi thru is
possible

however i find it confusing.

so, maybe i will focus on dvi2rgb only. Starting with simulation
2024-08-08 17:38:04 +09:00
neyko3 7a183c9aee improved hpd
added hpd fsm. not sure if compliant with the standard.

hdmi_in is the only allowed to srst the fsm.
on lock loss (e.g.  resolution change)

hdmi_out is checked only after hdmi_in is locked, just once
so, if hdmi_out is disconnected, design will continue tx

design requires both FPGA .bit and PS7 .elf, to work correctly
previous commit needs both FPGA and PS7 as well.
2024-05-24 18:11:21 +09:00
neyko3 176f5ba788 added hdmi-thru (without buffering)
basically connected HDMI_IN -> dvi2rgb -> rgb_op0 -> rgb2dvi -> HDMI_OUT

rgb_op0 operation:
 SW0[0] | Description
 0      | Normal color
 1      | inverted color

can get image correctly from my laptop

This demo only needs the FPGA bit file to run (no need for vitis apparently)
2024-05-20 16:40:30 +09:00