PYNQ-Z2_demos

Commit Graph

Author	SHA1	Message	Date
neyko3	7a183c9aee	improved hpd added hpd fsm. not sure if compliant with the standard. hdmi_in is the only allowed to srst the fsm. on lock loss (e.g. resolution change) hdmi_out is checked only after hdmi_in is locked, just once so, if hdmi_out is disconnected, design will continue tx design requires both FPGA .bit and PS7 .elf, to work correctly previous commit needs both FPGA and PS7 as well.	2024-05-24 18:11:21 +09:00
neyko3	176f5ba788	added hdmi-thru (without buffering) basically connected HDMI_IN -> dvi2rgb -> rgb_op0 -> rgb2dvi -> HDMI_OUT rgb_op0 operation: SW0[0] \| Description 0 \| Normal color 1 \| inverted color can get image correctly from my laptop This demo only needs the FPGA bit file to run (no need for vitis apparently)	2024-05-20 16:40:30 +09:00

Author

SHA1

Message

Date

neyko3

7a183c9aee

improved hpd

added hpd fsm. not sure if compliant with the standard.

hdmi_in is the only allowed to srst the fsm.
on lock loss (e.g.  resolution change)

hdmi_out is checked only after hdmi_in is locked, just once
so, if hdmi_out is disconnected, design will continue tx

design requires both FPGA .bit and PS7 .elf, to work correctly
previous commit needs both FPGA and PS7 as well.

2024-05-24 18:11:21 +09:00

neyko3

176f5ba788

added hdmi-thru (without buffering)

basically connected HDMI_IN -> dvi2rgb -> rgb_op0 -> rgb2dvi -> HDMI_OUT

rgb_op0 operation:
 SW0[0] | Description
 0      | Normal color
 1      | inverted color

can get image correctly from my laptop

This demo only needs the FPGA bit file to run (no need for vitis apparently)

2024-05-20 16:40:30 +09:00

2 Commits (7a183c9aeeda54c420fa5e624a60ec626af0f75a)