`default_nettype wire

module dvi_top(

output wire        BCLK_O,
inout  wire [14:0] DDR_addr,
inout  wire [ 2:0] DDR_ba,
inout  wire        DDR_cas_n,
inout  wire        DDR_ck_n,
inout  wire        DDR_ck_p,
inout  wire        DDR_cke,
inout  wire        DDR_cs_n,
inout  wire [ 3:0] DDR_dm,
inout  wire [31:0] DDR_dq,
inout  wire [ 3:0] DDR_dqs_n,
inout  wire [ 3:0] DDR_dqs_p,
inout  wire        DDR_odt,
inout  wire        DDR_ras_n,
inout  wire        DDR_reset_n,
inout  wire        DDR_we_n,
inout  wire        FIXED_IO_ddr_vrn,
inout  wire        FIXED_IO_ddr_vrp,
inout  wire [53:0] FIXED_IO_mio,
inout  wire        FIXED_IO_ps_clk,
inout  wire        FIXED_IO_ps_porb,
inout  wire        FIXED_IO_ps_srstb,
output wire        LRCLK_O,
output wire        MCLK_O,
input  wire        SDATA_I,
output wire        SDATA_O,
input  wire        TMDS_Clk_n_1,
input  wire        TMDS_Clk_p_1,
input  wire [2:0]  TMDS_Data_n_1,
input  wire [2:0]  TMDS_Data_p_1,
output wire        TMDS_Clk_n_0 ,
output wire        TMDS_Clk_p_0 ,
output wire [2:0]  TMDS_Data_n_0,
output wire [2:0]  TMDS_Data_p_0,
input  wire [3:0]  btns_4bits_tri_i,
inout  wire        hdmi_in_ddc_scl_io,
inout  wire        hdmi_in_ddc_sda_io,
output wire [0:0]  hdmi_rx_hpd       ,
input  wire        hdmi_tx_hpd       ,
inout  wire        iic_rtl_scl_io,
inout  wire        iic_rtl_sda_io,
output wire        leds_4bits_tri_o_3,
output wire        leds_4bits_tri_o_2,
output wire        leds_4bits_tri_o_1,
output wire        leds_4bits_tri_o_0,
input  wire        sws_2bits_tri_i_1, 
input  wire        sws_2bits_tri_i_0 
);

wire       CLK            ;
// wire       RST_BTN        ;
// wire       hdmi_tx_cec    ;
// wire       hdmi_tx_hpd    ;
// wire       hdmi_tx_rscl   ;
// wire       hdmi_tx_rsda   ;
// wire       hdmi_tx_clk_n  ;
// wire       hdmi_tx_clk_p  ;
// wire [2:0] hdmi_tx_n      ;
// wire [2:0] hdmi_tx_p      ;

blinki_bd_wrapper bd0 (
.FCLK_CLK0_0       (CLK),
.FCLK_CLK1_0       (),

//.leds_4bits_tri_io ({
.gpio_io_o_0  ({
  //leds_4bits_tri_o_3,
  1'bz,
  leds_4bits_tri_o_2,
  leds_4bits_tri_o_1,
  leds_4bits_tri_o_0
})

);

assign leds_4bits_tri_o_3 = hdmi_tx_hpd;       

display_demo_dvi u_demoDVI(
.CLK          (CLK), // board clock: 100 MHz on Arty/Basys3/Nexys
.RST_BTN      (~btns_4bits_tri_i[0]), // reset button
.hdmi_tx_cec  (), // CE control bidirectional
.hdmi_tx_hpd  (hdmi_tx_hpd       ), // hot-plug detect
.hdmi_tx_rscl (hdmi_in_ddc_scl_io), // DDC bidirectional
.hdmi_tx_rsda (hdmi_in_ddc_sda_io), // DDC bidirectional
.hdmi_tx_clk_n(TMDS_Clk_n_0      ), // HDMI clock differential negative
.hdmi_tx_clk_p(TMDS_Clk_p_0      ), // HDMI clock differential positive
.hdmi_tx_n    (TMDS_Data_n_0     ), // Three HDMI channels differential negative
.hdmi_tx_p    (TMDS_Data_p_0     ),  // Three HDMI channels differential positive
.sel ({ sws_2bits_tri_i_1, 
        sws_2bits_tri_i_0 
  })  // Three HDMI channels differential positive
);
 
endmodule