neyko3
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PYNQ-Z2_demos
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21 MiB
VHDL 37.9%
C 35%
Verilog 25.1%
Tcl 2%
 
 
 
 
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neyko3 176f5ba788 added hdmi-thru (without buffering) 
basically connected HDMI_IN -> dvi2rgb -> rgb_op0 -> rgb2dvi -> HDMI_OUT

rgb_op0 operation:
 SW0[0] | Description
 0      | Normal color
 1      | inverted color

can get image correctly from my laptop

This demo only needs the FPGA bit file to run (no need for vitis apparently)
 		2024-05-20 16:40:30 +09:00
ARM_Blinki reorganized vitis files 2024-04-16 10:41:36 +09:00
ARM_DMA added ARM_DMA demo 2024-04-16 18:12:34 +09:00
hdmi-in-test added hdmi-in (loop hdmi-out->hdmi-in) 2024-05-08 14:31:27 +09:00
hdmi-out-test added hdmi-out demo 2024-04-24 11:25:48 +09:00
hdmi-thru added hdmi-thru (without buffering) 2024-05-20 16:40:30 +09:00
.gitmodules added digilent ips as submodule 2024-04-24 11:37:00 +09:00