26 lines
705 B
Verilog
26 lines
705 B
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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// Project F: Async Reset
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// (C)2019 Will Green, Open source hardware released under the MIT License
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// Learn more at https://projectf.io
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module async_reset(
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input wire i_clk, // clock
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input wire i_rst, // reset (active high)
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output reg o_rst // output reset
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);
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(* ASYNC_REG = "TRUE" *) reg [1:0] rst_shf; // reset shift reg
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initial o_rst = 1'b1; // start off with reset asserted
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initial rst_shf = 2'b11; // and reset shift reg populated
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always @(posedge i_clk or posedge i_rst)
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if (i_rst)
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{o_rst, rst_shf} <= 3'b111;
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else
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{o_rst, rst_shf} <= {rst_shf, 1'b0};
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endmodule
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