97 lines
4.5 KiB
Verilog
97 lines
4.5 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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// Project F: Display Clocks
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// (C)2019 Will Green, Open source hardware released under the MIT License
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// Learn more at https://projectf.io
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// Defaults to 25.2 and 126 MHz for 640x480 at 60 Hz
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module display_clocks #(
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MULT_MASTER=31.5, // master clock multiplier (2.000-64.000)
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DIV_MASTER=5, // master clock divider (1-106)
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DIV_5X=5.0, // 5x clock divider (1-128)
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DIV_1X=25, // 1x clock divider (1-128)
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IN_PERIOD=10.0 // period of i_clk in ns (100 MHz = 10.0 ns)
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)
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(
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input wire i_clk, // input clock
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input wire i_rst, // reset (active high)
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output wire o_clk_1x, // pixel clock
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output wire o_clk_5x, // 5x clock for 10:1 DDR SerDes
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output wire o_locked // clock locked? (active high)
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);
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wire clk_fb; // internal clock feedback
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wire clk_1x_pre;
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wire clk_5x_pre;
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MMCME2_BASE #(
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.BANDWIDTH("OPTIMIZED"), // Jitter programming (OPTIMIZED, HIGH, LOW)
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.CLKFBOUT_MULT_F(MULT_MASTER), // Multiply value for all CLKOUT (2.000-64.000).
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.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB (-360.000-360.000).
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.CLKIN1_PERIOD(IN_PERIOD), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
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// CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128)
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.CLKOUT0_DIVIDE_F(DIV_5X), // Divide amount for CLKOUT0 (1.000-128.000).
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.CLKOUT1_DIVIDE(DIV_1X),
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.CLKOUT2_DIVIDE(1),
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.CLKOUT3_DIVIDE(1),
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.CLKOUT4_DIVIDE(1),
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.CLKOUT5_DIVIDE(1),
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.CLKOUT6_DIVIDE(1),
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// CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99).
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT6_DUTY_CYCLE(0.5),
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// CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
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.CLKOUT0_PHASE(0.0),
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.CLKOUT1_PHASE(0.0),
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.CLKOUT2_PHASE(0.0),
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.CLKOUT3_PHASE(0.0),
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.CLKOUT4_PHASE(0.0),
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.CLKOUT5_PHASE(0.0),
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.CLKOUT6_PHASE(0.0),
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.CLKOUT4_CASCADE("FALSE"), // Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE)
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.DIVCLK_DIVIDE(DIV_MASTER), // Master division value (1-106)
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.REF_JITTER1(0.010), // Reference input jitter in UI (0.000-0.999).
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.STARTUP_WAIT("FALSE") // Delays DONE until MMCM is locked (FALSE, TRUE)
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)
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MMCME2_BASE_inst (
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/* verilator lint_off PINCONNECTEMPTY */
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// Clock Outputs: 1-bit (each) output: User configurable clock outputs
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.CLKOUT0(clk_5x_pre), // 1-bit output: CLKOUT0
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.CLKOUT0B(), // 1-bit output: Inverted CLKOUT0
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.CLKOUT1(clk_1x_pre), // 1-bit output: CLKOUT1
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.CLKOUT1B(), // 1-bit output: Inverted CLKOUT1
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.CLKOUT2(), // 1-bit output: CLKOUT2
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.CLKOUT2B(), // 1-bit output: Inverted CLKOUT2
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.CLKOUT3(), // 1-bit output: CLKOUT3
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.CLKOUT3B(), // 1-bit output: Inverted CLKOUT3
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.CLKOUT4(), // 1-bit output: CLKOUT4
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.CLKOUT5(), // 1-bit output: CLKOUT5
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.CLKOUT6(), // 1-bit output: CLKOUT6
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// Feedback Clocks: 1-bit (each) output: Clock feedback ports
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.CLKFBOUT(clk_fb), // 1-bit output: Feedback clock
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.CLKFBOUTB(), // 1-bit output: Inverted CLKFBOUT
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// Status Ports: 1-bit (each) output: MMCM status ports
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.LOCKED(o_locked), // 1-bit output: LOCK
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// Clock Inputs: 1-bit (each) input: Clock input
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.CLKIN1(i_clk), // 1-bit input: Clock
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// Control Ports: 1-bit (each) input: MMCM control ports
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.PWRDWN(), // 1-bit input: Power-down
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/* verilator lint_on PINCONNECTEMPTY */
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.RST(i_rst), // 1-bit input: Reset
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// Feedback Clocks: 1-bit (each) input: Clock feedback ports
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.CLKFBIN(clk_fb) // 1-bit input: Feedback clock
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);
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// explicitly buffer output clocks
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BUFG bufg_clk_pix(.I(clk_1x_pre), .O(o_clk_1x));
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BUFG bufg_clk_pix_5x(.I(clk_5x_pre), .O(o_clk_5x));
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endmodule
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