81 lines
3.3 KiB
Verilog
81 lines
3.3 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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// Project F: Display Timings
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// (C)2019 Will Green, Open Source Hardware released under the MIT License
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// Learn more at https://projectf.io
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// Defaults to 640x480 at 60 Hz
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module display_timings #(
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H_RES=640, // horizontal resolution (pixels)
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V_RES=480, // vertical resolution (lines)
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H_FP=16, // horizontal front porch
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H_SYNC=96, // horizontal sync
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H_BP=48, // horizontal back porch
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V_FP=10, // vertical front porch
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V_SYNC=2, // vertical sync
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V_BP=33, // vertical back porch
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H_POL=0, // horizontal sync polarity (0:neg, 1:pos)
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V_POL=0 // vertical sync polarity (0:neg, 1:pos)
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)
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(
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input wire i_pix_clk, // pixel clock
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input wire i_rst, // reset: restarts frame (active high)
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output wire o_hs, // horizontal sync
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output wire o_vs, // vertical sync
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output wire o_de, // display enable: high during active video
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output wire o_frame, // high for one tick at the start of each frame
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output reg signed [15:0] o_sx, // horizontal beam position (including blanking)
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output reg signed [15:0] o_sy // vertical beam position (including blanking)
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);
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// Horizontal: sync, active, and pixels
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localparam signed H_STA = 0 - H_FP - H_SYNC - H_BP; // horizontal start
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localparam signed HS_STA = H_STA + H_FP; // sync start
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localparam signed HS_END = HS_STA + H_SYNC; // sync end
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localparam signed HA_STA = 0; // active start
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localparam signed HA_END = H_RES - 1; // active end
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// Vertical: sync, active, and pixels
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localparam signed V_STA = 0 - V_FP - V_SYNC - V_BP; // vertical start
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localparam signed VS_STA = V_STA + V_FP; // sync start
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localparam signed VS_END = VS_STA + V_SYNC; // sync end
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localparam signed VA_STA = 0; // active start
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localparam signed VA_END = V_RES - 1; // active end
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// generate sync signals with correct polarity
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assign o_hs = H_POL ? (o_sx > HS_STA && o_sx <= HS_END)
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: ~(o_sx > HS_STA && o_sx <= HS_END);
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assign o_vs = V_POL ? (o_sy > VS_STA && o_sy <= VS_END)
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: ~(o_sy > VS_STA && o_sy <= VS_END);
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// display enable: high during active period
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assign o_de = (o_sx >= 0 && o_sy >= 0);
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// o_frame: high for one tick at the start of each frame
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assign o_frame = (o_sy == V_STA && o_sx == H_STA);
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always @ (posedge i_pix_clk)
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begin
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if (i_rst) // reset to start of frame
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begin
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o_sx <= H_STA;
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o_sy <= V_STA;
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end
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else
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begin
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if (o_sx == HA_END) // end of line
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begin
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o_sx <= H_STA;
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if (o_sy == VA_END) // end of frame
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o_sy <= V_STA;
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else
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o_sy <= o_sy + 16'sh1;
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end
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else
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o_sx <= o_sx + 16'sh1;
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end
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end
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endmodule
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