100 lines
2.9 KiB
Verilog
100 lines
2.9 KiB
Verilog
`default_nettype wire
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module dvi_top(
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output wire BCLK_O,
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inout wire [14:0] DDR_addr,
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inout wire [ 2:0] DDR_ba,
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inout wire DDR_cas_n,
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inout wire DDR_ck_n,
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inout wire DDR_ck_p,
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inout wire DDR_cke,
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inout wire DDR_cs_n,
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inout wire [ 3:0] DDR_dm,
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inout wire [31:0] DDR_dq,
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inout wire [ 3:0] DDR_dqs_n,
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inout wire [ 3:0] DDR_dqs_p,
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inout wire DDR_odt,
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inout wire DDR_ras_n,
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inout wire DDR_reset_n,
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inout wire DDR_we_n,
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inout wire FIXED_IO_ddr_vrn,
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inout wire FIXED_IO_ddr_vrp,
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inout wire [53:0] FIXED_IO_mio,
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inout wire FIXED_IO_ps_clk,
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inout wire FIXED_IO_ps_porb,
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inout wire FIXED_IO_ps_srstb,
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output wire LRCLK_O,
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output wire MCLK_O,
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input wire SDATA_I,
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output wire SDATA_O,
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input wire TMDS_Clk_n_1,
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input wire TMDS_Clk_p_1,
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input wire [2:0] TMDS_Data_n_1,
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input wire [2:0] TMDS_Data_p_1,
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output wire TMDS_Clk_n_0 ,
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output wire TMDS_Clk_p_0 ,
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output wire [2:0] TMDS_Data_n_0,
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output wire [2:0] TMDS_Data_p_0,
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input wire [3:0] btns_4bits_tri_i,
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inout wire hdmi_in_ddc_scl_io,
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inout wire hdmi_in_ddc_sda_io,
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output wire [0:0] hdmi_rx_hpd ,
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input wire hdmi_tx_hpd ,
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inout wire iic_rtl_scl_io,
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inout wire iic_rtl_sda_io,
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output wire leds_4bits_tri_o_3,
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output wire leds_4bits_tri_o_2,
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output wire leds_4bits_tri_o_1,
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output wire leds_4bits_tri_o_0,
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input wire sws_2bits_tri_i_1,
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input wire sws_2bits_tri_i_0
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);
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wire CLK ;
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// wire RST_BTN ;
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// wire hdmi_tx_cec ;
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// wire hdmi_tx_hpd ;
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// wire hdmi_tx_rscl ;
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// wire hdmi_tx_rsda ;
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// wire hdmi_tx_clk_n ;
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// wire hdmi_tx_clk_p ;
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// wire [2:0] hdmi_tx_n ;
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// wire [2:0] hdmi_tx_p ;
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blinki_bd_wrapper bd0 (
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.FCLK_CLK0_0 (CLK),
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.FCLK_CLK1_0 (),
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//.leds_4bits_tri_io ({
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.gpio_io_o_0 ({
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//leds_4bits_tri_o_3,
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1'bz,
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leds_4bits_tri_o_2,
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leds_4bits_tri_o_1,
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leds_4bits_tri_o_0
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})
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);
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assign leds_4bits_tri_o_3 = hdmi_tx_hpd;
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display_demo_dvi u_demoDVI(
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.CLK (CLK), // board clock: 100 MHz on Arty/Basys3/Nexys
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.RST_BTN (~btns_4bits_tri_i[0]), // reset button
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.hdmi_tx_cec (), // CE control bidirectional
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.hdmi_tx_hpd (hdmi_tx_hpd ), // hot-plug detect
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.hdmi_tx_rscl (hdmi_in_ddc_scl_io), // DDC bidirectional
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.hdmi_tx_rsda (hdmi_in_ddc_sda_io), // DDC bidirectional
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.hdmi_tx_clk_n(TMDS_Clk_n_0 ), // HDMI clock differential negative
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.hdmi_tx_clk_p(TMDS_Clk_p_0 ), // HDMI clock differential positive
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.hdmi_tx_n (TMDS_Data_n_0 ), // Three HDMI channels differential negative
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.hdmi_tx_p (TMDS_Data_p_0 ), // Three HDMI channels differential positive
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.sel ({ sws_2bits_tri_i_1,
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sws_2bits_tri_i_0
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}) // Three HDMI channels differential positive
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);
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endmodule
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