118 lines
5.1 KiB
Verilog
118 lines
5.1 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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// Project F: Display 10:1 Serializer
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// (C)2019 Will Green, Open source hardware released under the MIT License
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// Learn more at https://projectf.io
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module serializer_10to1(
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input wire i_clk, // parallel clock
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input wire i_clk_hs, // high-speed clock (5 x i_clk when using DDR)
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input wire i_rst_oserdes, // reset from async reset (active high)
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input wire [9:0] i_data, // input parallel data
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output wire o_data // output serial data
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);
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// use two OSERDES2 to serialize 10-bit TMDS data
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wire shift1, shift2; // wires between oserdes master and slave
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OSERDESE2 #(
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.DATA_RATE_OQ("DDR"), // DDR, SDR
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.DATA_RATE_TQ("SDR"), // DDR, BUF, SDR
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.DATA_WIDTH(10), // Parallel data width (2-8,10,14)
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.INIT_OQ(1'b1), // Initial value of OQ output (1'b0,1'b1)
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.INIT_TQ(1'b1), // Initial value of TQ output (1'b0,1'b1)
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.SERDES_MODE("MASTER"), // MASTER, SLAVE
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.SRVAL_OQ(1'b0), // OQ output value when SR is used (1'b0,1'b1)
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.SRVAL_TQ(1'b0), // TQ output value when SR is used (1'b0,1'b1)
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.TBYTE_CTL("FALSE"), // Enable tristate byte operation (FALSE, TRUE)
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.TBYTE_SRC("FALSE"), // Tristate byte source (FALSE, TRUE)
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.TRISTATE_WIDTH(1) // 3-state converter width (1,4)
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)
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master10 (
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/* verilator lint_off PINCONNECTEMPTY */
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.OFB(), // 1-bit output: Feedback path for data
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.OQ(o_data), // 1-bit output: Data path output
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// SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
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.SHIFTOUT1(),
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.SHIFTOUT2(),
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.TBYTEOUT(), // 1-bit output: Byte group tristate
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.TFB(), // 1-bit output: 3-state control
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.TQ(), // 1-bit output: 3-state control
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.CLK(i_clk_hs), // 1-bit input: High speed clock
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.CLKDIV(i_clk), // 1-bit input: Divided clock
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/* verilator lint_on PINCONNECTEMPTY */
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// D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
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.D1(i_data[0]),
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.D2(i_data[1]),
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.D3(i_data[2]),
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.D4(i_data[3]),
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.D5(i_data[4]),
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.D6(i_data[5]),
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.D7(i_data[6]),
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.D8(i_data[7]),
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.OCE(1'b1), // 1-bit input: Output data clock enable
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.RST(i_rst_oserdes), // 1-bit input: Reset
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// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
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.SHIFTIN1(shift1),
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.SHIFTIN2(shift2),
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// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
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.T1(1'b0),
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.T2(1'b0),
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.T3(1'b0),
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.T4(1'b0),
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.TBYTEIN(1'b0), // 1-bit input: Byte group tristate
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.TCE(1'b0) // 1-bit input: 3-state clock enable
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);
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OSERDESE2 #(
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.DATA_RATE_OQ("DDR"), // DDR, SDR
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.DATA_RATE_TQ("SDR"), // DDR, BUF, SDR
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.DATA_WIDTH(10), // Parallel data width (2-8,10,14)
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.INIT_OQ(1'b1), // Initial value of OQ output (1'b0,1'b1)
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.INIT_TQ(1'b1), // Initial value of TQ output (1'b0,1'b1)
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.SERDES_MODE("SLAVE"), // MASTER, SLAVE
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.SRVAL_OQ(1'b0), // OQ output value when SR is used (1'b0,1'b1)
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.SRVAL_TQ(1'b0), // TQ output value when SR is used (1'b0,1'b1)
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.TBYTE_CTL("FALSE"), // Enable tristate byte operation (FALSE, TRUE)
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.TBYTE_SRC("FALSE"), // Tristate byte source (FALSE, TRUE)
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.TRISTATE_WIDTH(1) // 3-state converter width (1,4)
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)
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slave10 (
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/* verilator lint_off PINCONNECTEMPTY */
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.OFB(), // 1-bit output: Feedback path for data
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.OQ(), // 1-bit output: Data path output
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// SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
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.SHIFTOUT1(shift1),
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.SHIFTOUT2(shift2),
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.TBYTEOUT(), // 1-bit output: Byte group tristate
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.TFB(), // 1-bit output: 3-state control
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.TQ(), // 1-bit output: 3-state control
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.CLK(i_clk_hs), // 1-bit input: High speed clock
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.CLKDIV(i_clk), // 1-bit input: Divided clock
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/* verilator lint_on PINCONNECTEMPTY */
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// D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
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.D1(1'b0),
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.D2(1'b0),
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.D3(i_data[8]),
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.D4(i_data[9]),
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.D5(1'b0),
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.D6(1'b0),
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.D7(1'b0),
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.D8(1'b0),
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.OCE(1'b1), // 1-bit input: Output data clock enable
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.RST(i_rst_oserdes), // 1-bit input: Reset
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// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
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.SHIFTIN1(1'b0),
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.SHIFTIN2(1'b0),
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// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
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.T1(1'b0),
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.T2(1'b0),
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.T3(1'b0),
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.T4(1'b0),
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.TBYTEIN(1'b0), // 1-bit input: Byte group tristate
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.TCE(1'b0) // 1-bit input: 3-state clock enable
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);
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endmodule
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