32 lines
1.1 KiB
Verilog
32 lines
1.1 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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// Project F: Display Controller Simple Test Card
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// (C)2019 Will Green, Open Source Hardware released under the MIT License
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// Learn more at https://projectf.io
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module test_card_simple #(H_RES=640) (
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input wire signed [15:0] i_x,
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output wire [7:0] o_red,
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output wire [7:0] o_green,
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output wire [7:0] o_blue
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);
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localparam HW = H_RES >> 3; // horizontal colour width = H_RES / 8
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// Bands
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wire b0 = (i_x >= 0 ) & (i_x < HW );
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wire b1 = (i_x >= HW ) & (i_x < HW * 2);
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wire b2 = (i_x >= HW * 2) & (i_x < HW * 3);
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wire b3 = (i_x >= HW * 3) & (i_x < HW * 4);
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wire b4 = (i_x >= HW * 4) & (i_x < HW * 5);
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wire b5 = (i_x >= HW * 5) & (i_x < HW * 6);
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wire b6 = (i_x >= HW * 6) & (i_x < HW * 7);
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wire b7 = (i_x >= HW * 7) & (i_x < HW * 8);
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// Colour Output
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assign o_red = {8{b0 | b1 | b5}} + {2'b0,{6{b6}}} + {b7, 7'b0};
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assign o_green = {8{b1 | b2 | b3}} + {2'b0,{6{b6}}} + {b7, 7'b0};
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assign o_blue = {8{b3 | b4 | b5}} + {2'b0,{6{b6}}} + {b7, 7'b0};
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endmodule
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