73 lines
2.2 KiB
Verilog
73 lines
2.2 KiB
Verilog
module rgb_op0(
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(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 iV ACTIVE_VIDEO" *) input wire iRGB_ACTIVE,
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(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 iV DATA" *) input wire [23:0]iRGB_DATA ,
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(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 iV HSYNC" *) input wire iRGB_HSYNC ,
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(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 iV VSYNC" *) input wire iRGB_VSYNC ,
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(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 iV VSYNC" *) input wire [1:0] isel,
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(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 oV ACTIVE_VIDEO" *) output wire oRGB_ACTIVE,
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(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 oV DATA" *) output wire [23:0]oRGB_DATA ,
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(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 oV HSYNC" *) output wire oRGB_HSYNC ,
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(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 oV VSYNC" *) output wire oRGB_VSYNC
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,
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input wire hdmi_in_aPixelClkLckd,
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input wire hdmi_out_aPixelClkLckd,
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output wire hdmi_in_arst ,
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output wire hdmi_out_arst,
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input wire clk,
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input wire tx_hpd,
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output wire rx_hpd
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);
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assign oRGB_ACTIVE = iRGB_ACTIVE;
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//assign oRGB_DATA = iRGB_DATA ;
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assign oRGB_DATA[8*0+:8] =(isel[0])? ~iRGB_DATA[8*0+:8] : iRGB_DATA[8*0+:8];
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assign oRGB_DATA[8*1+:8] =(isel[0])? ~iRGB_DATA[8*1+:8] : iRGB_DATA[8*1+:8];
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assign oRGB_DATA[8*2+:8] =(isel[0])? ~iRGB_DATA[8*2+:8] : iRGB_DATA[8*2+:8];
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assign oRGB_HSYNC = iRGB_HSYNC ;
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assign oRGB_VSYNC = iRGB_VSYNC ;
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reg [ 7:0] r_hpd_fsm0=0;
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always@(posedge clk) begin
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r_hpd_fsm0 <=
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//delay done. check if hdmi_in is still locked
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(&r_hpd_fsm0 && hdmi_in_aPixelClkLckd )? r_hpd_fsm0:
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//if not locked goto 0 (retry)
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(&r_hpd_fsm0 )? 0:
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//start
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(r_hpd_fsm0==0 )? 1:
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//waits for hdmi_in
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(r_hpd_fsm0==1 && hdmi_in_aPixelClkLckd )? 2:
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//waits for hdmi_out
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(r_hpd_fsm0==2 && hdmi_out_aPixelClkLckd && tx_hpd)? 3:
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//delay, so that retry is not so quick
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(r_hpd_fsm0>=3 )? r_hpd_fsm0+1:
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r_hpd_fsm0;
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end
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assign hdmi_in_arst = (r_hpd_fsm0>=1)? 0: 1;
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assign rx_hpd = (r_hpd_fsm0>=1)? 1: 0;
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assign hdmi_out_arst = (r_hpd_fsm0>=2)? 0: 1;
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endmodule
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