forked from FPGALover/RISCV_picorv32_fpga
13 lines
547 B
Plaintext
13 lines
547 B
Plaintext
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<?xml version="1.0" encoding="UTF-8" ?>
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<!DOCTYPE pinplan>
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<pinplan intended_family="Cyclone IV E" variation_name="pll_sys" megafunction_name="ALTPLL" specifies="all_ports">
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<global>
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<pin name="inclk0" direction="input" scope="external" source="clock" />
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<pin name="c0" direction="output" scope="external" source="clock" />
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<pin name="c1" direction="output" scope="external" source="clock" />
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<pin name="c2" direction="output" scope="external" source="clock" />
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<pin name="locked" direction="output" scope="external" />
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</global>
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</pinplan>
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