forked from FPGALover/RISCV_picorv32_fpga
37 lines
689 B
Coq
37 lines
689 B
Coq
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`include "timescale.vh"
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module xoroshiro128plus_tb;
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/* Make a reset that pulses low once. */
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reg reset = 1;
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initial begin
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/* verilator lint_off STMTDLY */
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# 1 reset = 0;
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# 1 reset = 1;
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/* verilator lint_on STMTDLY */
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end
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/* Make a regular pulsing clock. */
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reg clk = 0;
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/* verilator lint_off STMTDLY */
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always #5
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/* verilator lint_on STMTDLY */
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begin
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clk = !clk;
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end
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wire [62:0] x;
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wire [32*16 - 1 : 0] y;
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always @ (posedge clk)
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begin
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$write ("%h\n%h\n", y[31:0], y[63:32]);
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end
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rnd r1 (.resn(reset), .clk(clk), .out(x));
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shuff s1 (.x(x), .out(y));
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endmodule
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