forked from FPGALover/RISCV_picorv32_fpga
63 lines
1.8 KiB
Python
63 lines
1.8 KiB
Python
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#!/usr/bin/python3
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#
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# makebin.py
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#
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# Prepares memory initialization files for the Verilog readmemb() functions generated by SpinalHDL.
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#
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# Input: A memory image file, hexadecimal, one 32 bit memory location per line.
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#
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# Output: Four, byte wide, symbol files in binary.
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#
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# The memory image file in hexadecimal, one 32 bit location content per line.
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import os
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import platform
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os_p = platform.system()
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file_dir = os.path.dirname(os.path.realpath('__file__'))
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joiner='';
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if(os_p=="Linux"):
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joiner="/";
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else:
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joiner="\\";
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hexFileName = os.path.join(file_dir, 'firmware'+joiner+'firmware.hex')
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# The binary symbol (byte) output files
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outFileName0 = os.path.join(file_dir, "firmware"+joiner+"Memory.v_toplevel_memory_1_symbol0.bin")
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outFileName1 = os.path.join(file_dir, "firmware"+joiner+"Memory.v_toplevel_memory_1_symbol1.bin")
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outFileName2 = os.path.join(file_dir, "firmware"+joiner+"Memory.v_toplevel_memory_1_symbol2.bin")
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outFileName3 = os.path.join(file_dir, "firmware"+joiner+"Memory.v_toplevel_memory_1_symbol3.bin")
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hexFile = open(hexFileName, "r")
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outFile0 = open(outFileName0, "w+")
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outFile1 = open(outFileName1, "w+")
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outFile2 = open(outFileName2, "w+")
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outFile3 = open(outFileName3, "w+")
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# Read memory location values one per line
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for line in hexFile:
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# Convert to 32 bit integer
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data = int(line, 16)
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# Split into 4 bytes
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byte0 = (data >> 0) & 0xFF
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byte1 = (data >> 8) & 0xFF
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byte2 = (data >> 16) & 0xFF
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byte3 = (data >> 24) & 0xFF
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# Write symbol ouptut files, one byte in binary per line
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outFile0.write(format(byte0, '08b') + '\n')
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outFile1.write(format(byte1, '08b') + '\n')
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outFile2.write(format(byte2, '08b') + '\n')
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outFile3.write(format(byte3, '08b') + '\n')
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# Close up the shop.
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outFile0.close()
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outFile1.close()
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outFile2.close()
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outFile3.close()
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