forked from FPGALover/RISCV_picorv32_fpga
missing files
parent
f5aa83f86e
commit
9acee30565
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Assembler report for xoro
|
||||
Sat Sep 16 21:12:47 2023
|
||||
Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Web Edition
|
||||
|
||||
|
||||
---------------------
|
||||
; Table of Contents ;
|
||||
---------------------
|
||||
1. Legal Notice
|
||||
2. Assembler Summary
|
||||
3. Assembler Settings
|
||||
4. Assembler Generated Files
|
||||
5. Assembler Device Options: E:/Photonic/RISCV/output_files/xoro.sof
|
||||
6. Assembler Messages
|
||||
|
||||
|
||||
|
||||
----------------
|
||||
; Legal Notice ;
|
||||
----------------
|
||||
Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, the Altera Quartus II License Agreement,
|
||||
the Altera MegaCore Function License Agreement, or other
|
||||
applicable license agreement, including, without limitation,
|
||||
that your use is for the sole purpose of programming logic
|
||||
devices manufactured by Altera and sold by Altera or its
|
||||
authorized distributors. Please refer to the applicable
|
||||
agreement for further details.
|
||||
|
||||
|
||||
|
||||
+---------------------------------------------------------------+
|
||||
; Assembler Summary ;
|
||||
+-----------------------+---------------------------------------+
|
||||
; Assembler Status ; Successful - Sat Sep 16 21:12:47 2023 ;
|
||||
; Revision Name ; xoro ;
|
||||
; Top-level Entity Name ; xoro_top ;
|
||||
; Family ; Cyclone IV E ;
|
||||
; Device ; EP4CE22F17C6 ;
|
||||
+-----------------------+---------------------------------------+
|
||||
|
||||
|
||||
+----------------------------------+
|
||||
; Assembler Settings ;
|
||||
+--------+---------+---------------+
|
||||
; Option ; Setting ; Default Value ;
|
||||
+--------+---------+---------------+
|
||||
|
||||
|
||||
+-----------------------------------------+
|
||||
; Assembler Generated Files ;
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||||
+-----------------------------------------+
|
||||
; File Name ;
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||||
+-----------------------------------------+
|
||||
; E:/Photonic/RISCV/output_files/xoro.sof ;
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+-----------------------------------------+
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||||
|
||||
|
||||
+-------------------------------------------------------------------+
|
||||
; Assembler Device Options: E:/Photonic/RISCV/output_files/xoro.sof ;
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||||
+----------------+--------------------------------------------------+
|
||||
; Option ; Setting ;
|
||||
+----------------+--------------------------------------------------+
|
||||
; Device ; EP4CE22F17C6 ;
|
||||
; JTAG usercode ; 0x00425C9B ;
|
||||
; Checksum ; 0x00425C9B ;
|
||||
+----------------+--------------------------------------------------+
|
||||
|
||||
|
||||
+--------------------+
|
||||
; Assembler Messages ;
|
||||
+--------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II 64-Bit Assembler
|
||||
Info: Version 15.0.0 Build 145 04/22/2015 SJ Web Edition
|
||||
Info: Processing started: Sat Sep 16 21:12:46 2023
|
||||
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off xoro -c xoro
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||||
Info (115031): Writing out detailed assembly data for power analysis
|
||||
Info (115030): Assembler is generating device programming files
|
||||
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 4761 megabytes
|
||||
Info: Processing ended: Sat Sep 16 21:12:47 2023
|
||||
Info: Elapsed time: 00:00:01
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
|
||||
|
||||
|
|
@ -0,0 +1 @@
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|||
Sat Sep 16 21:12:48 2023
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,6 @@
|
|||
Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
|
||||
Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
|
||||
Extra Info (176236): Started Fast Input/Output/OE register processing
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||||
Extra Info (176237): Finished Fast Input/Output/OE register processing
|
||||
Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
|
||||
Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
|
||||
|
|
@ -0,0 +1,16 @@
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Fitter Status : Successful - Sat Sep 16 21:12:44 2023
|
||||
Quartus II 64-Bit Version : 15.0.0 Build 145 04/22/2015 SJ Web Edition
|
||||
Revision Name : xoro
|
||||
Top-level Entity Name : xoro_top
|
||||
Family : Cyclone IV E
|
||||
Device : EP4CE22F17C6
|
||||
Timing Models : Final
|
||||
Total logic elements : 2,973 / 22,320 ( 13 % )
|
||||
Total combinational functions : 2,743 / 22,320 ( 12 % )
|
||||
Dedicated logic registers : 1,354 / 22,320 ( 6 % )
|
||||
Total registers : 1354
|
||||
Total pins : 46 / 154 ( 30 % )
|
||||
Total virtual pins : 0
|
||||
Total memory bits : 330,016 / 608,256 ( 54 % )
|
||||
Embedded Multiplier 9-bit elements : 8 / 132 ( 6 % )
|
||||
Total PLLs : 1 / 4 ( 25 % )
|
||||
|
|
@ -0,0 +1,129 @@
|
|||
Flow report for xoro
|
||||
Sat Sep 16 21:12:47 2023
|
||||
Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Web Edition
|
||||
|
||||
|
||||
---------------------
|
||||
; Table of Contents ;
|
||||
---------------------
|
||||
1. Legal Notice
|
||||
2. Flow Summary
|
||||
3. Flow Settings
|
||||
4. Flow Non-Default Global Settings
|
||||
5. Flow Elapsed Time
|
||||
6. Flow OS Summary
|
||||
7. Flow Log
|
||||
8. Flow Messages
|
||||
9. Flow Suppressed Messages
|
||||
|
||||
|
||||
|
||||
----------------
|
||||
; Legal Notice ;
|
||||
----------------
|
||||
Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, the Altera Quartus II License Agreement,
|
||||
the Altera MegaCore Function License Agreement, or other
|
||||
applicable license agreement, including, without limitation,
|
||||
that your use is for the sole purpose of programming logic
|
||||
devices manufactured by Altera and sold by Altera or its
|
||||
authorized distributors. Please refer to the applicable
|
||||
agreement for further details.
|
||||
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+------------------------------------+--------------------------------------------+
|
||||
; Flow Status ; Successful - Sat Sep 16 21:12:47 2023 ;
|
||||
; Quartus II 64-Bit Version ; 15.0.0 Build 145 04/22/2015 SJ Web Edition ;
|
||||
; Revision Name ; xoro ;
|
||||
; Top-level Entity Name ; xoro_top ;
|
||||
; Family ; Cyclone IV E ;
|
||||
; Device ; EP4CE22F17C6 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 2,973 / 22,320 ( 13 % ) ;
|
||||
; Total combinational functions ; 2,743 / 22,320 ( 12 % ) ;
|
||||
; Dedicated logic registers ; 1,354 / 22,320 ( 6 % ) ;
|
||||
; Total registers ; 1354 ;
|
||||
; Total pins ; 46 / 154 ( 30 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; Total memory bits ; 330,016 / 608,256 ( 54 % ) ;
|
||||
; Embedded Multiplier 9-bit elements ; 8 / 132 ( 6 % ) ;
|
||||
; Total PLLs ; 1 / 4 ( 25 % ) ;
|
||||
+------------------------------------+--------------------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------+
|
||||
; Flow Settings ;
|
||||
+-------------------+---------------------+
|
||||
; Option ; Setting ;
|
||||
+-------------------+---------------------+
|
||||
; Start date & time ; 09/16/2023 21:12:15 ;
|
||||
; Main task ; Compilation ;
|
||||
; Revision Name ; xoro ;
|
||||
+-------------------+---------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------------------+
|
||||
; Flow Non-Default Global Settings ;
|
||||
+-------------------------------------+---------------------------------------+---------------+-------------+------------+
|
||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||
+-------------------------------------+---------------------------------------+---------------+-------------+------------+
|
||||
; COMPILER_SIGNATURE_ID ; 101728417602065.169492393530232 ; -- ; -- ; -- ;
|
||||
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
||||
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
|
||||
; MISC_FILE ; qram32_inst.v ; -- ; -- ; -- ;
|
||||
; MISC_FILE ; qram32_bb.v ; -- ; -- ; -- ;
|
||||
; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ;
|
||||
; NUM_PARALLEL_PROCESSORS ; 2 ; -- ; -- ; -- ;
|
||||
; PARTITION_COLOR ; 16764057 ; -- ; xoro_top ; Top ;
|
||||
; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; xoro_top ; Top ;
|
||||
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; xoro_top ; Top ;
|
||||
; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
|
||||
; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
|
||||
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
|
||||
; TOP_LEVEL_ENTITY ; xoro_top ; xoro ; -- ; -- ;
|
||||
; VERILOG_INPUT_VERSION ; SystemVerilog_2005 ; Verilog_2001 ; -- ; -- ;
|
||||
; VERILOG_SHOW_LMF_MAPPING_MESSAGES ; Off ; -- ; -- ; -- ;
|
||||
+-------------------------------------+---------------------------------------+---------------+-------------+------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------------+
|
||||
; Flow Elapsed Time ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Analysis & Synthesis ; 00:00:13 ; 1.0 ; 4859 MB ; 00:00:10 ;
|
||||
; Fitter ; 00:00:15 ; 1.4 ; 5429 MB ; 00:00:09 ;
|
||||
; Assembler ; 00:00:01 ; 1.0 ; 4761 MB ; 00:00:01 ;
|
||||
; Total ; 00:00:29 ; -- ; -- ; 00:00:20 ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------+
|
||||
; Flow OS Summary ;
|
||||
+----------------------+------------------+-----------+------------+----------------+
|
||||
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
|
||||
+----------------------+------------------+-----------+------------+----------------+
|
||||
; Analysis & Synthesis ; DESKTOP-5FH9OH3 ; Windows 7 ; 6.2 ; x86_64 ;
|
||||
; Fitter ; DESKTOP-5FH9OH3 ; Windows 7 ; 6.2 ; x86_64 ;
|
||||
; Assembler ; DESKTOP-5FH9OH3 ; Windows 7 ; 6.2 ; x86_64 ;
|
||||
+----------------------+------------------+-----------+------------+----------------+
|
||||
|
||||
|
||||
------------
|
||||
; Flow Log ;
|
||||
------------
|
||||
quartus_map --read_settings_files=on --write_settings_files=off xoro -c xoro
|
||||
quartus_fit --read_settings_files=off --write_settings_files=off xoro -c xoro
|
||||
quartus_asm --read_settings_files=off --write_settings_files=off xoro -c xoro
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
<sld_project_info>
|
||||
<project>
|
||||
<hash md5_digest_80b="7a39fa13c40e9d017722"/>
|
||||
</project>
|
||||
<file_info>
|
||||
<file device="EP4CE22F17C6" path="xoro.sof" usercode="0xFFFFFFFF"/>
|
||||
</file_info>
|
||||
</sld_project_info>
|
||||
File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,23 @@
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|||
Warning (10273): Verilog HDL warning at picorv32.v(284): extended using "x" or "z"
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||||
Warning (10273): Verilog HDL warning at picorv32.v(304): extended using "x" or "z"
|
||||
Warning (10273): Verilog HDL warning at picorv32.v(311): extended using "x" or "z"
|
||||
Warning (10273): Verilog HDL warning at picorv32.v(370): extended using "x" or "z"
|
||||
Warning (10273): Verilog HDL warning at picorv32.v(372): extended using "x" or "z"
|
||||
Warning (10273): Verilog HDL warning at picorv32.v(1020): extended using "x" or "z"
|
||||
Warning (10273): Verilog HDL warning at picorv32.v(1229): extended using "x" or "z"
|
||||
Warning (10273): Verilog HDL warning at picorv32.v(1246): extended using "x" or "z"
|
||||
Warning (10273): Verilog HDL warning at picorv32.v(1290): extended using "x" or "z"
|
||||
Warning (10273): Verilog HDL warning at picorv32.v(1322): extended using "x" or "z"
|
||||
Warning (10273): Verilog HDL warning at picorv32.v(1377): extended using "x" or "z"
|
||||
Warning (10273): Verilog HDL warning at picorv32.v(1378): extended using "x" or "z"
|
||||
Warning (10273): Verilog HDL warning at picorv32.v(1390): extended using "x" or "z"
|
||||
Warning (10273): Verilog HDL warning at picorv32.v(1391): extended using "x" or "z"
|
||||
Warning (10273): Verilog HDL warning at picorv32.v(1409): extended using "x" or "z"
|
||||
Warning (10273): Verilog HDL warning at picorv32.v(1410): extended using "x" or "z"
|
||||
Warning (10273): Verilog HDL warning at picorv32.v(1413): extended using "x" or "z"
|
||||
Warning (10273): Verilog HDL warning at picorv32.v(1434): extended using "x" or "z"
|
||||
Warning (10273): Verilog HDL warning at picorv32.v(1559): extended using "x" or "z"
|
||||
Warning (10273): Verilog HDL warning at picorv32.v(1560): extended using "x" or "z"
|
||||
Warning (10273): Verilog HDL warning at picorv32.v(1946): extended using "x" or "z"
|
||||
Warning (10268): Verilog HDL information at picorv32.v(1375): always construct contains both blocking and non-blocking assignments
|
||||
Warning (10273): Verilog HDL warning at picorv32.v(2397): extended using "x" or "z"
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
Analysis & Synthesis Status : Successful - Sat Sep 16 21:12:28 2023
|
||||
Quartus II 64-Bit Version : 15.0.0 Build 145 04/22/2015 SJ Web Edition
|
||||
Revision Name : xoro
|
||||
Top-level Entity Name : xoro_top
|
||||
Family : Cyclone IV E
|
||||
Total logic elements : 3,155
|
||||
Total combinational functions : 2,709
|
||||
Dedicated logic registers : 1,420
|
||||
Total registers : 1420
|
||||
Total pins : 46
|
||||
Total virtual pins : 0
|
||||
Total memory bits : 330,016
|
||||
Embedded Multiplier 9-bit elements : 8
|
||||
Total PLLs : 1
|
||||
|
|
@ -0,0 +1,327 @@
|
|||
-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
|
||||
-- Your use of Altera Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Altera Program License
|
||||
-- Subscription Agreement, the Altera Quartus II License Agreement,
|
||||
-- the Altera MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Altera and sold by Altera or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
--
|
||||
-- This is a Quartus II output file. It is for reporting purposes only, and is
|
||||
-- not intended for use as a Quartus II input file. This file cannot be used
|
||||
-- to make Quartus II pin assignments - for instructions on how to make pin
|
||||
-- assignments, please see Quartus II help.
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
-- NC : No Connect. This pin has no internal connection to the device.
|
||||
-- DNU : Do Not Use. This pin MUST NOT be connected.
|
||||
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
|
||||
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
|
||||
-- of its bank.
|
||||
-- Bank 1: 3.3V
|
||||
-- Bank 2: 3.3V
|
||||
-- Bank 3: 1.2V
|
||||
-- Bank 4: 3.3V
|
||||
-- Bank 5: 3.3V
|
||||
-- Bank 6: 3.3V
|
||||
-- Bank 7: 3.3V
|
||||
-- Bank 8: 3.3V
|
||||
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
|
||||
-- It can also be used to report unused dedicated pins. The connection
|
||||
-- on the board for unused dedicated pins depends on whether this will
|
||||
-- be used in a future design. One example is device migration. When
|
||||
-- using device migration, refer to the device pin-tables. If it is a
|
||||
-- GND pin in the pin table or if it will not be used in a future design
|
||||
-- for another purpose the it MUST be connected to GND. If it is an unused
|
||||
-- dedicated pin, then it can be connected to a valid signal on the board
|
||||
-- (low, high, or toggling) if that signal is required for a different
|
||||
-- revision of the design.
|
||||
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
|
||||
-- This pin should be connected to GND. It may also be connected to a
|
||||
-- valid signal on the board (low, high, or toggling) if that signal
|
||||
-- is required for a different revision of the design.
|
||||
-- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
|
||||
-- or leave it unconnected.
|
||||
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
|
||||
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
|
||||
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
|
||||
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
|
||||
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
-- Pin directions (input, output or bidir) are based on device operating in user mode.
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Web Edition
|
||||
CHIP "xoro" ASSIGNED TO AN: EP4CE22F17C6
|
||||
|
||||
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
|
||||
-------------------------------------------------------------------------------------------------------------
|
||||
VCCIO8 : A1 : power : : 3.3V : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 :
|
||||
UART_TX : A3 : output : 3.3-V LVTTL : : 8 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 :
|
||||
GND+ : A8 : : : : 8 :
|
||||
GND+ : A9 : : : : 7 :
|
||||
GPIO_1_D[1] : A10 : output : 3.3-V LVTTL : : 7 : N
|
||||
LED[3] : A11 : output : 3.3-V LVTTL : : 7 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 7 :
|
||||
LED[1] : A13 : output : 3.3-V LVTTL : : 7 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7 :
|
||||
LED[0] : A15 : output : 3.3-V LVTTL : : 7 : Y
|
||||
VCCIO7 : A16 : power : : 3.3V : 7 :
|
||||
LED[6] : B1 : output : 3.3-V LVTTL : : 1 : Y
|
||||
GND : B2 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 :
|
||||
UART_RX : B4 : input : 2.5 V : : 8 : Y
|
||||
GPIO_1_D[3] : B5 : output : 3.3-V LVTTL : : 8 : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 :
|
||||
GND+ : B8 : : : : 8 :
|
||||
GND+ : B9 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 7 :
|
||||
LED[2] : B13 : output : 3.3-V LVTTL : : 7 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7 :
|
||||
GND : B15 : gnd : : : :
|
||||
GPIO_1_D[7] : B16 : output : 3.3-V LVTTL : : 6 : N
|
||||
~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : input : 3.3-V LVTTL : : 1 : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 :
|
||||
VCCIO8 : C4 : power : : 3.3V : 8 :
|
||||
GND : C5 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 :
|
||||
VCCIO8 : C7 : power : : 3.3V : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7 :
|
||||
VCCIO7 : C10 : power : : 3.3V : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 7 :
|
||||
GND : C12 : gnd : : : :
|
||||
VCCIO7 : C13 : power : : 3.3V : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 6 :
|
||||
LED[4] : D1 : output : 3.3-V LVTTL : : 1 : Y
|
||||
~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : input : 3.3-V LVTTL : : 1 : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : : : : 8 :
|
||||
VCCD_PLL3 : D4 : power : : 1.2V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 :
|
||||
GND : D7 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 7 :
|
||||
GND : D10 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 7 :
|
||||
VCCD_PLL2 : D13 : power : : 1.2V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 6 :
|
||||
GND+ : E1 : : : : 1 :
|
||||
GND : E2 : gnd : : : :
|
||||
VCCIO1 : E3 : power : : 3.3V : 1 :
|
||||
GND : E4 : gnd : : : :
|
||||
GNDA3 : E5 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 7 :
|
||||
GNDA2 : E12 : gnd : : : :
|
||||
GND : E13 : gnd : : : :
|
||||
VCCIO6 : E14 : power : : 3.3V : 6 :
|
||||
GND+ : E15 : : : : 6 :
|
||||
GND+ : E16 : : : : 6 :
|
||||
GPIO_1_D[0] : F1 : output : 3.3-V LVTTL : : 1 : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1 :
|
||||
LED[5] : F3 : output : 3.3-V LVTTL : : 1 : Y
|
||||
nSTATUS : F4 : : : : 1 :
|
||||
VCCA3 : F5 : power : : 2.5V : :
|
||||
GND : F6 : gnd : : : :
|
||||
VCCINT : F7 : power : : 1.2V : :
|
||||
GPIO_1_D[5] : F8 : output : 3.3-V LVTTL : : 8 : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F9 : : : : 7 :
|
||||
GND : F10 : gnd : : : :
|
||||
VCCINT : F11 : power : : 1.2V : :
|
||||
VCCA2 : F12 : power : : 2.5V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F13 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 6 :
|
||||
~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : F16 : output : 3.3-V LVTTL : : 6 : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 1 :
|
||||
VCCIO1 : G3 : power : : 3.3V : 1 :
|
||||
GND : G4 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 :
|
||||
VCCINT : G6 : power : : 1.2V : :
|
||||
VCCINT : G7 : power : : 1.2V : :
|
||||
VCCINT : G8 : power : : 1.2V : :
|
||||
VCCINT : G9 : power : : 1.2V : :
|
||||
VCCINT : G10 : power : : 1.2V : :
|
||||
GND : G11 : gnd : : : :
|
||||
MSEL2 : G12 : : : : 6 :
|
||||
GND : G13 : gnd : : : :
|
||||
VCCIO6 : G14 : power : : 3.3V : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 6 :
|
||||
~ALTERA_DCLK~ : H1 : output : 3.3-V LVTTL : : 1 : N
|
||||
~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : input : 3.3-V LVTTL : : 1 : N
|
||||
TCK : H3 : input : : : 1 :
|
||||
TDI : H4 : input : : : 1 :
|
||||
nCONFIG : H5 : : : : 1 :
|
||||
VCCINT : H6 : power : : 1.2V : :
|
||||
GND : H7 : gnd : : : :
|
||||
GND : H8 : gnd : : : :
|
||||
GND : H9 : gnd : : : :
|
||||
GND : H10 : gnd : : : :
|
||||
VCCINT : H11 : power : : 1.2V : :
|
||||
MSEL1 : H12 : : : : 6 :
|
||||
MSEL0 : H13 : : : : 6 :
|
||||
CONF_DONE : H14 : : : : 6 :
|
||||
GND : H15 : gnd : : : :
|
||||
GND : H16 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J1 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J2 : : : : 2 :
|
||||
nCE : J3 : : : : 1 :
|
||||
TDO : J4 : output : : : 1 :
|
||||
TMS : J5 : input : : : 1 :
|
||||
VCCINT : J6 : power : : 1.2V : :
|
||||
GND : J7 : gnd : : : :
|
||||
GND : J8 : gnd : : : :
|
||||
GND : J9 : gnd : : : :
|
||||
GND : J10 : gnd : : : :
|
||||
GND : J11 : gnd : : : :
|
||||
VCCINT : J12 : power : : 1.2V : :
|
||||
GPIO_1_D[32] : J13 : output : 3.3-V LVTTL : : 5 : Y
|
||||
GPIO_1_D[33] : J14 : output : 3.3-V LVTTL : : 5 : Y
|
||||
reset_btn : J15 : input : 3.3-V LVTTL : : 5 : Y
|
||||
GPIO_1_D[30] : J16 : output : 3.3-V LVTTL : : 5 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 2 :
|
||||
VCCIO2 : K3 : power : : 3.3V : 2 :
|
||||
GND : K4 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K5 : : : : 2 :
|
||||
GND : K6 : gnd : : : :
|
||||
VCCINT : K7 : power : : 1.2V : :
|
||||
GND : K8 : gnd : : : :
|
||||
VCCINT : K9 : power : : 1.2V : :
|
||||
VCCINT : K10 : power : : 1.2V : :
|
||||
VCCINT : K11 : power : : 1.2V : :
|
||||
GND : K12 : gnd : : : :
|
||||
GND : K13 : gnd : : : :
|
||||
VCCIO5 : K14 : power : : 3.3V : 5 :
|
||||
GPIO_1_D[31] : K15 : output : 3.3-V LVTTL : : 5 : Y
|
||||
GPIO_1_D[17] : K16 : output : 3.3-V LVTTL : : 5 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 2 :
|
||||
LED[7] : L3 : output : 3.3-V LVTTL : : 2 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : : : : 2 :
|
||||
VCCA1 : L5 : power : : 2.5V : :
|
||||
VCCINT : L6 : power : : 1.2V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 3 :
|
||||
GND : L9 : gnd : : : :
|
||||
GND : L10 : gnd : : : :
|
||||
GND : L11 : gnd : : : :
|
||||
VCCA4 : L12 : power : : 2.5V : :
|
||||
GPIO_1_D[29] : L13 : output : 3.3-V LVTTL : : 5 : Y
|
||||
GPIO_1_D[26] : L14 : output : 3.3-V LVTTL : : 5 : Y
|
||||
GPIO_1_D[19] : L15 : output : 3.3-V LVTTL : : 5 : Y
|
||||
GPIO_1_D[16] : L16 : output : 3.3-V LVTTL : : 5 : Y
|
||||
GND+ : M1 : : : : 2 :
|
||||
GND+ : M2 : : : : 2 :
|
||||
VCCIO2 : M3 : power : : 3.3V : 2 :
|
||||
GND : M4 : gnd : : : :
|
||||
GNDA1 : M5 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : M6 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 3 :
|
||||
VCCINT : M9 : power : : 1.2V : :
|
||||
GPIO_1_D[28] : M10 : output : 3.3-V LVTTL : : 4 : Y
|
||||
VCCINT : M11 : power : : 1.2V : :
|
||||
GNDA4 : M12 : gnd : : : :
|
||||
GND : M13 : gnd : : : :
|
||||
VCCIO5 : M14 : power : : 3.3V : 5 :
|
||||
GND+ : M15 : : : : 5 :
|
||||
GND+ : M16 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : N1 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : N2 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 3 :
|
||||
VCCD_PLL1 : N4 : power : : 1.2V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : N5 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : N6 : : : : 3 :
|
||||
GND : N7 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 3 :
|
||||
GPIO_1_D[14] : N9 : output : 3.3-V LVTTL : : 4 : Y
|
||||
GND : N10 : gnd : : : :
|
||||
GPIO_1_D[15] : N11 : output : 3.3-V LVTTL : : 4 : Y
|
||||
GPIO_1_D[12] : N12 : output : 3.3-V LVTTL : : 4 : Y
|
||||
VCCD_PLL4 : N13 : power : : 1.2V : :
|
||||
GPIO_1_D[27] : N14 : output : 3.3-V LVTTL : : 5 : Y
|
||||
GPIO_1_D[24] : N15 : output : 3.3-V LVTTL : : 5 : Y
|
||||
GPIO_1_D[23] : N16 : output : 3.3-V LVTTL : : 5 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 3 :
|
||||
VCCIO3 : P4 : power : : 1.2V : 3 :
|
||||
GND : P5 : gnd : : : :
|
||||
VREFB3N0 : P6 : : : 0.6V : 3 :
|
||||
VCCIO3 : P7 : power : : 1.2V : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 3 :
|
||||
GPIO_1_D[13] : P9 : output : 3.3-V LVTTL : : 4 : Y
|
||||
VCCIO4 : P10 : power : : 3.3V : 4 :
|
||||
GPIO_1_D[10] : P11 : output : 3.3-V LVTTL : : 4 : Y
|
||||
GND : P12 : gnd : : : :
|
||||
VCCIO4 : P13 : power : : 3.3V : 4 :
|
||||
GPIO_1_D[25] : P14 : output : 3.3-V LVTTL : : 4 : Y
|
||||
GPIO_1_D[20] : P15 : output : 3.3-V LVTTL : : 5 : Y
|
||||
GPIO_1_D[21] : P16 : output : 3.3-V LVTTL : : 5 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 :
|
||||
GND : R2 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 3 :
|
||||
CLOCK_50 : R8 : input : 1.2-V HSTL Class II : : 3 : Y
|
||||
GND+ : R9 : : : : 4 :
|
||||
GPIO_1_D[11] : R10 : output : 3.3-V LVTTL : : 4 : Y
|
||||
GPIO_1_D[9] : R11 : output : 3.3-V LVTTL : : 4 : Y
|
||||
GPIO_1_D[6] : R12 : output : 3.3-V LVTTL : : 4 : Y
|
||||
GPIO_1_D[4] : R13 : output : 3.3-V LVTTL : : 4 : Y
|
||||
GPIO_1_D[22] : R14 : output : 3.3-V LVTTL : : 4 : Y
|
||||
GND : R15 : gnd : : : :
|
||||
GPIO_1_D[18] : R16 : output : 3.3-V LVTTL : : 5 : Y
|
||||
VCCIO3 : T1 : power : : 1.2V : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T2 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T5 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T6 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 3 :
|
||||
GND+ : T8 : : : : 3 :
|
||||
GND+ : T9 : : : : 4 :
|
||||
GPIO_1_D[8] : T10 : output : 3.3-V LVTTL : : 4 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T11 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T12 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T13 : : : : 4 :
|
||||
GPIO_1_D[2] : T14 : output : 3.3-V LVTTL : : 4 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T15 : : : : 4 :
|
||||
VCCIO4 : T16 : power : : 3.3V : 4 :
|
||||
|
|
@ -0,0 +1 @@
|
|||
<sld_project_info/>
|
||||
Binary file not shown.
Loading…
Reference in New Issue