diff --git a/rtl/DE0-NANO/Memory.v_toplevel_memory_1_symbol0.bin b/rtl/DE0-NANO/Memory.v_toplevel_memory_1_symbol0.bin
new file mode 100644
index 0000000..4e13f2a
--- /dev/null
+++ b/rtl/DE0-NANO/Memory.v_toplevel_memory_1_symbol0.bin
@@ -0,0 +1,16384 @@
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diff --git a/rtl/DE0-NANO/Memory.v_toplevel_memory_1_symbol1.bin b/rtl/DE0-NANO/Memory.v_toplevel_memory_1_symbol1.bin
new file mode 100644
index 0000000..6b178d6
--- /dev/null
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diff --git a/rtl/DE0-NANO/Memory.v_toplevel_memory_1_symbol2.bin b/rtl/DE0-NANO/Memory.v_toplevel_memory_1_symbol2.bin
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index 0000000..946e261
--- /dev/null
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diff --git a/rtl/DE0-NANO/Memory.v_toplevel_memory_1_symbol3.bin b/rtl/DE0-NANO/Memory.v_toplevel_memory_1_symbol3.bin
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index 0000000..d088872
--- /dev/null
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+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
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+00000000
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+00000000
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+00000000
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+00000000
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+00000000
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+00000000
diff --git a/rtl/DE0-NANO/output_files/xoro.asm.rpt b/rtl/DE0-NANO/output_files/xoro.asm.rpt
new file mode 100644
index 0000000..cea5fb0
--- /dev/null
+++ b/rtl/DE0-NANO/output_files/xoro.asm.rpt
@@ -0,0 +1,92 @@
+Assembler report for xoro
+Sat Sep 16 21:12:47 2023
+Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: E:/Photonic/RISCV/output_files/xoro.sof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus II License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Sat Sep 16 21:12:47 2023 ;
+; Revision Name         ; xoro                                  ;
+; Top-level Entity Name ; xoro_top                              ;
+; Family                ; Cyclone IV E                          ;
+; Device                ; EP4CE22F17C6                          ;
++-----------------------+---------------------------------------+
+
+
++----------------------------------+
+; Assembler Settings               ;
++--------+---------+---------------+
+; Option ; Setting ; Default Value ;
++--------+---------+---------------+
+
+
++-----------------------------------------+
+; Assembler Generated Files               ;
++-----------------------------------------+
+; File Name                               ;
++-----------------------------------------+
+; E:/Photonic/RISCV/output_files/xoro.sof ;
++-----------------------------------------+
+
+
++-------------------------------------------------------------------+
+; Assembler Device Options: E:/Photonic/RISCV/output_files/xoro.sof ;
++----------------+--------------------------------------------------+
+; Option         ; Setting                                          ;
++----------------+--------------------------------------------------+
+; Device         ; EP4CE22F17C6                                     ;
+; JTAG usercode  ; 0x00425C9B                                       ;
+; Checksum       ; 0x00425C9B                                       ;
++----------------+--------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Assembler
+    Info: Version 15.0.0 Build 145 04/22/2015 SJ Web Edition
+    Info: Processing started: Sat Sep 16 21:12:46 2023
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off xoro -c xoro
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 4761 megabytes
+    Info: Processing ended: Sat Sep 16 21:12:47 2023
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/rtl/DE0-NANO/output_files/xoro.done b/rtl/DE0-NANO/output_files/xoro.done
new file mode 100644
index 0000000..8dfd15a
--- /dev/null
+++ b/rtl/DE0-NANO/output_files/xoro.done
@@ -0,0 +1 @@
+Sat Sep 16 21:12:48 2023
diff --git a/rtl/DE0-NANO/output_files/xoro.fit.rpt b/rtl/DE0-NANO/output_files/xoro.fit.rpt
new file mode 100644
index 0000000..bf80107
--- /dev/null
+++ b/rtl/DE0-NANO/output_files/xoro.fit.rpt
@@ -0,0 +1,7228 @@
+Fitter report for xoro
+Sat Sep 16 21:12:44 2023
+Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Fitter Netlist Optimizations
+  7. Ignored Assignments
+  8. Incremental Compilation Preservation Summary
+  9. Incremental Compilation Partition Settings
+ 10. Incremental Compilation Placement Preservation
+ 11. Pin-Out File
+ 12. Fitter Resource Usage Summary
+ 13. Fitter Partition Statistics
+ 14. Input Pins
+ 15. Output Pins
+ 16. Dual Purpose and Dedicated Pins
+ 17. I/O Bank Usage
+ 18. All Package Pins
+ 19. PLL Summary
+ 20. PLL Usage
+ 21. Fitter Resource Utilization by Entity
+ 22. Delay Chain Summary
+ 23. Pad To Core Delay Chain Fanout
+ 24. Control Signals
+ 25. Global & Other Fast Signals
+ 26. Fitter RAM Summary
+ 27. |xoro_top|Memory:mem|altsyncram:memory_1_symbol3_rtl_0|altsyncram_edi1:auto_generated|ALTSYNCRAM
+ 28. |xoro_top|Memory:mem|altsyncram:memory_1_symbol1_rtl_0|altsyncram_cdi1:auto_generated|ALTSYNCRAM
+ 29. |xoro_top|Memory:mem|altsyncram:memory_1_symbol0_rtl_0|altsyncram_bdi1:auto_generated|ALTSYNCRAM
+ 30. |xoro_top|Memory:mem|altsyncram:memory_1_symbol2_rtl_0|altsyncram_ddi1:auto_generated|ALTSYNCRAM
+ 31. Fitter DSP Block Usage Summary
+ 32. DSP Block Details
+ 33. Routing Usage Summary
+ 34. LAB Logic Elements
+ 35. LAB-wide Signals
+ 36. LAB Signals Sourced
+ 37. LAB Signals Sourced Out
+ 38. LAB Distinct Inputs
+ 39. I/O Rules Summary
+ 40. I/O Rules Details
+ 41. I/O Rules Matrix
+ 42. Fitter Device Options
+ 43. Operating Settings and Conditions
+ 44. Estimated Delay Added for Hold Timing Summary
+ 45. Estimated Delay Added for Hold Timing Details
+ 46. Fitter Messages
+ 47. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus II License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; Fitter Summary                                                                  ;
++------------------------------------+--------------------------------------------+
+; Fitter Status                      ; Successful - Sat Sep 16 21:12:44 2023      ;
+; Quartus II 64-Bit Version          ; 15.0.0 Build 145 04/22/2015 SJ Web Edition ;
+; Revision Name                      ; xoro                                       ;
+; Top-level Entity Name              ; xoro_top                                   ;
+; Family                             ; Cyclone IV E                               ;
+; Device                             ; EP4CE22F17C6                               ;
+; Timing Models                      ; Final                                      ;
+; Total logic elements               ; 2,973 / 22,320 ( 13 % )                    ;
+;     Total combinational functions  ; 2,743 / 22,320 ( 12 % )                    ;
+;     Dedicated logic registers      ; 1,354 / 22,320 ( 6 % )                     ;
+; Total registers                    ; 1354                                       ;
+; Total pins                         ; 46 / 154 ( 30 % )                          ;
+; Total virtual pins                 ; 0                                          ;
+; Total memory bits                  ; 330,016 / 608,256 ( 54 % )                 ;
+; Embedded Multiplier 9-bit elements ; 8 / 132 ( 6 % )                            ;
+; Total PLLs                         ; 1 / 4 ( 25 % )                             ;
++------------------------------------+--------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; EP4CE22F17C6                          ;                                       ;
+; Maximum processors allowed for parallel compilation                        ; 2                                     ;                                       ;
+; Nominal Core Supply Voltage                                                ; 1.2V                                  ;                                       ;
+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
+; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
+; Device I/O Standard                                                        ; 2.5 V                                 ;                                       ;
+; Use smart compilation                                                      ; Off                                   ; Off                                   ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; PowerPlay Power Optimization During Fitting                                ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate Full Fit Report During ECO Compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; PCI I/O                                                                    ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Auto                                  ; Auto                                  ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 16          ;
+; Maximum allowed            ; 2           ;
+;                            ;             ;
+; Average used               ; 1.43        ;
+; Maximum used               ; 2           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;  42.9%      ;
+;     Processors 3-16        ;   0.0%      ;
++----------------------------+-------------+
+
+
++--------------------------------------------+
+; I/O Assignment Warnings                    ;
++--------------+-----------------------------+
+; Pin Name     ; Reason                      ;
++--------------+-----------------------------+
+; LED[0]       ; Missing drive strength      ;
+; LED[1]       ; Missing drive strength      ;
+; LED[2]       ; Missing drive strength      ;
+; LED[3]       ; Missing drive strength      ;
+; LED[4]       ; Missing drive strength      ;
+; LED[5]       ; Missing drive strength      ;
+; LED[6]       ; Missing drive strength      ;
+; LED[7]       ; Missing drive strength      ;
+; UART_TX      ; Missing drive strength      ;
+; GPIO_1_D[0]  ; Missing drive strength      ;
+; GPIO_1_D[1]  ; Missing drive strength      ;
+; GPIO_1_D[2]  ; Missing drive strength      ;
+; GPIO_1_D[3]  ; Missing drive strength      ;
+; GPIO_1_D[4]  ; Missing drive strength      ;
+; GPIO_1_D[5]  ; Missing drive strength      ;
+; GPIO_1_D[6]  ; Missing drive strength      ;
+; GPIO_1_D[7]  ; Missing drive strength      ;
+; GPIO_1_D[8]  ; Missing drive strength      ;
+; GPIO_1_D[9]  ; Missing drive strength      ;
+; GPIO_1_D[10] ; Missing drive strength      ;
+; GPIO_1_D[11] ; Missing drive strength      ;
+; GPIO_1_D[12] ; Missing drive strength      ;
+; GPIO_1_D[13] ; Missing drive strength      ;
+; GPIO_1_D[14] ; Missing drive strength      ;
+; GPIO_1_D[15] ; Missing drive strength      ;
+; GPIO_1_D[16] ; Missing drive strength      ;
+; GPIO_1_D[17] ; Missing drive strength      ;
+; GPIO_1_D[18] ; Missing drive strength      ;
+; GPIO_1_D[19] ; Missing drive strength      ;
+; GPIO_1_D[20] ; Missing drive strength      ;
+; GPIO_1_D[21] ; Missing drive strength      ;
+; GPIO_1_D[22] ; Missing drive strength      ;
+; GPIO_1_D[23] ; Missing drive strength      ;
+; GPIO_1_D[24] ; Missing drive strength      ;
+; GPIO_1_D[25] ; Missing drive strength      ;
+; GPIO_1_D[26] ; Missing drive strength      ;
+; GPIO_1_D[27] ; Missing drive strength      ;
+; GPIO_1_D[28] ; Missing drive strength      ;
+; GPIO_1_D[29] ; Missing drive strength      ;
+; GPIO_1_D[30] ; Missing drive strength      ;
+; GPIO_1_D[31] ; Missing drive strength      ;
+; GPIO_1_D[32] ; Missing drive strength      ;
+; GPIO_1_D[33] ; Missing drive strength      ;
+; GPIO_1_D[0]  ; Missing location assignment ;
+; GPIO_1_D[1]  ; Missing location assignment ;
+; GPIO_1_D[3]  ; Missing location assignment ;
+; GPIO_1_D[5]  ; Missing location assignment ;
+; GPIO_1_D[7]  ; Missing location assignment ;
++--------------+-----------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Netlist Optimizations                                                                                                                                                                                                                                                                         ;
++-------------------------------------------------------------------+-----------------+------------------+---------------------+-----------+----------------+-----------------------------------------------------------------------------------------------+------------------+-----------------------+
+; Node                                                              ; Action          ; Operation        ; Reason              ; Node Port ; Node Port Name ; Destination Node                                                                              ; Destination Port ; Destination Port Name ;
++-------------------------------------------------------------------+-----------------+------------------+---------------------+-----------+----------------+-----------------------------------------------------------------------------------------------+------------------+-----------------------+
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[0]               ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[0]               ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[0]~_Duplicate_1                              ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[0]~_Duplicate_1  ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[1]               ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[1]               ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[1]~_Duplicate_1                              ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[1]~_Duplicate_1  ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[2]               ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[2]               ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[2]~_Duplicate_1                              ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[2]~_Duplicate_1  ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[3]               ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[3]               ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[3]~_Duplicate_1                              ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[3]~_Duplicate_1  ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[4]               ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[4]               ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[4]~_Duplicate_1                              ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[4]~_Duplicate_1  ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[5]               ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[5]               ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[5]~_Duplicate_1                              ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[5]~_Duplicate_1  ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[6]               ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[6]               ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[6]~_Duplicate_1                              ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[6]~_Duplicate_1  ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[7]               ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[7]               ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[7]~_Duplicate_1                              ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[7]~_Duplicate_1  ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[8]               ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[8]               ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[8]~_Duplicate_1                              ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[8]~_Duplicate_1  ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[9]               ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[9]               ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[9]~_Duplicate_1                              ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[9]~_Duplicate_1  ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[10]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[10]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[10]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[10]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[11]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[11]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[11]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[11]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[12]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[12]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[12]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[12]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[13]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[13]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[13]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[13]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[14]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[14]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[14]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[14]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[15]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[15]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[15]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[15]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[16]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[16]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[16]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[16]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[17]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[17]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[17]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[17]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[18]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[18]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[18]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[18]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult7 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[19]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[19]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[19]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[19]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult7 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[20]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[20]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[20]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[20]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult7 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[21]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[21]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[21]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[21]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult7 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[22]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[22]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[22]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[22]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult7 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[23]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[23]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[23]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[23]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult7 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[24]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[24]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[24]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[24]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult7 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[25]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[25]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[25]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[25]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult7 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[26]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[26]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[26]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[26]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult7 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[27]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[27]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[27]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[27]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult7 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[28]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[28]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[28]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[28]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult7 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[29]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[29]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[29]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[29]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult7 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[30]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[30]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[30]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[30]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult7 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[31]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[31]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[31]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[31]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult7 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[32]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[32]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[32]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs1[32]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult7 ; DATAA            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[0]               ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[0]               ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[0]~_Duplicate_1                              ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[0]~_Duplicate_1  ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[1]               ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[1]               ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[1]~_Duplicate_1                              ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[1]~_Duplicate_1  ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[2]               ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[2]               ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[2]~_Duplicate_1                              ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[2]~_Duplicate_1  ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[3]               ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[3]               ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[3]~_Duplicate_1                              ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[3]~_Duplicate_1  ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[4]               ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[4]               ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[4]~_Duplicate_1                              ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[4]~_Duplicate_1  ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[5]               ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[5]               ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[5]~_Duplicate_1                              ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[5]~_Duplicate_1  ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[6]               ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[6]               ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[6]~_Duplicate_1                              ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[6]~_Duplicate_1  ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[7]               ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[7]               ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[7]~_Duplicate_1                              ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[7]~_Duplicate_1  ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[8]               ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[8]               ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[8]~_Duplicate_1                              ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[8]~_Duplicate_1  ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[9]               ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[9]               ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[9]~_Duplicate_1                              ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[9]~_Duplicate_1  ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[10]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[10]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[10]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[10]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[11]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[11]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[11]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[11]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[12]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[12]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[12]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[12]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[13]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[13]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[13]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[13]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[14]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[14]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[14]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[14]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[15]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[15]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[15]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[15]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[16]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[16]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[16]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[16]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[17]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[17]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[17]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[17]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[18]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[18]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[18]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[18]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult7 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[19]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[19]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[19]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[19]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult7 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[20]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[20]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[20]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[20]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult7 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[21]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[21]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[21]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[21]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult7 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[22]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[22]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[22]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[22]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult7 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[23]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[23]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[23]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[23]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult7 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[24]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[24]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[24]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[24]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult7 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[25]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[25]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[25]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[25]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult7 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[26]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[26]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[26]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[26]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult7 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[27]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[27]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[27]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[27]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult7 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[28]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[28]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[28]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[28]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult7 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[29]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[29]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[29]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[29]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult7 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[30]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[30]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[30]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[30]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult7 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[31]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[31]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[31]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[31]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult7 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[32]              ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ; DATAB            ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[32]              ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[32]~_Duplicate_1                             ; Q                ;                       ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|rs2[32]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult7 ; DATAB            ;                       ;
++-------------------------------------------------------------------+-----------------+------------------+---------------------+-----------+----------------+-----------------------------------------------------------------------------------------------+------------------+-----------------------+
+
+
++-----------------------------------------------------------------------------------------------+
+; Ignored Assignments                                                                           ;
++--------------+----------------+--------------+---------------+---------------+----------------+
+; Name         ; Ignored Entity ; Ignored From ; Ignored To    ; Ignored Value ; Ignored Source ;
++--------------+----------------+--------------+---------------+---------------+----------------+
+; Location     ;                ;              ; ADC_CS_N      ; PIN_A10       ; QSF Assignment ;
+; Location     ;                ;              ; ADC_SADDR     ; PIN_B10       ; QSF Assignment ;
+; Location     ;                ;              ; ADC_SCLK      ; PIN_B14       ; QSF Assignment ;
+; Location     ;                ;              ; ADC_SDAT      ; PIN_A9        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[0]  ; PIN_P2        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[10] ; PIN_N2        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[11] ; PIN_N1        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[12] ; PIN_L4        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[1]  ; PIN_N5        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[2]  ; PIN_N6        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[3]  ; PIN_M8        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[4]  ; PIN_P8        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[5]  ; PIN_T7        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[6]  ; PIN_N8        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[7]  ; PIN_T6        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[8]  ; PIN_R1        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[9]  ; PIN_P1        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_BA[0]    ; PIN_M7        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_BA[1]    ; PIN_M6        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_CAS_N    ; PIN_L1        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_CKE      ; PIN_L7        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_CLK      ; PIN_R4        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_CS_N     ; PIN_P6        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQM[0]   ; PIN_R6        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQM[1]   ; PIN_T5        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[0]    ; PIN_G2        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[10]   ; PIN_T3        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[11]   ; PIN_R3        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[12]   ; PIN_R5        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[13]   ; PIN_P3        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[14]   ; PIN_N3        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[15]   ; PIN_K1        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[1]    ; PIN_G1        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[2]    ; PIN_L8        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[3]    ; PIN_K5        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[4]    ; PIN_K2        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[5]    ; PIN_J2        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[6]    ; PIN_J1        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[7]    ; PIN_R7        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[8]    ; PIN_T4        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[9]    ; PIN_T2        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_RAS_N    ; PIN_L2        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_WE_N     ; PIN_C2        ; QSF Assignment ;
+; Location     ;                ;              ; EPCS_ASDO     ; PIN_C1        ; QSF Assignment ;
+; Location     ;                ;              ; EPCS_DATA0    ; PIN_H2        ; QSF Assignment ;
+; Location     ;                ;              ; EPCS_DCLK     ; PIN_H1        ; QSF Assignment ;
+; Location     ;                ;              ; EPCS_NCSO     ; PIN_D2        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_D[0]   ; PIN_D3        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_D[10]  ; PIN_B6        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_D[11]  ; PIN_A6        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_D[12]  ; PIN_B7        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_D[13]  ; PIN_D6        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_D[14]  ; PIN_A7        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_D[15]  ; PIN_C6        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_D[16]  ; PIN_C8        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_D[17]  ; PIN_E6        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_D[18]  ; PIN_E7        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_D[19]  ; PIN_D8        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_D[1]   ; PIN_C3        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_D[20]  ; PIN_E8        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_D[21]  ; PIN_F8        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_D[22]  ; PIN_F9        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_D[23]  ; PIN_E9        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_D[24]  ; PIN_C9        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_D[25]  ; PIN_D9        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_D[26]  ; PIN_E11       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_D[27]  ; PIN_E10       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_D[28]  ; PIN_C11       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_D[29]  ; PIN_B11       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_D[2]   ; PIN_A2        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_D[30]  ; PIN_A12       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_D[31]  ; PIN_D11       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_D[32]  ; PIN_D12       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_D[33]  ; PIN_B12       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_D[6]   ; PIN_A4        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_D[7]   ; PIN_B5        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_D[8]   ; PIN_A5        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_D[9]   ; PIN_D5        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_IN[0]  ; PIN_A8        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0_IN[1]  ; PIN_B8        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1_IN[0]  ; PIN_T9        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1_IN[1]  ; PIN_R9        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_2[0]     ; PIN_A14       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_2[10]    ; PIN_F14       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_2[11]    ; PIN_G16       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_2[12]    ; PIN_G15       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_2[1]     ; PIN_B16       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_2[2]     ; PIN_C14       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_2[3]     ; PIN_C16       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_2[4]     ; PIN_C15       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_2[5]     ; PIN_D16       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_2[6]     ; PIN_D15       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_2[7]     ; PIN_D14       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_2[8]     ; PIN_F15       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_2[9]     ; PIN_F16       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_2_IN[0]  ; PIN_E15       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_2_IN[1]  ; PIN_E16       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_2_IN[2]  ; PIN_M16       ; QSF Assignment ;
+; Location     ;                ;              ; G_SENSOR_CS_N ; PIN_G5        ; QSF Assignment ;
+; Location     ;                ;              ; G_SENSOR_INT  ; PIN_M2        ; QSF Assignment ;
+; Location     ;                ;              ; I2C_SCLK      ; PIN_F2        ; QSF Assignment ;
+; Location     ;                ;              ; I2C_SDAT      ; PIN_F1        ; QSF Assignment ;
+; Location     ;                ;              ; KEY[1]        ; PIN_E1        ; QSF Assignment ;
+; Location     ;                ;              ; RND_OUT[0]    ; PIN_T12       ; QSF Assignment ;
+; Location     ;                ;              ; RND_OUT[1]    ; PIN_T13       ; QSF Assignment ;
+; Location     ;                ;              ; RND_OUT[2]    ; PIN_T15       ; QSF Assignment ;
+; Location     ;                ;              ; RND_OUT[3]    ; PIN_F13       ; QSF Assignment ;
+; Location     ;                ;              ; SW[0]         ; PIN_M1        ; QSF Assignment ;
+; Location     ;                ;              ; SW[1]         ; PIN_T8        ; QSF Assignment ;
+; Location     ;                ;              ; SW[2]         ; PIN_B9        ; QSF Assignment ;
+; Location     ;                ;              ; SW[3]         ; PIN_M15       ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; ADC_CS_N      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; ADC_SADDR     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; ADC_SCLK      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; ADC_SDAT      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_ADDR[0]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_ADDR[10] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_ADDR[11] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_ADDR[12] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_ADDR[1]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_ADDR[2]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_ADDR[3]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_ADDR[4]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_ADDR[5]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_ADDR[6]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_ADDR[7]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_ADDR[8]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_ADDR[9]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_BA[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_BA[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_CAS_N    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_CKE      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_CLK      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_CS_N     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_DQM[0]   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_DQM[1]   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_DQ[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_DQ[10]   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_DQ[11]   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_DQ[12]   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_DQ[13]   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_DQ[14]   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_DQ[15]   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_DQ[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_DQ[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_DQ[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_DQ[4]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_DQ[5]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_DQ[6]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_DQ[7]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_DQ[8]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_DQ[9]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_RAS_N    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; DRAM_WE_N     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; EPCS_ASDO     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; EPCS_DATA0    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; EPCS_DCLK     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; EPCS_NCSO     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[0]   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[10]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[11]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[12]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[13]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[14]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[15]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[16]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[17]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[18]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[19]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[1]   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[20]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[21]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[22]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[23]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[24]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[25]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[26]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[27]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[28]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[29]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[2]   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[30]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[31]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[32]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[33]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[3]   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[4]   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[5]   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[6]   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[7]   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[8]   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_D[9]   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_IN[0]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_0_IN[1]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_1_D      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_1_IN[0]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_1_IN[1]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_2[0]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_2[10]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_2[11]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_2[12]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_2[1]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_2[2]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_2[3]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_2[4]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_2[5]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_2[6]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_2[7]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_2[8]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_2[9]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_2_IN[0]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_2_IN[1]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; GPIO_2_IN[2]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; G_SENSOR_CS_N ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; G_SENSOR_INT  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; I2C_SCLK      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; I2C_SDAT      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; KEY[1]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; RND_OUT       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; RND_OUT[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; RND_OUT[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; RND_OUT[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; RND_OUT[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; SW[0]         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; SW[1]         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; SW[2]         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; xoro_top       ;              ; SW[3]         ; 3.3-V LVTTL   ; QSF Assignment ;
++--------------+----------------+--------------+---------------+---------------+----------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary                                                      ;
++---------------------+---------------------+----------------------------+--------------------------+
+; Type                ; Total [A + B]       ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+---------------------+----------------------------+--------------------------+
+; Placement (by node) ;                     ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 4382 ) ; 0.00 % ( 0 / 4382 )        ; 0.00 % ( 0 / 4382 )      ;
+;     -- Achieved     ; 0.00 % ( 0 / 4382 ) ; 0.00 % ( 0 / 4382 )        ; 0.00 % ( 0 / 4382 )      ;
+;                     ;                     ;                            ;                          ;
+; Routing (by net)    ;                     ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 0 )    ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+;     -- Achieved     ; 0.00 % ( 0 / 0 )    ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
++---------------------+---------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                                                     ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top                            ; 0.00 % ( 0 / 4368 )   ; N/A                     ; Source File       ; N/A                 ;       ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 14 )     ; N/A                     ; Source File       ; N/A                 ;       ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in E:/Photonic/RISCV/output_files/xoro.pin.
+
+
++--------------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                            ;
++---------------------------------------------+----------------------------+
+; Resource                                    ; Usage                      ;
++---------------------------------------------+----------------------------+
+; Total logic elements                        ; 2,973 / 22,320 ( 13 % )    ;
+;     -- Combinational with no register       ; 1619                       ;
+;     -- Register only                        ; 230                        ;
+;     -- Combinational with a register        ; 1124                       ;
+;                                             ;                            ;
+; Logic element usage by number of LUT inputs ;                            ;
+;     -- 4 input functions                    ; 1274                       ;
+;     -- 3 input functions                    ; 1043                       ;
+;     -- <=2 input functions                  ; 426                        ;
+;     -- Register only                        ; 230                        ;
+;                                             ;                            ;
+; Logic elements by mode                      ;                            ;
+;     -- normal mode                          ; 2182                       ;
+;     -- arithmetic mode                      ; 561                        ;
+;                                             ;                            ;
+; Total registers*                            ; 1,354 / 23,018 ( 6 % )     ;
+;     -- Dedicated logic registers            ; 1,354 / 22,320 ( 6 % )     ;
+;     -- I/O registers                        ; 0 / 698 ( 0 % )            ;
+;                                             ;                            ;
+; Total LABs:  partially or completely used   ; 216 / 1,395 ( 15 % )       ;
+; Virtual pins                                ; 0                          ;
+; I/O pins                                    ; 46 / 154 ( 30 % )          ;
+;     -- Clock pins                           ; 1 / 7 ( 14 % )             ;
+;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )              ;
+;                                             ;                            ;
+; Global signals                              ; 5                          ;
+; M9Ks                                        ; 51 / 66 ( 77 % )           ;
+; Total block memory bits                     ; 330,016 / 608,256 ( 54 % ) ;
+; Total block memory implementation bits      ; 470,016 / 608,256 ( 77 % ) ;
+; Embedded Multiplier 9-bit elements          ; 8 / 132 ( 6 % )            ;
+; PLLs                                        ; 1 / 4 ( 25 % )             ;
+; Global clocks                               ; 5 / 20 ( 25 % )            ;
+; JTAGs                                       ; 0 / 1 ( 0 % )              ;
+; CRC blocks                                  ; 0 / 1 ( 0 % )              ;
+; ASMI blocks                                 ; 0 / 1 ( 0 % )              ;
+; Oscillator blocks                           ; 0 / 1 ( 0 % )              ;
+; Impedance control blocks                    ; 0 / 4 ( 0 % )              ;
+; Average interconnect usage (total/H/V)      ; 6.7% / 6.5% / 6.9%         ;
+; Peak interconnect usage (total/H/V)         ; 34.2% / 32.1% / 37.1%      ;
+; Maximum fan-out                             ; 1298                       ;
+; Highest non-global fan-out                  ; 224                        ;
+; Total fan-out                               ; 14990                      ;
+; Average fan-out                             ; 3.37                       ;
++---------------------------------------------+----------------------------+
+*  Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++------------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                          ;
++---------------------------------------------+-----------------------+--------------------------------+
+; Statistic                                   ; Top                   ; hard_block:auto_generated_inst ;
++---------------------------------------------+-----------------------+--------------------------------+
+; Difficulty Clustering Region                ; Low                   ; Low                            ;
+;                                             ;                       ;                                ;
+; Total logic elements                        ; 2973 / 22320 ( 13 % ) ; 0 / 22320 ( 0 % )              ;
+;     -- Combinational with no register       ; 1619                  ; 0                              ;
+;     -- Register only                        ; 230                   ; 0                              ;
+;     -- Combinational with a register        ; 1124                  ; 0                              ;
+;                                             ;                       ;                                ;
+; Logic element usage by number of LUT inputs ;                       ;                                ;
+;     -- 4 input functions                    ; 1274                  ; 0                              ;
+;     -- 3 input functions                    ; 1043                  ; 0                              ;
+;     -- <=2 input functions                  ; 426                   ; 0                              ;
+;     -- Register only                        ; 230                   ; 0                              ;
+;                                             ;                       ;                                ;
+; Logic elements by mode                      ;                       ;                                ;
+;     -- normal mode                          ; 2182                  ; 0                              ;
+;     -- arithmetic mode                      ; 561                   ; 0                              ;
+;                                             ;                       ;                                ;
+; Total registers                             ; 1354                  ; 0                              ;
+;     -- Dedicated logic registers            ; 1354 / 22320 ( 6 % )  ; 0 / 22320 ( 0 % )              ;
+;     -- I/O registers                        ; 0                     ; 0                              ;
+;                                             ;                       ;                                ;
+; Total LABs:  partially or completely used   ; 216 / 1395 ( 15 % )   ; 0 / 1395 ( 0 % )               ;
+;                                             ;                       ;                                ;
+; Virtual pins                                ; 0                     ; 0                              ;
+; I/O pins                                    ; 46                    ; 0                              ;
+; Embedded Multiplier 9-bit elements          ; 8 / 132 ( 6 % )       ; 0 / 132 ( 0 % )                ;
+; Total memory bits                           ; 330016                ; 0                              ;
+; Total RAM block bits                        ; 470016                ; 0                              ;
+; PLL                                         ; 0 / 4 ( 0 % )         ; 1 / 4 ( 25 % )                 ;
+; M9K                                         ; 51 / 66 ( 77 % )      ; 0 / 66 ( 0 % )                 ;
+; Clock control block                         ; 2 / 24 ( 8 % )        ; 3 / 24 ( 12 % )                ;
+;                                             ;                       ;                                ;
+; Connections                                 ;                       ;                                ;
+;     -- Input Connections                    ; 1301                  ; 1                              ;
+;     -- Registered Input Connections         ; 1197                  ; 0                              ;
+;     -- Output Connections                   ; 1                     ; 1301                           ;
+;     -- Registered Output Connections        ; 0                     ; 0                              ;
+;                                             ;                       ;                                ;
+; Internal Connections                        ;                       ;                                ;
+;     -- Total Connections                    ; 15227                 ; 1311                           ;
+;     -- Registered Connections               ; 7229                  ; 0                              ;
+;                                             ;                       ;                                ;
+; External Connections                        ;                       ;                                ;
+;     -- Top                                  ; 0                     ; 1302                           ;
+;     -- hard_block:auto_generated_inst       ; 1302                  ; 0                              ;
+;                                             ;                       ;                                ;
+; Partition Interface                         ;                       ;                                ;
+;     -- Input Ports                          ; 3                     ; 1                              ;
+;     -- Output Ports                         ; 43                    ; 3                              ;
+;     -- Bidir Ports                          ; 0                     ; 0                              ;
+;                                             ;                       ;                                ;
+; Registered Ports                            ;                       ;                                ;
+;     -- Registered Input Ports               ; 0                     ; 0                              ;
+;     -- Registered Output Ports              ; 0                     ; 0                              ;
+;                                             ;                       ;                                ;
+; Port Connectivity                           ;                       ;                                ;
+;     -- Input Ports driven by GND            ; 0                     ; 0                              ;
+;     -- Output Ports driven by GND           ; 0                     ; 0                              ;
+;     -- Input Ports driven by VCC            ; 0                     ; 0                              ;
+;     -- Output Ports driven by VCC           ; 0                     ; 0                              ;
+;     -- Input Ports with no Source           ; 0                     ; 0                              ;
+;     -- Output Ports with no Source          ; 0                     ; 0                              ;
+;     -- Input Ports with no Fanout           ; 0                     ; 0                              ;
+;     -- Output Ports with no Fanout          ; 0                     ; 0                              ;
++---------------------------------------------+-----------------------+--------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                                        ;
++-----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+---------------------+---------------------------+----------------------+-----------+
+; Name      ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard        ; Termination Control Block ; Location assigned by ; Slew Rate ;
++-----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+---------------------+---------------------------+----------------------+-----------+
+; CLOCK_50  ; R8    ; 3        ; 27           ; 0            ; 21           ; 1                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; 1.2-V HSTL Class II ; --                        ; User                 ; no        ;
+; UART_RX   ; B4    ; 8        ; 7            ; 34           ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V               ; --                        ; User                 ; no        ;
+; reset_btn ; J15   ; 5        ; 53           ; 14           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL         ; --                        ; User                 ; no        ;
++-----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+---------------------+---------------------------+----------------------+-----------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                             ;
++--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name         ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; GPIO_1_D[0]  ; F1    ; 1        ; 0            ; 23           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; GPIO_1_D[10] ; P11   ; 4        ; 38           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_D[11] ; R10   ; 4        ; 34           ; 0            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_D[12] ; N12   ; 4        ; 47           ; 0            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_D[13] ; P9    ; 4        ; 38           ; 0            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_D[14] ; N9    ; 4        ; 29           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_D[15] ; N11   ; 4        ; 43           ; 0            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_D[16] ; L16   ; 5        ; 53           ; 11           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_D[17] ; K16   ; 5        ; 53           ; 12           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_D[18] ; R16   ; 5        ; 53           ; 8            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_D[19] ; L15   ; 5        ; 53           ; 11           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_D[1]  ; A10   ; 7        ; 34           ; 34           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; GPIO_1_D[20] ; P15   ; 5        ; 53           ; 6            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_D[21] ; P16   ; 5        ; 53           ; 7            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_D[22] ; R14   ; 4        ; 49           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_D[23] ; N16   ; 5        ; 53           ; 9            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_D[24] ; N15   ; 5        ; 53           ; 9            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_D[25] ; P14   ; 4        ; 49           ; 0            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_D[26] ; L14   ; 5        ; 53           ; 9            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_D[27] ; N14   ; 5        ; 53           ; 6            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_D[28] ; M10   ; 4        ; 43           ; 0            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_D[29] ; L13   ; 5        ; 53           ; 10           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_D[2]  ; T14   ; 4        ; 45           ; 0            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_D[30] ; J16   ; 5        ; 53           ; 14           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_D[31] ; K15   ; 5        ; 53           ; 13           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_D[32] ; J13   ; 5        ; 53           ; 16           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_D[33] ; J14   ; 5        ; 53           ; 15           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_D[3]  ; B5    ; 8        ; 11           ; 34           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; GPIO_1_D[4]  ; R13   ; 4        ; 40           ; 0            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_D[5]  ; F8    ; 8        ; 20           ; 34           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; GPIO_1_D[6]  ; R12   ; 4        ; 36           ; 0            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_D[7]  ; B16   ; 6        ; 53           ; 22           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; GPIO_1_D[8]  ; T10   ; 4        ; 34           ; 0            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_D[9]  ; R11   ; 4        ; 34           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LED[0]       ; A15   ; 7        ; 38           ; 34           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LED[1]       ; A13   ; 7        ; 49           ; 34           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LED[2]       ; B13   ; 7        ; 49           ; 34           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LED[3]       ; A11   ; 7        ; 40           ; 34           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LED[4]       ; D1    ; 1        ; 0            ; 25           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LED[5]       ; F3    ; 1        ; 0            ; 26           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LED[6]       ; B1    ; 1        ; 0            ; 28           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LED[7]       ; L3    ; 2        ; 0            ; 10           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; UART_TX      ; A3    ; 8        ; 7            ; 34           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
++--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Dual Purpose and Dedicated Pins                                                                                         ;
++----------+-----------------------------+--------------------------+-------------------------+---------------------------+
+; Location ; Pin Name                    ; Reserved As              ; User Signal Name        ; Pin Type                  ;
++----------+-----------------------------+--------------------------+-------------------------+---------------------------+
+; C1       ; DIFFIO_L3n, DATA1, ASDO     ; As input tri-stated      ; ~ALTERA_ASDO_DATA1~     ; Dual Purpose Pin          ;
+; D2       ; DIFFIO_L4p, FLASH_nCE, nCSO ; As input tri-stated      ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin          ;
+; F4       ; nSTATUS                     ; -                        ; -                       ; Dedicated Programming Pin ;
+; H1       ; DCLK                        ; As output driving ground ; ~ALTERA_DCLK~           ; Dual Purpose Pin          ;
+; H2       ; DATA0                       ; As input tri-stated      ; ~ALTERA_DATA0~          ; Dual Purpose Pin          ;
+; H5       ; nCONFIG                     ; -                        ; -                       ; Dedicated Programming Pin ;
+; J3       ; nCE                         ; -                        ; -                       ; Dedicated Programming Pin ;
+; J16      ; DIFFIO_R9n, DEV_OE          ; Use as regular IO        ; GPIO_1_D[30]            ; Dual Purpose Pin          ;
+; J15      ; DIFFIO_R9p, DEV_CLRn        ; Use as regular IO        ; reset_btn               ; Dual Purpose Pin          ;
+; H14      ; CONF_DONE                   ; -                        ; -                       ; Dedicated Programming Pin ;
+; H13      ; MSEL0                       ; -                        ; -                       ; Dedicated Programming Pin ;
+; H12      ; MSEL1                       ; -                        ; -                       ; Dedicated Programming Pin ;
+; G12      ; MSEL2                       ; -                        ; -                       ; Dedicated Programming Pin ;
+; G12      ; MSEL3                       ; -                        ; -                       ; Dedicated Programming Pin ;
+; F16      ; DIFFIO_R4n, nCEO            ; Use as programming pin   ; ~ALTERA_nCEO~           ; Dual Purpose Pin          ;
+; A15      ; DIFFIO_T19n, PADD1          ; Use as regular IO        ; LED[0]                  ; Dual Purpose Pin          ;
+; A10      ; DIFFIO_T16n, PADD5          ; Use as regular IO        ; GPIO_1_D[1]             ; Dual Purpose Pin          ;
+; F8       ; DIFFIO_T10p, DATA3          ; Use as regular IO        ; GPIO_1_D[5]             ; Dual Purpose Pin          ;
+; B5       ; DIFFIO_T5p, DATA8           ; Use as regular IO        ; GPIO_1_D[3]             ; Dual Purpose Pin          ;
+; B4       ; DIFFIO_T3p, DATA11          ; Use as regular IO        ; UART_RX                 ; Dual Purpose Pin          ;
++----------+-----------------------------+--------------------------+-------------------------+---------------------------+
+
+
++------------------------------------------------------------+
+; I/O Bank Usage                                             ;
++----------+------------------+---------------+--------------+
+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ;
++----------+------------------+---------------+--------------+
+; 1        ; 8 / 14 ( 57 % )  ; 3.3V          ; --           ;
+; 2        ; 1 / 16 ( 6 % )   ; 3.3V          ; --           ;
+; 3        ; 1 / 25 ( 4 % )   ; 1.2V          ; 0.6V         ;
+; 4        ; 14 / 20 ( 70 % ) ; 3.3V          ; --           ;
+; 5        ; 16 / 18 ( 89 % ) ; 3.3V          ; --           ;
+; 6        ; 2 / 13 ( 15 % )  ; 3.3V          ; --           ;
+; 7        ; 5 / 24 ( 21 % )  ; 3.3V          ; --           ;
+; 8        ; 4 / 24 ( 17 % )  ; 3.3V          ; --           ;
++----------+------------------+---------------+--------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                                               ;
++----------+------------+----------+-----------------------------------------------------------+--------+---------------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                            ; Dir.   ; I/O Standard        ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+-----------------------------------------------------------+--------+---------------------+---------+------------+-----------------+----------+--------------+
+; A1       ;            ; 8        ; VCCIO8                                                    ; power  ;                     ; 3.3V    ; --         ;                 ; --       ; --           ;
+; A2       ; 238        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; A3       ; 239        ; 8        ; UART_TX                                                   ; output ; 3.3-V LVTTL         ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A4       ; 236        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; A5       ; 232        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; A6       ; 225        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; A7       ; 220        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; A8       ; 211        ; 8        ; GND+                                                      ;        ;                     ;         ; Column I/O ;                 ; --       ; --           ;
+; A9       ; 209        ; 7        ; GND+                                                      ;        ;                     ;         ; Column I/O ;                 ; --       ; --           ;
+; A10      ; 198        ; 7        ; GPIO_1_D[1]                                               ; output ; 3.3-V LVTTL         ;         ; Column I/O ; N               ; no       ; Off          ;
+; A11      ; 188        ; 7        ; LED[3]                                                    ; output ; 3.3-V LVTTL         ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A12      ; 186        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; A13      ; 179        ; 7        ; LED[1]                                                    ; output ; 3.3-V LVTTL         ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A14      ; 181        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; A15      ; 191        ; 7        ; LED[0]                                                    ; output ; 3.3-V LVTTL         ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A16      ;            ; 7        ; VCCIO7                                                    ; power  ;                     ; 3.3V    ; --         ;                 ; --       ; --           ;
+; B1       ; 5          ; 1        ; LED[6]                                                    ; output ; 3.3-V LVTTL         ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; B2       ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; B3       ; 242        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; B4       ; 237        ; 8        ; UART_RX                                                   ; input  ; 2.5 V               ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B5       ; 233        ; 8        ; GPIO_1_D[3]                                               ; output ; 3.3-V LVTTL         ;         ; Column I/O ; N               ; no       ; Off          ;
+; B6       ; 226        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; B7       ; 221        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; B8       ; 212        ; 8        ; GND+                                                      ;        ;                     ;         ; Column I/O ;                 ; --       ; --           ;
+; B9       ; 210        ; 7        ; GND+                                                      ;        ;                     ;         ; Column I/O ;                 ; --       ; --           ;
+; B10      ; 199        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; B11      ; 189        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; B12      ; 187        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; B13      ; 180        ; 7        ; LED[2]                                                    ; output ; 3.3-V LVTTL         ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B14      ; 182        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; B15      ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; B16      ; 164        ; 6        ; GPIO_1_D[7]                                               ; output ; 3.3-V LVTTL         ;         ; Row I/O    ; N               ; no       ; Off          ;
+; C1       ; 7          ; 1        ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP     ; input  ; 3.3-V LVTTL         ;         ; Row I/O    ; N               ; no       ; On           ;
+; C2       ; 6          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Row I/O    ;                 ; no       ; On           ;
+; C3       ; 245        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; C4       ;            ; 8        ; VCCIO8                                                    ; power  ;                     ; 3.3V    ; --         ;                 ; --       ; --           ;
+; C5       ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; C6       ; 224        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; --       ; --           ;
+; C7       ;            ; 8        ; VCCIO8                                                    ; power  ;                     ; 3.3V    ; --         ;                 ; --       ; --           ;
+; C8       ; 215        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; C9       ; 200        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; C10      ;            ; 7        ; VCCIO7                                                    ; power  ;                     ; 3.3V    ; --         ;                 ; --       ; --           ;
+; C11      ; 190        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; --       ; --           ;
+; C12      ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; C13      ;            ; 7        ; VCCIO7                                                    ; power  ;                     ; 3.3V    ; --         ;                 ; --       ; --           ;
+; C14      ; 175        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; C15      ; 174        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Row I/O    ;                 ; no       ; On           ;
+; C16      ; 173        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Row I/O    ;                 ; no       ; On           ;
+; D1       ; 10         ; 1        ; LED[4]                                                    ; output ; 3.3-V LVTTL         ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; D2       ; 9          ; 1        ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 3.3-V LVTTL         ;         ; Row I/O    ; N               ; no       ; On           ;
+; D3       ; 246        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; D4       ;            ;          ; VCCD_PLL3                                                 ; power  ;                     ; 1.2V    ; --         ;                 ; --       ; --           ;
+; D5       ; 241        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; D6       ; 234        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; D7       ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; D8       ; 216        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; D9       ; 201        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; D10      ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; D11      ; 177        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; D12      ; 178        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; D13      ;            ;          ; VCCD_PLL2                                                 ; power  ;                     ; 1.2V    ; --         ;                 ; --       ; --           ;
+; D14      ; 176        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; D15      ; 170        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Row I/O    ;                 ; no       ; On           ;
+; D16      ; 169        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Row I/O    ;                 ; no       ; On           ;
+; E1       ; 26         ; 1        ; GND+                                                      ;        ;                     ;         ; Row I/O    ;                 ; --       ; --           ;
+; E2       ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; E3       ;            ; 1        ; VCCIO1                                                    ; power  ;                     ; 3.3V    ; --         ;                 ; --       ; --           ;
+; E4       ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; E5       ;            ;          ; GNDA3                                                     ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; E6       ; 231        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; E7       ; 227        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; E8       ; 218        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; E9       ; 205        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; E10      ; 184        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; E11      ; 183        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; E12      ;            ;          ; GNDA2                                                     ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; E13      ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; E14      ;            ; 6        ; VCCIO6                                                    ; power  ;                     ; 3.3V    ; --         ;                 ; --       ; --           ;
+; E15      ; 151        ; 6        ; GND+                                                      ;        ;                     ;         ; Row I/O    ;                 ; --       ; --           ;
+; E16      ; 150        ; 6        ; GND+                                                      ;        ;                     ;         ; Row I/O    ;                 ; --       ; --           ;
+; F1       ; 14         ; 1        ; GPIO_1_D[0]                                               ; output ; 3.3-V LVTTL         ;         ; Row I/O    ; N               ; no       ; Off          ;
+; F2       ; 13         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Row I/O    ;                 ; no       ; On           ;
+; F3       ; 8          ; 1        ; LED[5]                                                    ; output ; 3.3-V LVTTL         ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F4       ; 11         ; 1        ; ^nSTATUS                                                  ;        ;                     ;         ; --         ;                 ; --       ; --           ;
+; F5       ;            ; --       ; VCCA3                                                     ; power  ;                     ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F6       ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; F7       ;            ;          ; VCCINT                                                    ; power  ;                     ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F8       ; 219        ; 8        ; GPIO_1_D[5]                                               ; output ; 3.3-V LVTTL         ;         ; Column I/O ; N               ; no       ; Off          ;
+; F9       ; 197        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; F10      ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; F11      ;            ;          ; VCCINT                                                    ; power  ;                     ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F12      ;            ; --       ; VCCA2                                                     ; power  ;                     ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F13      ; 161        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Row I/O    ;                 ; no       ; On           ;
+; F14      ; 167        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Row I/O    ;                 ; --       ; --           ;
+; F15      ; 163        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Row I/O    ;                 ; no       ; On           ;
+; F16      ; 162        ; 6        ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN                ; output ; 3.3-V LVTTL         ;         ; Row I/O    ; N               ; no       ; Off          ;
+; G1       ; 16         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Row I/O    ;                 ; no       ; On           ;
+; G2       ; 15         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Row I/O    ;                 ; no       ; On           ;
+; G3       ;            ; 1        ; VCCIO1                                                    ; power  ;                     ; 3.3V    ; --         ;                 ; --       ; --           ;
+; G4       ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; G5       ; 12         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Row I/O    ;                 ; no       ; On           ;
+; G6       ;            ;          ; VCCINT                                                    ; power  ;                     ; 1.2V    ; --         ;                 ; --       ; --           ;
+; G7       ;            ;          ; VCCINT                                                    ; power  ;                     ; 1.2V    ; --         ;                 ; --       ; --           ;
+; G8       ;            ;          ; VCCINT                                                    ; power  ;                     ; 1.2V    ; --         ;                 ; --       ; --           ;
+; G9       ;            ;          ; VCCINT                                                    ; power  ;                     ; 1.2V    ; --         ;                 ; --       ; --           ;
+; G10      ;            ;          ; VCCINT                                                    ; power  ;                     ; 1.2V    ; --         ;                 ; --       ; --           ;
+; G11      ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; G12      ; 155        ; 6        ; ^MSEL2                                                    ;        ;                     ;         ; --         ;                 ; --       ; --           ;
+; G12      ; 156        ; 6        ; ^MSEL3                                                    ;        ;                     ;         ; --         ;                 ; --       ; --           ;
+; G13      ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; G14      ;            ; 6        ; VCCIO6                                                    ; power  ;                     ; 3.3V    ; --         ;                 ; --       ; --           ;
+; G15      ; 160        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Row I/O    ;                 ; no       ; On           ;
+; G16      ; 159        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Row I/O    ;                 ; no       ; On           ;
+; H1       ; 17         ; 1        ; ~ALTERA_DCLK~                                             ; output ; 3.3-V LVTTL         ;         ; Row I/O    ; N               ; no       ; On           ;
+; H2       ; 18         ; 1        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP          ; input  ; 3.3-V LVTTL         ;         ; Row I/O    ; N               ; no       ; On           ;
+; H3       ; 21         ; 1        ; #TCK                                                      ; input  ;                     ;         ; --         ;                 ; --       ; --           ;
+; H4       ; 20         ; 1        ; #TDI                                                      ; input  ;                     ;         ; --         ;                 ; --       ; --           ;
+; H5       ; 19         ; 1        ; ^nCONFIG                                                  ;        ;                     ;         ; --         ;                 ; --       ; --           ;
+; H6       ;            ;          ; VCCINT                                                    ; power  ;                     ; 1.2V    ; --         ;                 ; --       ; --           ;
+; H7       ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; H8       ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; H9       ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; H10      ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; H11      ;            ;          ; VCCINT                                                    ; power  ;                     ; 1.2V    ; --         ;                 ; --       ; --           ;
+; H12      ; 154        ; 6        ; ^MSEL1                                                    ;        ;                     ;         ; --         ;                 ; --       ; --           ;
+; H13      ; 153        ; 6        ; ^MSEL0                                                    ;        ;                     ;         ; --         ;                 ; --       ; --           ;
+; H14      ; 152        ; 6        ; ^CONF_DONE                                                ;        ;                     ;         ; --         ;                 ; --       ; --           ;
+; H15      ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; H16      ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; J1       ; 30         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Row I/O    ;                 ; no       ; On           ;
+; J2       ; 29         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Row I/O    ;                 ; no       ; On           ;
+; J3       ; 24         ; 1        ; ^nCE                                                      ;        ;                     ;         ; --         ;                 ; --       ; --           ;
+; J4       ; 23         ; 1        ; #TDO                                                      ; output ;                     ;         ; --         ;                 ; --       ; --           ;
+; J5       ; 22         ; 1        ; #TMS                                                      ; input  ;                     ;         ; --         ;                 ; --       ; --           ;
+; J6       ;            ;          ; VCCINT                                                    ; power  ;                     ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J7       ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; J8       ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; J9       ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; J10      ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; J11      ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; J12      ;            ;          ; VCCINT                                                    ; power  ;                     ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J13      ; 146        ; 5        ; GPIO_1_D[32]                                              ; output ; 3.3-V LVTTL         ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J14      ; 144        ; 5        ; GPIO_1_D[33]                                              ; output ; 3.3-V LVTTL         ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J15      ; 143        ; 5        ; reset_btn                                                 ; input  ; 3.3-V LVTTL         ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J16      ; 142        ; 5        ; GPIO_1_D[30]                                              ; output ; 3.3-V LVTTL         ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K1       ; 37         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Row I/O    ;                 ; no       ; On           ;
+; K2       ; 36         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Row I/O    ;                 ; no       ; On           ;
+; K3       ;            ; 2        ; VCCIO2                                                    ; power  ;                     ; 3.3V    ; --         ;                 ; --       ; --           ;
+; K4       ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; K5       ; 45         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Row I/O    ;                 ; no       ; On           ;
+; K6       ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; K7       ;            ;          ; VCCINT                                                    ; power  ;                     ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K8       ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; K9       ;            ;          ; VCCINT                                                    ; power  ;                     ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K10      ;            ;          ; VCCINT                                                    ; power  ;                     ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K11      ;            ;          ; VCCINT                                                    ; power  ;                     ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K12      ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; K13      ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; K14      ;            ; 5        ; VCCIO5                                                    ; power  ;                     ; 3.3V    ; --         ;                 ; --       ; --           ;
+; K15      ; 141        ; 5        ; GPIO_1_D[31]                                              ; output ; 3.3-V LVTTL         ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K16      ; 140        ; 5        ; GPIO_1_D[17]                                              ; output ; 3.3-V LVTTL         ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; L1       ; 39         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Row I/O    ;                 ; no       ; On           ;
+; L2       ; 38         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Row I/O    ;                 ; no       ; On           ;
+; L3       ; 40         ; 2        ; LED[7]                                                    ; output ; 3.3-V LVTTL         ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; L4       ; 46         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Row I/O    ;                 ; no       ; On           ;
+; L5       ;            ; --       ; VCCA1                                                     ; power  ;                     ; 2.5V    ; --         ;                 ; --       ; --           ;
+; L6       ;            ;          ; VCCINT                                                    ; power  ;                     ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L7       ; 75         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; L8       ; 79         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; L9       ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; L10      ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; L11      ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; L12      ;            ; --       ; VCCA4                                                     ; power  ;                     ; 2.5V    ; --         ;                 ; --       ; --           ;
+; L13      ; 136        ; 5        ; GPIO_1_D[29]                                              ; output ; 3.3-V LVTTL         ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; L14      ; 134        ; 5        ; GPIO_1_D[26]                                              ; output ; 3.3-V LVTTL         ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; L15      ; 138        ; 5        ; GPIO_1_D[19]                                              ; output ; 3.3-V LVTTL         ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; L16      ; 137        ; 5        ; GPIO_1_D[16]                                              ; output ; 3.3-V LVTTL         ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; M1       ; 28         ; 2        ; GND+                                                      ;        ;                     ;         ; Row I/O    ;                 ; --       ; --           ;
+; M2       ; 27         ; 2        ; GND+                                                      ;        ;                     ;         ; Row I/O    ;                 ; --       ; --           ;
+; M3       ;            ; 2        ; VCCIO2                                                    ; power  ;                     ; 3.3V    ; --         ;                 ; --       ; --           ;
+; M4       ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; M5       ;            ;          ; GNDA1                                                     ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; M6       ; 64         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; M7       ; 68         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; M8       ; 81         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; M9       ;            ;          ; VCCINT                                                    ; power  ;                     ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M10      ; 111        ; 4        ; GPIO_1_D[28]                                              ; output ; 3.3-V LVTTL         ;         ; Column I/O ; Y               ; no       ; Off          ;
+; M11      ;            ;          ; VCCINT                                                    ; power  ;                     ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M12      ;            ;          ; GNDA4                                                     ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; M13      ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; M14      ;            ; 5        ; VCCIO5                                                    ; power  ;                     ; 3.3V    ; --         ;                 ; --       ; --           ;
+; M15      ; 149        ; 5        ; GND+                                                      ;        ;                     ;         ; Row I/O    ;                 ; --       ; --           ;
+; M16      ; 148        ; 5        ; GND+                                                      ;        ;                     ;         ; Row I/O    ;                 ; --       ; --           ;
+; N1       ; 44         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Row I/O    ;                 ; no       ; On           ;
+; N2       ; 43         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Row I/O    ;                 ; no       ; On           ;
+; N3       ; 52         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; N4       ;            ;          ; VCCD_PLL1                                                 ; power  ;                     ; 1.2V    ; --         ;                 ; --       ; --           ;
+; N5       ; 62         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; N6       ; 63         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; N7       ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; N8       ; 82         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; N9       ; 93         ; 4        ; GPIO_1_D[14]                                              ; output ; 3.3-V LVTTL         ;         ; Column I/O ; Y               ; no       ; Off          ;
+; N10      ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; N11      ; 112        ; 4        ; GPIO_1_D[15]                                              ; output ; 3.3-V LVTTL         ;         ; Column I/O ; Y               ; no       ; Off          ;
+; N12      ; 117        ; 4        ; GPIO_1_D[12]                                              ; output ; 3.3-V LVTTL         ;         ; Column I/O ; Y               ; no       ; Off          ;
+; N13      ;            ;          ; VCCD_PLL4                                                 ; power  ;                     ; 1.2V    ; --         ;                 ; --       ; --           ;
+; N14      ; 126        ; 5        ; GPIO_1_D[27]                                              ; output ; 3.3-V LVTTL         ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; N15      ; 133        ; 5        ; GPIO_1_D[24]                                              ; output ; 3.3-V LVTTL         ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; N16      ; 132        ; 5        ; GPIO_1_D[23]                                              ; output ; 3.3-V LVTTL         ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; P1       ; 51         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Row I/O    ;                 ; no       ; On           ;
+; P2       ; 50         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Row I/O    ;                 ; no       ; On           ;
+; P3       ; 53         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; P4       ;            ; 3        ; VCCIO3                                                    ; power  ;                     ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P5       ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; P6       ; 67         ; 3        ; VREFB3N0                                                  ;        ;                     ; 0.6V    ; Column I/O ;                 ; --       ; --           ;
+; P7       ;            ; 3        ; VCCIO3                                                    ; power  ;                     ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P8       ; 85         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; P9       ; 105        ; 4        ; GPIO_1_D[13]                                              ; output ; 3.3-V LVTTL         ;         ; Column I/O ; Y               ; no       ; Off          ;
+; P10      ;            ; 4        ; VCCIO4                                                    ; power  ;                     ; 3.3V    ; --         ;                 ; --       ; --           ;
+; P11      ; 106        ; 4        ; GPIO_1_D[10]                                              ; output ; 3.3-V LVTTL         ;         ; Column I/O ; Y               ; no       ; Off          ;
+; P12      ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; P13      ;            ; 4        ; VCCIO4                                                    ; power  ;                     ; 3.3V    ; --         ;                 ; --       ; --           ;
+; P14      ; 119        ; 4        ; GPIO_1_D[25]                                              ; output ; 3.3-V LVTTL         ;         ; Column I/O ; Y               ; no       ; Off          ;
+; P15      ; 127        ; 5        ; GPIO_1_D[20]                                              ; output ; 3.3-V LVTTL         ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; P16      ; 128        ; 5        ; GPIO_1_D[21]                                              ; output ; 3.3-V LVTTL         ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; R1       ; 49         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Row I/O    ;                 ; no       ; On           ;
+; R2       ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; R3       ; 54         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; R4       ; 60         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; R5       ; 71         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; R6       ; 73         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; R7       ; 76         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; R8       ; 86         ; 3        ; CLOCK_50                                                  ; input  ; 1.2-V HSTL Class II ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R9       ; 88         ; 4        ; GND+                                                      ;        ;                     ;         ; Column I/O ;                 ; --       ; --           ;
+; R10      ; 96         ; 4        ; GPIO_1_D[11]                                              ; output ; 3.3-V LVTTL         ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R11      ; 98         ; 4        ; GPIO_1_D[9]                                               ; output ; 3.3-V LVTTL         ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R12      ; 100        ; 4        ; GPIO_1_D[6]                                               ; output ; 3.3-V LVTTL         ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R13      ; 107        ; 4        ; GPIO_1_D[4]                                               ; output ; 3.3-V LVTTL         ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R14      ; 120        ; 4        ; GPIO_1_D[22]                                              ; output ; 3.3-V LVTTL         ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R15      ;            ;          ; GND                                                       ; gnd    ;                     ;         ; --         ;                 ; --       ; --           ;
+; R16      ; 129        ; 5        ; GPIO_1_D[18]                                              ; output ; 3.3-V LVTTL         ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; T1       ;            ; 3        ; VCCIO3                                                    ; power  ;                     ; 1.2V    ; --         ;                 ; --       ; --           ;
+; T2       ; 59         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; T3       ; 55         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; T4       ; 61         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; T5       ; 72         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; T6       ; 74         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; T7       ; 77         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; T8       ; 87         ; 3        ; GND+                                                      ;        ;                     ;         ; Column I/O ;                 ; --       ; --           ;
+; T9       ; 89         ; 4        ; GND+                                                      ;        ;                     ;         ; Column I/O ;                 ; --       ; --           ;
+; T10      ; 97         ; 4        ; GPIO_1_D[8]                                               ; output ; 3.3-V LVTTL         ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T11      ; 99         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; T12      ; 101        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; T13      ; 108        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; T14      ; 115        ; 4        ; GPIO_1_D[2]                                               ; output ; 3.3-V LVTTL         ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T15      ; 116        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;                     ;         ; Column I/O ;                 ; no       ; On           ;
+; T16      ;            ; 4        ; VCCIO4                                                    ; power  ;                     ; 3.3V    ; --         ;                 ; --       ; --           ;
++----------+------------+----------+-----------------------------------------------------------+--------+---------------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-----------------------------------------------------------------------------------------------------------------+
+; PLL Summary                                                                                                     ;
++-------------------------------+---------------------------------------------------------------------------------+
+; Name                          ; pll_sys:pll_sys_inst|altpll:altpll_component|pll_sys_altpll:auto_generated|pll1 ;
++-------------------------------+---------------------------------------------------------------------------------+
+; SDC pin name                  ; pll_sys_inst|altpll_component|auto_generated|pll1                               ;
+; PLL mode                      ; Normal                                                                          ;
+; Compensate clock              ; clock0                                                                          ;
+; Compensated input/output pins ; --                                                                              ;
+; Switchover type               ; --                                                                              ;
+; Input frequency 0             ; 50.0 MHz                                                                        ;
+; Input frequency 1             ; --                                                                              ;
+; Nominal PFD frequency         ; 50.0 MHz                                                                        ;
+; Nominal VCO frequency         ; 900.0 MHz                                                                       ;
+; VCO post scale K counter      ; --                                                                              ;
+; VCO frequency control         ; Auto                                                                            ;
+; VCO phase shift step          ; 138 ps                                                                          ;
+; VCO multiply                  ; --                                                                              ;
+; VCO divide                    ; --                                                                              ;
+; Freq min lock                 ; 33.35 MHz                                                                       ;
+; Freq max lock                 ; 72.24 MHz                                                                       ;
+; M VCO Tap                     ; 0                                                                               ;
+; M Initial                     ; 1                                                                               ;
+; M value                       ; 18                                                                              ;
+; N value                       ; 1                                                                               ;
+; Charge pump current           ; setting 1                                                                       ;
+; Loop filter resistance        ; setting 27                                                                      ;
+; Loop filter capacitance       ; setting 0                                                                       ;
+; Bandwidth                     ; 1.03 MHz to 1.97 MHz                                                            ;
+; Bandwidth type                ; Medium                                                                          ;
+; Real time reconfigurable      ; Off                                                                             ;
+; Scan chain MIF file           ; --                                                                              ;
+; Preserve PLL counter order    ; Off                                                                             ;
+; PLL location                  ; PLL_4                                                                           ;
+; Inclk0 signal                 ; CLOCK_50                                                                        ;
+; Inclk1 signal                 ; --                                                                              ;
+; Inclk0 signal type            ; Dedicated Pin                                                                   ;
+; Inclk1 signal type            ; --                                                                              ;
++-------------------------------+---------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; PLL Usage                                                                                                                                                                                                                                                                                                                        ;
++---------------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+--------------+---------------+---------+---------+----------------------------------------------------------+
+; Name                                                                                        ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift ; Phase Shift Step ; Duty Cycle ; Counter ; Counter Value ; High / Low   ; Cascade Input ; Initial ; VCO Tap ; SDC Pin Name                                             ;
++---------------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+--------------+---------------+---------+---------+----------------------------------------------------------+
+; pll_sys:pll_sys_inst|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] ; clock0       ; 2    ; 1   ; 100.0 MHz        ; 0 (0 ps)    ; 5.00 (138 ps)    ; 50/50      ; C0      ; 9             ; 5/4 Odd      ; --            ; 1       ; 0       ; pll_sys_inst|altpll_component|auto_generated|pll1|clk[0] ;
+; pll_sys:pll_sys_inst|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[1] ; clock1       ; 9    ; 61  ; 7.38 MHz         ; 0 (0 ps)    ; 0.37 (138 ps)    ; 50/50      ; C2      ; 122           ; 61/61 Even   ; --            ; 1       ; 0       ; pll_sys_inst|altpll_component|auto_generated|pll1|clk[1] ;
+; pll_sys:pll_sys_inst|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[2] ; clock2       ; 9    ; 244 ; 1.84 MHz         ; 0 (0 ps)    ; 0.09 (138 ps)    ; 50/50      ; C1      ; 488           ; 244/244 Even ; --            ; 1       ; 0       ; pll_sys_inst|altpll_component|auto_generated|pll1|clk[2] ;
++---------------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+--------------+---------------+---------+---------+----------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                  ;
++----------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node                   ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name                                                                                      ; Library Name ;
++----------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------------------------+--------------+
+; |xoro_top                                    ; 2973 (11)   ; 1354 (9)                  ; 0 (0)         ; 330016      ; 51   ; 8            ; 0       ; 4         ; 46   ; 0            ; 1619 (2)     ; 230 (0)           ; 1124 (10)        ; |xoro_top                                                                                                ; work         ;
+;    |AsyncReceiver:uartRx|                    ; 121 (62)    ; 78 (36)                   ; 0 (0)         ; 256         ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 43 (25)      ; 9 (2)             ; 69 (51)          ; |xoro_top|AsyncReceiver:uartRx                                                                           ; work         ;
+;       |Fifo:fifo_1|                          ; 60 (60)     ; 42 (42)                   ; 0 (0)         ; 256         ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 18 (18)      ; 7 (7)             ; 35 (35)          ; |xoro_top|AsyncReceiver:uartRx|Fifo:fifo_1                                                               ; work         ;
+;          |altsyncram:mem_rtl_0|              ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 256         ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |xoro_top|AsyncReceiver:uartRx|Fifo:fifo_1|altsyncram:mem_rtl_0                                          ; work         ;
+;             |altsyncram_s9c1:auto_generated| ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 256         ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |xoro_top|AsyncReceiver:uartRx|Fifo:fifo_1|altsyncram:mem_rtl_0|altsyncram_s9c1:auto_generated           ; work         ;
+;    |Memory:mem|                              ; 214 (194)   ; 192 (180)                 ; 0 (0)         ; 327712      ; 48   ; 0            ; 0       ; 0         ; 0    ; 0            ; 22 (14)      ; 82 (78)           ; 110 (102)        ; |xoro_top|Memory:mem                                                                                     ; work         ;
+;       |altsyncram:memory_1_symbol0_rtl_0|    ; 5 (0)       ; 3 (0)                     ; 0 (0)         ; 81928       ; 12   ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (0)        ; 1 (0)             ; 2 (0)            ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol0_rtl_0                                                   ; work         ;
+;          |altsyncram_bdi1:auto_generated|    ; 5 (3)       ; 3 (3)                     ; 0 (0)         ; 81928       ; 12   ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (0)        ; 1 (1)             ; 2 (2)            ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol0_rtl_0|altsyncram_bdi1:auto_generated                    ; work         ;
+;             |decode_jsa:decode2|             ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol0_rtl_0|altsyncram_bdi1:auto_generated|decode_jsa:decode2 ; work         ;
+;       |altsyncram:memory_1_symbol1_rtl_0|    ; 5 (0)       ; 3 (0)                     ; 0 (0)         ; 81928       ; 12   ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (0)        ; 1 (0)             ; 2 (0)            ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol1_rtl_0                                                   ; work         ;
+;          |altsyncram_cdi1:auto_generated|    ; 5 (3)       ; 3 (3)                     ; 0 (0)         ; 81928       ; 12   ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (0)        ; 1 (1)             ; 2 (2)            ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol1_rtl_0|altsyncram_cdi1:auto_generated                    ; work         ;
+;             |decode_jsa:decode2|             ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol1_rtl_0|altsyncram_cdi1:auto_generated|decode_jsa:decode2 ; work         ;
+;       |altsyncram:memory_1_symbol2_rtl_0|    ; 5 (0)       ; 3 (0)                     ; 0 (0)         ; 81928       ; 12   ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (0)        ; 1 (0)             ; 2 (0)            ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol2_rtl_0                                                   ; work         ;
+;          |altsyncram_ddi1:auto_generated|    ; 5 (3)       ; 3 (3)                     ; 0 (0)         ; 81928       ; 12   ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (0)        ; 1 (1)             ; 2 (2)            ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol2_rtl_0|altsyncram_ddi1:auto_generated                    ; work         ;
+;             |decode_jsa:decode2|             ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol2_rtl_0|altsyncram_ddi1:auto_generated|decode_jsa:decode2 ; work         ;
+;       |altsyncram:memory_1_symbol3_rtl_0|    ; 5 (0)       ; 3 (0)                     ; 0 (0)         ; 81928       ; 12   ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (0)        ; 1 (0)             ; 2 (0)            ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol3_rtl_0                                                   ; work         ;
+;          |altsyncram_edi1:auto_generated|    ; 5 (3)       ; 3 (3)                     ; 0 (0)         ; 81928       ; 12   ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (0)        ; 1 (1)             ; 2 (2)            ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol3_rtl_0|altsyncram_edi1:auto_generated                    ; work         ;
+;             |decode_jsa:decode2|             ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol3_rtl_0|altsyncram_edi1:auto_generated|decode_jsa:decode2 ; work         ;
+;    |busInterface:busInterface|               ; 171 (171)   ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 109 (109)    ; 0 (0)             ; 62 (62)          ; |xoro_top|busInterface:busInterface                                                                      ; work         ;
+;    |gpio:gpio|                               ; 18 (18)     ; 17 (17)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 6 (6)             ; 11 (11)          ; |xoro_top|gpio:gpio                                                                                      ; work         ;
+;    |picorv32:cpu|                            ; 2234 (1749) ; 800 (533)                 ; 0 (0)         ; 2048        ; 2    ; 8            ; 0       ; 4         ; 0    ; 0            ; 1428 (1210)  ; 119 (86)          ; 687 (464)        ; |xoro_top|picorv32:cpu                                                                                   ; work         ;
+;       |altsyncram:cpuregs_rtl_0|             ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 1024        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |xoro_top|picorv32:cpu|altsyncram:cpuregs_rtl_0                                                          ; work         ;
+;          |altsyncram_trd1:auto_generated|    ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 1024        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |xoro_top|picorv32:cpu|altsyncram:cpuregs_rtl_0|altsyncram_trd1:auto_generated                           ; work         ;
+;       |altsyncram:cpuregs_rtl_1|             ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 1024        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |xoro_top|picorv32:cpu|altsyncram:cpuregs_rtl_1                                                          ; work         ;
+;          |altsyncram_trd1:auto_generated|    ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 1024        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |xoro_top|picorv32:cpu|altsyncram:cpuregs_rtl_1|altsyncram_trd1:auto_generated                           ; work         ;
+;       |picorv32_pcpi_div:pcpi_div|           ; 376 (376)   ; 200 (200)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 172 (172)    ; 33 (33)           ; 171 (171)        ; |xoro_top|picorv32:cpu|picorv32_pcpi_div:pcpi_div                                                        ; work         ;
+;       |picorv32_pcpi_fast_mul:pcpi_mul|      ; 116 (70)    ; 67 (67)                   ; 0 (0)         ; 0           ; 0    ; 8            ; 0       ; 4         ; 0    ; 0            ; 46 (0)       ; 0 (0)             ; 70 (70)          ; |xoro_top|picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul                                                   ; work         ;
+;          |lpm_mult:Mult0|                    ; 46 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 8            ; 0       ; 4         ; 0    ; 0            ; 46 (0)       ; 0 (0)             ; 0 (0)            ; |xoro_top|picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0                                    ; work         ;
+;             |mult_86t:auto_generated|        ; 46 (46)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 8            ; 0       ; 4         ; 0    ; 0            ; 46 (46)      ; 0 (0)             ; 0 (0)            ; |xoro_top|picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated            ; work         ;
+;    |pll_sys:pll_sys_inst|                    ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |xoro_top|pll_sys:pll_sys_inst                                                                           ; work         ;
+;       |altpll:altpll_component|              ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |xoro_top|pll_sys:pll_sys_inst|altpll:altpll_component                                                   ; work         ;
+;          |pll_sys_altpll:auto_generated|     ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |xoro_top|pll_sys:pll_sys_inst|altpll:altpll_component|pll_sys_altpll:auto_generated                     ; work         ;
+;    |prng:prng|                               ; 198 (35)    ; 193 (34)                  ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (1)        ; 5 (1)             ; 188 (33)         ; |xoro_top|prng:prng                                                                                      ; work         ;
+;       |xoroshiro128plus:prng|                ; 163 (163)   ; 159 (159)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 4 (4)             ; 155 (155)        ; |xoro_top|prng:prng|xoroshiro128plus:prng                                                                ; work         ;
+;    |timer:timer|                             ; 34 (34)     ; 33 (33)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 1 (1)             ; 32 (32)          ; |xoro_top|timer:timer                                                                                    ; work         ;
+;    |uartTx:uartTx|                           ; 40 (34)     ; 32 (26)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 8 (8)        ; 8 (8)             ; 24 (18)          ; |xoro_top|uartTx:uartTx                                                                                  ; work         ;
+;       |BaudRateGenerator:baudRateGenerator|  ; 6 (4)       ; 6 (4)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 6 (4)            ; |xoro_top|uartTx:uartTx|BaudRateGenerator:baudRateGenerator                                              ; work         ;
+;          |EdgeDetect:baudClockEdgeDetect|    ; 1 (1)       ; 1 (1)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |xoro_top|uartTx:uartTx|BaudRateGenerator:baudRateGenerator|EdgeDetect:baudClockEdgeDetect               ; work         ;
+;          |EdgeDetect:bitClockEdgeDetect|     ; 1 (1)       ; 1 (1)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |xoro_top|uartTx:uartTx|BaudRateGenerator:baudRateGenerator|EdgeDetect:bitClockEdgeDetect                ; work         ;
++----------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++----------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                          ;
++--------------+----------+---------------+---------------+-----------------------+-----+------+
+; Name         ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
++--------------+----------+---------------+---------------+-----------------------+-----+------+
+; reset_btn    ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; LED[0]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LED[1]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LED[2]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LED[3]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LED[4]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LED[5]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LED[6]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LED[7]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; UART_TX      ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[0]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[1]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[2]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[3]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[4]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[5]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[6]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[7]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[8]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[9]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[10] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[11] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[12] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[13] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[14] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[15] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[16] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[17] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[18] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[19] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[20] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[21] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[22] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[23] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[24] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[25] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[26] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[27] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[28] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[29] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[30] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[31] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[32] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_D[33] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; UART_RX      ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; CLOCK_50     ; Input    ; --            ; --            ; --                    ; --  ; --   ;
++--------------+----------+---------------+---------------+-----------------------+-----+------+
+
+
++-------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout                                    ;
++-------------------------------------+-------------------+---------+
+; Source Pin / Fanout                 ; Pad To Core Index ; Setting ;
++-------------------------------------+-------------------+---------+
+; reset_btn                           ;                   ;         ;
+; UART_RX                             ;                   ;         ;
+;      - AsyncReceiver:uartRx|rxSync1 ; 1                 ; 6       ;
+;      - GPIO_1_D[31]~output          ; 1                 ; 6       ;
+; CLOCK_50                            ;                   ;         ;
++-------------------------------------+-------------------+---------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                                                                                                                                                      ;
++-----------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+; Name                                                                                                      ; Location           ; Fan-Out ; Usage                      ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++-----------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+; AsyncReceiver:uartRx|Fifo:fifo_1|head[3]~0                                                                ; LCCOMB_X34_Y9_N14  ; 5       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; AsyncReceiver:uartRx|Fifo:fifo_1|mem~14                                                                   ; LCCOMB_X32_Y9_N14  ; 8       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; AsyncReceiver:uartRx|_zz_6~0                                                                              ; LCCOMB_X34_Y9_N20  ; 7       ; Write enable               ; no     ; --                   ; --               ; --                        ;
+; CLOCK_50                                                                                                  ; PIN_R8             ; 1       ; Clock                      ; no     ; --                   ; --               ; --                        ;
+; Memory:mem|altsyncram:memory_1_symbol0_rtl_0|altsyncram_bdi1:auto_generated|_~0                           ; LCCOMB_X23_Y19_N28 ; 12      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; Memory:mem|altsyncram:memory_1_symbol0_rtl_0|altsyncram_bdi1:auto_generated|decode_jsa:decode2|eq_node[0] ; LCCOMB_X25_Y13_N2  ; 8       ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; Memory:mem|altsyncram:memory_1_symbol0_rtl_0|altsyncram_bdi1:auto_generated|decode_jsa:decode2|eq_node[1] ; LCCOMB_X25_Y13_N24 ; 4       ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; Memory:mem|altsyncram:memory_1_symbol1_rtl_0|altsyncram_cdi1:auto_generated|_~0                           ; LCCOMB_X25_Y17_N14 ; 12      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; Memory:mem|altsyncram:memory_1_symbol1_rtl_0|altsyncram_cdi1:auto_generated|decode_jsa:decode2|eq_node[0] ; LCCOMB_X25_Y13_N16 ; 8       ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; Memory:mem|altsyncram:memory_1_symbol1_rtl_0|altsyncram_cdi1:auto_generated|decode_jsa:decode2|eq_node[1] ; LCCOMB_X25_Y13_N6  ; 4       ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; Memory:mem|altsyncram:memory_1_symbol2_rtl_0|altsyncram_ddi1:auto_generated|_~0                           ; LCCOMB_X21_Y12_N12 ; 12      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; Memory:mem|altsyncram:memory_1_symbol2_rtl_0|altsyncram_ddi1:auto_generated|decode_jsa:decode2|eq_node[0] ; LCCOMB_X25_Y13_N20 ; 8       ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; Memory:mem|altsyncram:memory_1_symbol2_rtl_0|altsyncram_ddi1:auto_generated|decode_jsa:decode2|eq_node[1] ; LCCOMB_X25_Y13_N14 ; 4       ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; Memory:mem|altsyncram:memory_1_symbol3_rtl_0|altsyncram_edi1:auto_generated|_~0                           ; LCCOMB_X25_Y24_N12 ; 12      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; Memory:mem|altsyncram:memory_1_symbol3_rtl_0|altsyncram_edi1:auto_generated|decode_jsa:decode2|eq_node[0] ; LCCOMB_X25_Y13_N26 ; 8       ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; Memory:mem|altsyncram:memory_1_symbol3_rtl_0|altsyncram_edi1:auto_generated|decode_jsa:decode2|eq_node[1] ; LCCOMB_X25_Y19_N12 ; 4       ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; gpio:gpio|gpio[0]~1                                                                                       ; LCCOMB_X25_Y12_N16 ; 8       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; picorv32:cpu|Selector61~0                                                                                 ; LCCOMB_X31_Y17_N30 ; 26      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; picorv32:cpu|always16~1                                                                                   ; LCCOMB_X32_Y18_N12 ; 4       ; Write enable               ; no     ; --                   ; --               ; --                        ;
+; picorv32:cpu|always5~1                                                                                    ; LCCOMB_X24_Y16_N22 ; 26      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; picorv32:cpu|always9~0                                                                                    ; LCCOMB_X28_Y18_N8  ; 63      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; picorv32:cpu|always9~1                                                                                    ; LCCOMB_X28_Y17_N0  ; 47      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; picorv32:cpu|cpu_state.cpu_state_ldmem                                                                    ; FF_X28_Y15_N15     ; 41      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; picorv32:cpu|instr_sltiu~0                                                                                ; LCCOMB_X28_Y20_N14 ; 23      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; picorv32:cpu|latched_rd[4]~0                                                                              ; LCCOMB_X27_Y16_N6  ; 5       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; picorv32:cpu|mem_addr[2]~16                                                                               ; LCCOMB_X28_Y16_N14 ; 150     ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; picorv32:cpu|mem_wdata[0]~2                                                                               ; LCCOMB_X28_Y16_N4  ; 32      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; picorv32:cpu|mem_wordsize.10                                                                              ; FF_X25_Y16_N25     ; 23      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; picorv32:cpu|mem_wordsize~10                                                                              ; LCCOMB_X29_Y16_N16 ; 3       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; picorv32:cpu|mem_wstrb[0]~4                                                                               ; LCCOMB_X29_Y17_N24 ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; picorv32:cpu|picorv32_pcpi_div:pcpi_div|dividend[0]~47                                                    ; LCCOMB_X39_Y11_N22 ; 32      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; picorv32:cpu|picorv32_pcpi_div:pcpi_div|outsign                                                           ; FF_X24_Y12_N23     ; 33      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; picorv32:cpu|picorv32_pcpi_div:pcpi_div|quotient_msk[4]~33                                                ; LCCOMB_X40_Y8_N14  ; 95      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; picorv32:cpu|picorv32_pcpi_div:pcpi_div|start                                                             ; LCCOMB_X39_Y10_N22 ; 100     ; Sync. clear, Sync. load    ; no     ; --                   ; --               ; --                        ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|always2~0                                                    ; LCCOMB_X36_Y12_N30 ; 5       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; picorv32:cpu|reg_op1[1]~6                                                                                 ; LCCOMB_X28_Y17_N4  ; 30      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; picorv32:cpu|reg_op2[25]~35                                                                               ; LCCOMB_X37_Y17_N14 ; 32      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; picorv32:cpu|reg_op2[28]~34                                                                               ; LCCOMB_X28_Y16_N24 ; 33      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; picorv32:cpu|reg_op2[28]~36                                                                               ; LCCOMB_X35_Y17_N28 ; 27      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; picorv32:cpu|reg_pc[22]~0                                                                                 ; LCCOMB_X30_Y21_N4  ; 61      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; pll_sys:pll_sys_inst|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0]               ; PLL_4              ; 1250    ; Clock                      ; yes    ; Global Clock         ; GCLK18           ; --                        ;
+; prng:prng|prng_clk                                                                                        ; FF_X27_Y17_N5      ; 159     ; Clock                      ; yes    ; Global Clock         ; GCLK11           ; --                        ;
+; resetn                                                                                                    ; FF_X27_Y9_N17      ; 225     ; Clock enable, Sync. clear  ; no     ; --                   ; --               ; --                        ;
+; resetn                                                                                                    ; FF_X27_Y9_N17      ; 242     ; Async. clear               ; yes    ; Global Clock         ; GCLK8            ; --                        ;
+; uartTx:uartTx|BaudRateGenerator:baudRateGenerator|EdgeDetect:baudClockEdgeDetect|io_q                     ; LCCOMB_X27_Y10_N4  ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; uartTx:uartTx|BaudRateGenerator:baudRateGenerator|EdgeDetect:bitClockEdgeDetect|io_q                      ; LCCOMB_X27_Y10_N16 ; 6       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; uartTx:uartTx|bitCount[3]~1                                                                               ; LCCOMB_X26_Y10_N26 ; 11      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; uartTx:uartTx|buffer[0]~0                                                                                 ; LCCOMB_X25_Y10_N2  ; 8       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
++-----------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals                                                                                                                                                                                                        ;
++---------------------------------------------------------------------------------------------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; Name                                                                                        ; Location      ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++---------------------------------------------------------------------------------------------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; pll_sys:pll_sys_inst|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] ; PLL_4         ; 1250    ; 94                                   ; Global Clock         ; GCLK18           ; --                        ;
+; pll_sys:pll_sys_inst|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[1] ; PLL_4         ; 1       ; 0                                    ; Global Clock         ; GCLK17           ; --                        ;
+; pll_sys:pll_sys_inst|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[2] ; PLL_4         ; 2       ; 0                                    ; Global Clock         ; GCLK19           ; --                        ;
+; prng:prng|prng_clk                                                                          ; FF_X27_Y17_N5 ; 159     ; 0                                    ; Global Clock         ; GCLK11           ; --                        ;
+; resetn                                                                                      ; FF_X27_Y9_N17 ; 242     ; 0                                    ; Global Clock         ; GCLK8            ; --                        ;
++---------------------------------------------------------------------------------------------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter RAM Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
++-------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+------------------------+------------------------+---------------+
+; Name                                                                                            ; Type ; Mode             ; Clock Mode   ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size  ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M9Ks ; MIF                                  ; Location                                                                                                                                                                                       ; Mixed Width RDW Mode ; Port A RDW Mode        ; Port B RDW Mode        ; Fits in MLABs ;
++-------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+------------------------+------------------------+---------------+
+; AsyncReceiver:uartRx|Fifo:fifo_1|altsyncram:mem_rtl_0|altsyncram_s9c1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 32           ; 8            ; 32           ; 8            ; yes                    ; no                      ; yes                    ; no                      ; 256   ; 32                          ; 8                           ; 32                          ; 8                           ; 256                 ; 1    ; None                                 ; M9K_X33_Y9_N0                                                                                                                                                                                  ; Don't care           ; New data with NBE Read ; New data with NBE Read ; No - Unknown  ;
+; Memory:mem|altsyncram:memory_1_symbol0_rtl_0|altsyncram_bdi1:auto_generated|ALTSYNCRAM          ; AUTO ; Simple Dual Port ; Dual Clocks  ; 10241        ; 8            ; 10241        ; 8            ; yes                    ; no                      ; yes                    ; no                      ; 81928 ; 10241                       ; 8                           ; 10241                       ; 8                           ; 81928               ; 12   ; db/xoro.ram0_Memory_a0c6519c.hdl.mif ; M9K_X22_Y19_N0, M9K_X22_Y15_N0, M9K_X22_Y21_N0, M9K_X22_Y16_N0, M9K_X22_Y23_N0, M9K_X22_Y17_N0, M9K_X22_Y8_N0, M9K_X22_Y11_N0, M9K_X22_Y20_N0, M9K_X22_Y13_N0, M9K_X22_Y10_N0, M9K_X22_Y9_N0   ; Don't care           ; New data with NBE Read ; New data with NBE Read ; No - Unknown  ;
+; Memory:mem|altsyncram:memory_1_symbol1_rtl_0|altsyncram_cdi1:auto_generated|ALTSYNCRAM          ; AUTO ; Simple Dual Port ; Dual Clocks  ; 10241        ; 8            ; 10241        ; 8            ; yes                    ; no                      ; yes                    ; no                      ; 81928 ; 10241                       ; 8                           ; 10241                       ; 8                           ; 81928               ; 12   ; db/xoro.ram1_Memory_a0c6519c.hdl.mif ; M9K_X22_Y18_N0, M9K_X22_Y14_N0, M9K_X33_Y14_N0, M9K_X33_Y15_N0, M9K_X33_Y20_N0, M9K_X33_Y18_N0, M9K_X22_Y22_N0, M9K_X33_Y11_N0, M9K_X33_Y22_N0, M9K_X33_Y16_N0, M9K_X33_Y13_N0, M9K_X33_Y21_N0 ; Don't care           ; New data with NBE Read ; New data with NBE Read ; No - Unknown  ;
+; Memory:mem|altsyncram:memory_1_symbol2_rtl_0|altsyncram_ddi1:auto_generated|ALTSYNCRAM          ; AUTO ; Simple Dual Port ; Dual Clocks  ; 10241        ; 8            ; 10241        ; 8            ; yes                    ; no                      ; yes                    ; no                      ; 81928 ; 10241                       ; 8                           ; 10241                       ; 8                           ; 81928               ; 12   ; db/xoro.ram2_Memory_a0c6519c.hdl.mif ; M9K_X33_Y6_N0, M9K_X33_Y8_N0, M9K_X33_Y7_N0, M9K_X33_Y12_N0, M9K_X22_Y12_N0, M9K_X33_Y10_N0, M9K_X33_Y4_N0, M9K_X22_Y6_N0, M9K_X33_Y5_N0, M9K_X22_Y5_N0, M9K_X22_Y4_N0, M9K_X22_Y7_N0          ; Don't care           ; New data with NBE Read ; New data with NBE Read ; No - Unknown  ;
+; Memory:mem|altsyncram:memory_1_symbol3_rtl_0|altsyncram_edi1:auto_generated|ALTSYNCRAM          ; AUTO ; Simple Dual Port ; Dual Clocks  ; 10241        ; 8            ; 10241        ; 8            ; yes                    ; no                      ; yes                    ; no                      ; 81928 ; 10241                       ; 8                           ; 10241                       ; 8                           ; 81928               ; 12   ; db/xoro.ram3_Memory_a0c6519c.hdl.mif ; M9K_X33_Y28_N0, M9K_X22_Y26_N0, M9K_X22_Y29_N0, M9K_X22_Y25_N0, M9K_X33_Y23_N0, M9K_X22_Y27_N0, M9K_X33_Y27_N0, M9K_X33_Y25_N0, M9K_X33_Y24_N0, M9K_X33_Y26_N0, M9K_X22_Y24_N0, M9K_X22_Y28_N0 ; Don't care           ; New data with NBE Read ; New data with NBE Read ; No - Unknown  ;
+; picorv32:cpu|altsyncram:cpuregs_rtl_0|altsyncram_trd1:auto_generated|ALTSYNCRAM                 ; AUTO ; Simple Dual Port ; Single Clock ; 32           ; 32           ; 32           ; 32           ; yes                    ; no                      ; yes                    ; no                      ; 1024  ; 32                          ; 32                          ; 32                          ; 32                          ; 1024                ; 1    ; None                                 ; M9K_X33_Y19_N0                                                                                                                                                                                 ; Don't care           ; New data with NBE Read ; New data with NBE Read ; No - Unknown  ;
+; picorv32:cpu|altsyncram:cpuregs_rtl_1|altsyncram_trd1:auto_generated|ALTSYNCRAM                 ; AUTO ; Simple Dual Port ; Single Clock ; 32           ; 32           ; 32           ; 32           ; yes                    ; no                      ; yes                    ; no                      ; 1024  ; 32                          ; 32                          ; 32                          ; 32                          ; 1024                ; 1    ; None                                 ; M9K_X33_Y17_N0                                                                                                                                                                                 ; Don't care           ; New data with NBE Read ; New data with NBE Read ; No - Unknown  ;
++-------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+------------------------+------------------------+---------------+
+Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
+
+
+RAM content values are presented in the following format: (Binary) (Octal) (Decimal) (Hexadecimal) 
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; |xoro_top|Memory:mem|altsyncram:memory_1_symbol3_rtl_0|altsyncram_edi1:auto_generated|ALTSYNCRAM                                                                                                                                                                 ;
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+;   Addr   ;              +0              ;              +1              ;              +2              ;              +3              ;              +4              ;              +5              ;              +6              ;              +7              ;
++----------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+
+;0;(01001000) (110) (72) (48)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00100000) (40) (32) (20)   ;(00100000) (40) (32) (20)   ;(00100000) (40) (32) (20)   ;(00100000) (40) (32) (20)   ;
+;8;(00100000) (40) (32) (20)    ;(00100000) (40) (32) (20)   ;(00100000) (40) (32) (20)   ;(00100000) (40) (32) (20)   ;(00100010) (42) (34) (22)   ;(00100010) (42) (34) (22)   ;(00100010) (42) (34) (22)   ;(00100010) (42) (34) (22)   ;
+;16;(00100010) (42) (34) (22)    ;(00100010) (42) (34) (22)   ;(00100010) (42) (34) (22)   ;(00100010) (42) (34) (22)   ;(00100101) (45) (37) (25)   ;(00100101) (45) (37) (25)   ;(00100101) (45) (37) (25)   ;(00100101) (45) (37) (25)   ;
+;24;(00100101) (45) (37) (25)    ;(00100101) (45) (37) (25)   ;(00100101) (45) (37) (25)   ;(00100101) (45) (37) (25)   ;(00100111) (47) (39) (27)   ;(00100111) (47) (39) (27)   ;(00100111) (47) (39) (27)   ;(00100111) (47) (39) (27)   ;
+;32;(00100111) (47) (39) (27)    ;(00100111) (47) (39) (27)   ;(00100111) (47) (39) (27)   ;(00100111) (47) (39) (27)   ;(01001000) (110) (72) (48)   ;(00100000) (40) (32) (20)   ;(00000000) (0) (0) (00)   ;(01100011) (143) (99) (63)   ;
+;40;(00100000) (40) (32) (20)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00100000) (40) (32) (20)   ;(00100000) (40) (32) (20)   ;(00100000) (40) (32) (20)   ;(00100001) (41) (33) (21)   ;(00100001) (41) (33) (21)   ;
+;48;(00100001) (41) (33) (21)    ;(00100001) (41) (33) (21)   ;(00100010) (42) (34) (22)   ;(00100010) (42) (34) (22)   ;(00100010) (42) (34) (22)   ;(00100010) (42) (34) (22)   ;(00100011) (43) (35) (23)   ;(00100011) (43) (35) (23)   ;
+;56;(00100011) (43) (35) (23)    ;(00100011) (43) (35) (23)   ;(00100100) (44) (36) (24)   ;(00100100) (44) (36) (24)   ;(00100100) (44) (36) (24)   ;(00100100) (44) (36) (24)   ;(00100101) (45) (37) (25)   ;(00100101) (45) (37) (25)   ;
+;64;(00100101) (45) (37) (25)    ;(00100101) (45) (37) (25)   ;(00100110) (46) (38) (26)   ;(00100110) (46) (38) (26)   ;(00100110) (46) (38) (26)   ;(00100110) (46) (38) (26)   ;(00100111) (47) (39) (27)   ;(00100111) (47) (39) (27)   ;
+;72;(00100111) (47) (39) (27)    ;(00100111) (47) (39) (27)   ;(00000100) (4) (4) (04)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;80;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;88;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;96;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;104;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;112;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;120;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;128;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;136;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;144;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;152;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;160;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;168;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;176;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;184;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;192;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;200;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;208;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;216;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;224;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;232;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;240;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
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+;9848;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;9856;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;9864;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;9872;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;9880;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;9888;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;9896;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;9904;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
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+;9928;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
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+;9960;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;9968;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;9976;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;9984;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;9992;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10000;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10008;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10016;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10024;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10032;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10040;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10048;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10056;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10064;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10072;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10080;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10088;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10096;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10104;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10112;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10120;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10128;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10136;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10144;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10152;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10160;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10168;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10176;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10184;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10192;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10200;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10208;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10216;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10224;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10232;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10240;(00000000) (0) (0) (00)    ;
+
+
+RAM content values are presented in the following format: (Binary) (Octal) (Decimal) (Hexadecimal) 
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; |xoro_top|Memory:mem|altsyncram:memory_1_symbol1_rtl_0|altsyncram_cdi1:auto_generated|ALTSYNCRAM                                                                                                                                                                 ;
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+;   Addr   ;              +0              ;              +1              ;              +2              ;              +3              ;              +4              ;              +5              ;              +6              ;              +7              ;
++----------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+
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+;9856;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
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+;9888;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;9896;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
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+;9920;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;9928;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
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+;9960;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;9968;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;9976;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;9984;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;9992;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10000;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10008;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10016;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10024;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10032;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10040;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10048;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10056;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10064;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10072;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10080;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10088;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10096;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10104;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10112;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10120;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10128;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10136;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10144;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10152;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10160;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10168;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10176;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10184;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10192;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10200;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10208;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10216;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10224;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10232;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10240;(00000000) (0) (0) (00)    ;
+
+
+RAM content values are presented in the following format: (Binary) (Octal) (Decimal) (Hexadecimal) 
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; |xoro_top|Memory:mem|altsyncram:memory_1_symbol0_rtl_0|altsyncram_bdi1:auto_generated|ALTSYNCRAM                                                                                                                                                                 ;
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+;   Addr   ;              +0              ;              +1              ;              +2              ;              +3              ;              +4              ;              +5              ;              +6              ;              +7              ;
++----------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+
+;0;(01101111) (157) (111) (6F)    ;(00010011) (23) (19) (13)   ;(00010011) (23) (19) (13)   ;(00010011) (23) (19) (13)   ;(00100011) (43) (35) (23)   ;(00100011) (43) (35) (23)   ;(00100011) (43) (35) (23)   ;(00100011) (43) (35) (23)   ;
+;8;(00100011) (43) (35) (23)    ;(00100011) (43) (35) (23)   ;(00100011) (43) (35) (23)   ;(00100011) (43) (35) (23)   ;(00100011) (43) (35) (23)   ;(00100011) (43) (35) (23)   ;(00100011) (43) (35) (23)   ;(00100011) (43) (35) (23)   ;
+;16;(00100011) (43) (35) (23)    ;(00100011) (43) (35) (23)   ;(00100011) (43) (35) (23)   ;(00100011) (43) (35) (23)   ;(00100011) (43) (35) (23)   ;(00100011) (43) (35) (23)   ;(00100011) (43) (35) (23)   ;(00100011) (43) (35) (23)   ;
+;24;(00100011) (43) (35) (23)    ;(00100011) (43) (35) (23)   ;(00100011) (43) (35) (23)   ;(00100011) (43) (35) (23)   ;(00100011) (43) (35) (23)   ;(00100011) (43) (35) (23)   ;(00100011) (43) (35) (23)   ;(00100011) (43) (35) (23)   ;
+;32;(00100011) (43) (35) (23)    ;(00100011) (43) (35) (23)   ;(00100011) (43) (35) (23)   ;(00100011) (43) (35) (23)   ;(00010011) (23) (19) (13)   ;(00010011) (23) (19) (13)   ;(10010011) (223) (147) (93)   ;(11101111) (357) (239) (EF)   ;
+;40;(10010011) (223) (147) (93)    ;(01100011) (143) (99) (63)   ;(01110011) (163) (115) (73)   ;(10000011) (203) (131) (83)   ;(10000011) (203) (131) (83)   ;(00000011) (3) (3) (03)   ;(00000011) (3) (3) (03)   ;(10000011) (203) (131) (83)   ;
+;48;(00000011) (3) (3) (03)    ;(10000011) (203) (131) (83)   ;(00000011) (3) (3) (03)   ;(10000011) (203) (131) (83)   ;(00000011) (3) (3) (03)   ;(10000011) (203) (131) (83)   ;(00000011) (3) (3) (03)   ;(10000011) (203) (131) (83)   ;
+;56;(00000011) (3) (3) (03)    ;(10000011) (203) (131) (83)   ;(00000011) (3) (3) (03)   ;(10000011) (203) (131) (83)   ;(00000011) (3) (3) (03)   ;(10000011) (203) (131) (83)   ;(00000011) (3) (3) (03)   ;(10000011) (203) (131) (83)   ;
+;64;(00000011) (3) (3) (03)    ;(10000011) (203) (131) (83)   ;(00000011) (3) (3) (03)   ;(10000011) (203) (131) (83)   ;(00000011) (3) (3) (03)   ;(10000011) (203) (131) (83)   ;(00000011) (3) (3) (03)   ;(10000011) (203) (131) (83)   ;
+;72;(00000011) (3) (3) (03)    ;(10000011) (203) (131) (83)   ;(00001011) (13) (11) (0B)   ;(00010011) (23) (19) (13)   ;(00010011) (23) (19) (13)   ;(00010011) (23) (19) (13)   ;(00010011) (23) (19) (13)   ;(00010011) (23) (19) (13)   ;
+;80;(00010011) (23) (19) (13)    ;(00010011) (23) (19) (13)   ;(00010011) (23) (19) (13)   ;(00010011) (23) (19) (13)   ;(00010011) (23) (19) (13)   ;(00010011) (23) (19) (13)   ;(00010011) (23) (19) (13)   ;(00010011) (23) (19) (13)   ;
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+;10000;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10008;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10016;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10024;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10032;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10040;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10048;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10056;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10064;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10072;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10080;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10088;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10096;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10104;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10112;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10120;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10128;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10136;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10144;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10152;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10160;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10168;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10176;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10184;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10192;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10200;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10208;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10216;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10224;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10232;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10240;(00000000) (0) (0) (00)    ;
+
+
+RAM content values are presented in the following format: (Binary) (Octal) (Decimal) (Hexadecimal) 
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; |xoro_top|Memory:mem|altsyncram:memory_1_symbol2_rtl_0|altsyncram_ddi1:auto_generated|ALTSYNCRAM                                                                                                                                                                 ;
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+;   Addr   ;              +0              ;              +1              ;              +2              ;              +3              ;              +4              ;              +5              ;              +6              ;              +7              ;
++----------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+
+;0;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00110000) (60) (48) (30)   ;(00010000) (20) (16) (10)   ;(00100000) (40) (32) (20)   ;(00110000) (60) (48) (30)   ;
+;8;(01000000) (100) (64) (40)    ;(01010000) (120) (80) (50)   ;(01100000) (140) (96) (60)   ;(01110000) (160) (112) (70)   ;(10000000) (200) (128) (80)   ;(10010000) (220) (144) (90)   ;(10100000) (240) (160) (A0)   ;(10110000) (260) (176) (B0)   ;
+;16;(11000000) (300) (192) (C0)    ;(11010000) (320) (208) (D0)   ;(11100000) (340) (224) (E0)   ;(11110000) (360) (240) (F0)   ;(00000000) (0) (0) (00)   ;(00010000) (20) (16) (10)   ;(00100000) (40) (32) (20)   ;(00110000) (60) (48) (30)   ;
+;24;(01000000) (100) (64) (40)    ;(01010000) (120) (80) (50)   ;(01100000) (140) (96) (60)   ;(01110000) (160) (112) (70)   ;(10000000) (200) (128) (80)   ;(10010000) (220) (144) (90)   ;(10100000) (240) (160) (A0)   ;(10110000) (260) (176) (B0)   ;
+;32;(11000000) (300) (192) (C0)    ;(11010000) (320) (208) (D0)   ;(11100000) (340) (224) (E0)   ;(11110000) (360) (240) (F0)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000010) (2) (2) (02)   ;(01000000) (100) (64) (40)   ;
+;40;(00000000) (0) (0) (00)    ;(10110101) (265) (181) (B5)   ;(00010000) (20) (16) (10)   ;(00000000) (0) (0) (00)   ;(01000000) (100) (64) (40)   ;(10000000) (200) (128) (80)   ;(00000000) (0) (0) (00)   ;(01000000) (100) (64) (40)   ;
+;48;(10000000) (200) (128) (80)    ;(11000000) (300) (192) (C0)   ;(00000000) (0) (0) (00)   ;(01000000) (100) (64) (40)   ;(10000000) (200) (128) (80)   ;(11000000) (300) (192) (C0)   ;(00000000) (0) (0) (00)   ;(01000000) (100) (64) (40)   ;
+;56;(10000000) (200) (128) (80)    ;(11000000) (300) (192) (C0)   ;(00000000) (0) (0) (00)   ;(01000000) (100) (64) (40)   ;(10000000) (200) (128) (80)   ;(11000000) (300) (192) (C0)   ;(00000000) (0) (0) (00)   ;(01000000) (100) (64) (40)   ;
+;64;(10000000) (200) (128) (80)    ;(11000000) (300) (192) (C0)   ;(00000000) (0) (0) (00)   ;(01000000) (100) (64) (40)   ;(10000000) (200) (128) (80)   ;(11000000) (300) (192) (C0)   ;(00000000) (0) (0) (00)   ;(01000000) (100) (64) (40)   ;
+;72;(10000000) (200) (128) (80)    ;(11000000) (300) (192) (C0)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;80;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;88;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;96;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;104;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;112;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;120;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;128;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;136;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;144;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;152;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;160;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
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+;10104;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10112;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10120;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10128;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10136;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10144;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10152;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10160;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10168;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10176;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10184;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10192;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10200;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10208;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10216;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10224;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10232;(00000000) (0) (0) (00)    ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;(00000000) (0) (0) (00)   ;
+;10240;(00000000) (0) (0) (00)    ;
+
+
++-----------------------------------------------------------------------------------------------+
+; Fitter DSP Block Usage Summary                                                                ;
++---------------------------------------+-------------+---------------------+-------------------+
+; Statistic                             ; Number Used ; Available per Block ; Maximum Available ;
++---------------------------------------+-------------+---------------------+-------------------+
+; Simple Multipliers (9-bit)            ; 0           ; 2                   ; 132               ;
+; Simple Multipliers (18-bit)           ; 4           ; 1                   ; 66                ;
+; Embedded Multiplier Blocks            ; 4           ; --                  ; 66                ;
+; Embedded Multiplier 9-bit elements    ; 8           ; 2                   ; 132               ;
+; Signed Embedded Multipliers           ; 1           ; --                  ; --                ;
+; Unsigned Embedded Multipliers         ; 1           ; --                  ; --                ;
+; Mixed Sign Embedded Multipliers       ; 2           ; --                  ; --                ;
+; Variable Sign Embedded Multipliers    ; 0           ; --                  ; --                ;
+; Dedicated Input Shift Register Chains ; 0           ; --                  ; --                ;
++---------------------------------------+-------------+---------------------+-------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; DSP Block Details                                                                                                                                                                                                                                                                               ;
++--------------------------------------------------------------------------------------------------+----------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+
+; Name                                                                                             ; Mode                       ; Location           ; Sign Representation ; Has Input Shift Register Chain ; Data A Input Register ; Data B Input Register ; Pipeline Register ; Output Register ;
++--------------------------------------------------------------------------------------------------+----------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_out6     ; Simple Multiplier (18-bit) ; DSPOUT_X42_Y13_N2  ;                     ; No                             ;                       ;                       ;                   ; no              ;
+;    picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult5 ;                            ; DSPMULT_X42_Y13_N0 ; Mixed               ;                                ; yes                   ; yes                   ; no                ;                 ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_out8     ; Simple Multiplier (18-bit) ; DSPOUT_X42_Y11_N2  ;                     ; No                             ;                       ;                       ;                   ; no              ;
+;    picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult7 ;                            ; DSPMULT_X42_Y11_N0 ; Signed              ;                                ; yes                   ; yes                   ; no                ;                 ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_out4     ; Simple Multiplier (18-bit) ; DSPOUT_X42_Y12_N2  ;                     ; No                             ;                       ;                       ;                   ; no              ;
+;    picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult3 ;                            ; DSPMULT_X42_Y12_N0 ; Mixed               ;                                ; yes                   ; yes                   ; no                ;                 ;
+; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|w589w[0]     ; Simple Multiplier (18-bit) ; DSPOUT_X42_Y16_N2  ;                     ; No                             ;                       ;                       ;                   ; no              ;
+;    picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated|mac_mult1 ;                            ; DSPMULT_X42_Y16_N0 ; Unsigned            ;                                ; yes                   ; yes                   ; no                ;                 ;
++--------------------------------------------------------------------------------------------------+----------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+
+
+
++------------------------------------------------+
+; Routing Usage Summary                          ;
++-----------------------+------------------------+
+; Routing Resource Type ; Usage                  ;
++-----------------------+------------------------+
+; Block interconnects   ; 6,023 / 71,559 ( 8 % ) ;
+; C16 interconnects     ; 66 / 2,597 ( 3 % )     ;
+; C4 interconnects      ; 3,239 / 46,848 ( 7 % ) ;
+; Direct links          ; 549 / 71,559 ( < 1 % ) ;
+; Global clocks         ; 5 / 20 ( 25 % )        ;
+; Local interconnects   ; 1,406 / 24,624 ( 6 % ) ;
+; R24 interconnects     ; 112 / 2,496 ( 4 % )    ;
+; R4 interconnects      ; 3,888 / 62,424 ( 6 % ) ;
++-----------------------+------------------------+
+
+
++-----------------------------------------------------------------------------+
+; LAB Logic Elements                                                          ;
++---------------------------------------------+-------------------------------+
+; Number of Logic Elements  (Average = 13.76) ; Number of LABs  (Total = 216) ;
++---------------------------------------------+-------------------------------+
+; 1                                           ; 8                             ;
+; 2                                           ; 4                             ;
+; 3                                           ; 4                             ;
+; 4                                           ; 3                             ;
+; 5                                           ; 2                             ;
+; 6                                           ; 0                             ;
+; 7                                           ; 2                             ;
+; 8                                           ; 0                             ;
+; 9                                           ; 3                             ;
+; 10                                          ; 3                             ;
+; 11                                          ; 5                             ;
+; 12                                          ; 5                             ;
+; 13                                          ; 14                            ;
+; 14                                          ; 13                            ;
+; 15                                          ; 27                            ;
+; 16                                          ; 123                           ;
++---------------------------------------------+-------------------------------+
+
+
++--------------------------------------------------------------------+
+; LAB-wide Signals                                                   ;
++------------------------------------+-------------------------------+
+; LAB-wide Signals  (Average = 1.43) ; Number of LABs  (Total = 216) ;
++------------------------------------+-------------------------------+
+; 1 Async. clear                     ; 25                            ;
+; 1 Clock                            ; 167                           ;
+; 1 Clock enable                     ; 71                            ;
+; 1 Sync. clear                      ; 18                            ;
+; 1 Sync. load                       ; 19                            ;
+; 2 Clock enables                    ; 9                             ;
++------------------------------------+-------------------------------+
+
+
++------------------------------------------------------------------------------+
+; LAB Signals Sourced                                                          ;
++----------------------------------------------+-------------------------------+
+; Number of Signals Sourced  (Average = 19.40) ; Number of LABs  (Total = 216) ;
++----------------------------------------------+-------------------------------+
+; 0                                            ; 3                             ;
+; 1                                            ; 5                             ;
+; 2                                            ; 8                             ;
+; 3                                            ; 1                             ;
+; 4                                            ; 3                             ;
+; 5                                            ; 2                             ;
+; 6                                            ; 2                             ;
+; 7                                            ; 1                             ;
+; 8                                            ; 1                             ;
+; 9                                            ; 0                             ;
+; 10                                           ; 2                             ;
+; 11                                           ; 1                             ;
+; 12                                           ; 2                             ;
+; 13                                           ; 4                             ;
+; 14                                           ; 4                             ;
+; 15                                           ; 13                            ;
+; 16                                           ; 26                            ;
+; 17                                           ; 11                            ;
+; 18                                           ; 11                            ;
+; 19                                           ; 10                            ;
+; 20                                           ; 6                             ;
+; 21                                           ; 7                             ;
+; 22                                           ; 8                             ;
+; 23                                           ; 14                            ;
+; 24                                           ; 11                            ;
+; 25                                           ; 6                             ;
+; 26                                           ; 7                             ;
+; 27                                           ; 7                             ;
+; 28                                           ; 8                             ;
+; 29                                           ; 4                             ;
+; 30                                           ; 4                             ;
+; 31                                           ; 9                             ;
+; 32                                           ; 15                            ;
++----------------------------------------------+-------------------------------+
+
+
++---------------------------------------------------------------------------------+
+; LAB Signals Sourced Out                                                         ;
++-------------------------------------------------+-------------------------------+
+; Number of Signals Sourced Out  (Average = 9.10) ; Number of LABs  (Total = 216) ;
++-------------------------------------------------+-------------------------------+
+; 0                                               ; 3                             ;
+; 1                                               ; 14                            ;
+; 2                                               ; 10                            ;
+; 3                                               ; 7                             ;
+; 4                                               ; 13                            ;
+; 5                                               ; 11                            ;
+; 6                                               ; 11                            ;
+; 7                                               ; 13                            ;
+; 8                                               ; 13                            ;
+; 9                                               ; 24                            ;
+; 10                                              ; 7                             ;
+; 11                                              ; 13                            ;
+; 12                                              ; 16                            ;
+; 13                                              ; 10                            ;
+; 14                                              ; 10                            ;
+; 15                                              ; 13                            ;
+; 16                                              ; 25                            ;
+; 17                                              ; 0                             ;
+; 18                                              ; 1                             ;
+; 19                                              ; 2                             ;
++-------------------------------------------------+-------------------------------+
+
+
++------------------------------------------------------------------------------+
+; LAB Distinct Inputs                                                          ;
++----------------------------------------------+-------------------------------+
+; Number of Distinct Inputs  (Average = 19.72) ; Number of LABs  (Total = 216) ;
++----------------------------------------------+-------------------------------+
+; 0                                            ; 0                             ;
+; 1                                            ; 1                             ;
+; 2                                            ; 3                             ;
+; 3                                            ; 5                             ;
+; 4                                            ; 4                             ;
+; 5                                            ; 3                             ;
+; 6                                            ; 7                             ;
+; 7                                            ; 2                             ;
+; 8                                            ; 3                             ;
+; 9                                            ; 5                             ;
+; 10                                           ; 8                             ;
+; 11                                           ; 7                             ;
+; 12                                           ; 6                             ;
+; 13                                           ; 8                             ;
+; 14                                           ; 6                             ;
+; 15                                           ; 4                             ;
+; 16                                           ; 6                             ;
+; 17                                           ; 9                             ;
+; 18                                           ; 11                            ;
+; 19                                           ; 5                             ;
+; 20                                           ; 7                             ;
+; 21                                           ; 14                            ;
+; 22                                           ; 5                             ;
+; 23                                           ; 13                            ;
+; 24                                           ; 7                             ;
+; 25                                           ; 10                            ;
+; 26                                           ; 4                             ;
+; 27                                           ; 1                             ;
+; 28                                           ; 1                             ;
+; 29                                           ; 8                             ;
+; 30                                           ; 4                             ;
+; 31                                           ; 4                             ;
+; 32                                           ; 9                             ;
+; 33                                           ; 12                            ;
+; 34                                           ; 8                             ;
+; 35                                           ; 5                             ;
+; 36                                           ; 1                             ;
++----------------------------------------------+-------------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 30    ;
+; Number of I/O Rules Passed       ; 11    ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 19    ;
++----------------------------------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                                    ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O  ;                   ;
+; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O  ;                   ;
+; Pass         ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O  ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
+; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; No open drain assignments found.                                         ; I/O  ;                   ;
+; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength or Termination assignments found.                    ; I/O  ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O  ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O  ;                   ;
+; Pass         ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; 0 such failures found.                                                   ; I/O  ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Pin/Rules          ; IO_000001    ; IO_000002    ; IO_000003    ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007    ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Total Pass         ; 41           ; 0            ; 41           ; 0            ; 1            ; 46        ; 41           ; 0            ; 46        ; 46        ; 0            ; 0            ; 0            ; 0            ; 2            ; 0            ; 0            ; 2            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 46        ; 0            ; 44           ;
+; Total Unchecked    ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Total Inapplicable ; 5            ; 46           ; 5            ; 46           ; 45           ; 0         ; 5            ; 46           ; 0         ; 0         ; 46           ; 46           ; 46           ; 46           ; 44           ; 46           ; 46           ; 44           ; 46           ; 46           ; 46           ; 46           ; 46           ; 46           ; 46           ; 46           ; 46           ; 0         ; 46           ; 2            ;
+; Total Fail         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; reset_btn          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LED[0]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; LED[1]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; LED[2]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; LED[3]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; LED[4]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; LED[5]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; LED[6]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; LED[7]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; UART_TX            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[0]        ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[1]        ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[2]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[3]        ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[4]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[5]        ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[6]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[7]        ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[8]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[9]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[10]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[11]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[12]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[13]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[14]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[15]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[16]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[17]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[18]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[19]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[20]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[21]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[22]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[23]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[24]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[25]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[26]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[27]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[28]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[29]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[30]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[31]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[32]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; GPIO_1_D[33]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
+; UART_RX            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; CLOCK_50           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Pass         ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass         ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+
+
++---------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                       ;
++------------------------------------------------------------------+--------------------------+
+; Option                                                           ; Setting                  ;
++------------------------------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                      ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                      ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                      ;
+; Enable INIT_DONE output                                          ; Off                      ;
+; Configuration scheme                                             ; Active Serial            ;
+; Error detection CRC                                              ; Off                      ;
+; Enable open drain on CRC_ERROR pin                               ; Off                      ;
+; Enable input tri-state on active configuration pins in user mode ; Off                      ;
+; Configuration Voltage Level                                      ; Auto                     ;
+; Force Configuration Voltage Level                                ; Off                      ;
+; nCEO                                                             ; As output driving ground ;
+; Data[0]                                                          ; As input tri-stated      ;
+; Data[1]/ASDO                                                     ; As input tri-stated      ;
+; Data[7..2]                                                       ; Unreserved               ;
+; FLASH_nCE/nCSO                                                   ; As input tri-stated      ;
+; Other Active Parallel pins                                       ; Unreserved               ;
+; DCLK                                                             ; As output driving ground ;
++------------------------------------------------------------------+--------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.20 V ;
+; Low Junction Temperature  ; 0 °C   ;
+; High Junction Temperature ; 85 °C  ;
++---------------------------+--------+
+
+
++------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Summary              ;
++-----------------+----------------------+-------------------+
+; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
++-----------------+----------------------+-------------------+
+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
+This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
+
+
++----------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Details                        ;
++---------------------------+----------------------+-------------------+
+; Source Register           ; Destination Register ; Delay Added in ns ;
++---------------------------+----------------------+-------------------+
+; picorv32:cpu|mem_wdata[4] ; gpio:gpio|gpio[4]    ; 0.011             ;
+; picorv32:cpu|mem_wdata[7] ; gpio:gpio|gpio[7]    ; 0.011             ;
+; picorv32:cpu|mem_wdata[5] ; gpio:gpio|gpio[5]    ; 0.011             ;
+; picorv32:cpu|mem_wdata[2] ; gpio:gpio|gpio[2]    ; 0.011             ;
++---------------------------+----------------------+-------------------+
+Note: This table only shows the top 4 path(s) that have the largest delay added for hold.
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Info (20032): Parallel compilation is enabled and will use up to 2 processors
+Info (119006): Selected device EP4CE22F17C6 for design "xoro"
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (15535): Implemented PLL "pll_sys:pll_sys_inst|altpll:altpll_component|pll_sys_altpll:auto_generated|pll1" as Cyclone IV E PLL type
+    Info (15099): Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for pll_sys:pll_sys_inst|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] port
+    Info (15099): Implementing clock multiplication of 9, clock division of 61, and phase shift of 0 degrees (0 ps) for pll_sys:pll_sys_inst|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[1] port
+    Info (15099): Implementing clock multiplication of 9, clock division of 244, and phase shift of 0 degrees (0 ps) for pll_sys:pll_sys_inst|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[2] port
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
+Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+    Info (176445): Device EP4CE10F17C6 is compatible
+    Info (176445): Device EP4CE6F17C6 is compatible
+    Info (176445): Device EP4CE15F17C6 is compatible
+Info (169124): Fitter converted 5 user pins into dedicated programming pins
+    Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1
+    Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2
+    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location H1
+    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location H2
+    Info (169125): Pin ~ALTERA_nCEO~ is reserved at location F16
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
+Critical Warning (169085): No exact pin location assignment(s) for 5 pins of 46 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
+Info (332104): Reading SDC File: 'de0_nano_system.sdc'
+Warning (332174): Ignored filter at de0_nano_system.sdc(41): altera_reserved_tck could not be matched with a port or pin or register or keeper or net or combinational node or node
+Warning (332049): Ignored create_clock at de0_nano_system.sdc(41): Argument <targets> is not an object ID
+    Info (332050): create_clock -period 10MHz -name {altera_reserved_tck} {altera_reserved_tck}
+Info (332110): Deriving PLL clocks
+    Info (332110): create_generated_clock -source {pll_sys_inst|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {pll_sys_inst|altpll_component|auto_generated|pll1|clk[0]} {pll_sys_inst|altpll_component|auto_generated|pll1|clk[0]}
+    Info (332110): create_generated_clock -source {pll_sys_inst|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 61 -multiply_by 9 -duty_cycle 50.00 -name {pll_sys_inst|altpll_component|auto_generated|pll1|clk[1]} {pll_sys_inst|altpll_component|auto_generated|pll1|clk[1]}
+    Info (332110): create_generated_clock -source {pll_sys_inst|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 244 -multiply_by 9 -duty_cycle 50.00 -name {pll_sys_inst|altpll_component|auto_generated|pll1|clk[2]} {pll_sys_inst|altpll_component|auto_generated|pll1|clk[2]}
+Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
+Warning (332174): Ignored filter at de0_nano_system.sdc(72): altera_reserved_tck could not be matched with a clock
+Warning (332049): Ignored set_false_path at de0_nano_system.sdc(72): Argument <from> is an empty collection
+    Info (332050): set_false_path -from [get_clocks {altera_reserved_tck}] -to [get_clocks {altera_reserved_tck}]
+Warning (332049): Ignored set_false_path at de0_nano_system.sdc(72): Argument <to> is an empty collection
+Warning (332060): Node: prng:prng|prng_clk was determined to be a clock but was found without an associated clock assignment.
+    Info (13166): Register prng:prng|xoroshiro128plus:prng|ss[15] is being clocked by prng:prng|prng_clk
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
+Info (332111): Found 4 clocks
+    Info (332111):   Period   Clock Name
+    Info (332111): ======== ============
+    Info (332111):   20.000     CLOCK_50
+    Info (332111):   10.000 pll_sys_inst|altpll_component|auto_generated|pll1|clk[0]
+    Info (332111):  135.555 pll_sys_inst|altpll_component|auto_generated|pll1|clk[1]
+    Info (332111):  542.222 pll_sys_inst|altpll_component|auto_generated|pll1|clk[2]
+Info (176353): Automatically promoted node pll_sys:pll_sys_inst|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] (placed in counter C0 of PLL_4)
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18
+Info (176353): Automatically promoted node pll_sys:pll_sys_inst|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[1] (placed in counter C2 of PLL_4)
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17
+Info (176353): Automatically promoted node pll_sys:pll_sys_inst|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[2] (placed in counter C1 of PLL_4)
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19
+Info (176353): Automatically promoted node prng:prng|prng_clk 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+Info (176353): Automatically promoted node resetn 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node timer:timer|rdy
+        Info (176357): Destination node picorv32:cpu|picorv32_pcpi_div:pcpi_div|pcpi_wr
+        Info (176357): Destination node picorv32:cpu|instr_beq
+        Info (176357): Destination node picorv32:cpu|instr_bne
+        Info (176357): Destination node picorv32:cpu|instr_blt
+        Info (176357): Destination node picorv32:cpu|instr_bge
+        Info (176357): Destination node picorv32:cpu|instr_bltu
+        Info (176357): Destination node picorv32:cpu|instr_bgeu
+        Info (176357): Destination node picorv32:cpu|instr_addi
+        Info (176357): Destination node picorv32:cpu|instr_slti
+        Info (176358): Non-global destination nodes limited to 10 nodes
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+    Extra Info (176218): Packed 132 registers into blocks of type Embedded multiplier block
+    Extra Info (176220): Created 66 register duplicates
+Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
+    Info (176211): Number of I/O pins in group: 5 (unused VREF, 3.3V VCCIO, 0 input, 5 output, 0 bidirectional)
+        Info (176212): I/O standards used: 3.3-V LVTTL.
+Info (176215): I/O bank details before I/O pin placement
+    Info (176214): Statistics of I/O banks
+        Info (176213): I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 7 total pin(s) used --  7 pins available
+        Info (176213): I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 1 total pin(s) used --  15 pins available
+        Info (176213): I/O bank number 3 uses 0.6V VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  24 pins available
+        Info (176213): I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 14 total pin(s) used --  6 pins available
+        Info (176213): I/O bank number 5 does not use VREF pins and has 3.3V VCCIO pins. 16 total pin(s) used --  2 pins available
+        Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  12 pins available
+        Info (176213): I/O bank number 7 does not use VREF pins and has 3.3V VCCIO pins. 4 total pin(s) used --  20 pins available
+        Info (176213): I/O bank number 8 does not use VREF pins and has 3.3V VCCIO pins. 2 total pin(s) used --  22 pins available
+Warning (15705): Ignored locations or region assignments to the following nodes
+    Warning (15706): Node "ADC_CS_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "ADC_SADDR" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "ADC_SCLK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "ADC_SDAT" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_BA[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_BA[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_CKE" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_CLK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_CS_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQM[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQM[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_WE_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "EPCS_ASDO" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "EPCS_DATA0" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "EPCS_DCLK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "EPCS_NCSO" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_D[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_D[10]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_D[11]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_D[12]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_D[13]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_D[14]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_D[15]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_D[16]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_D[17]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_D[18]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_D[19]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_D[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_D[20]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_D[21]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_D[22]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_D[23]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_D[24]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_D[25]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_D[26]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_D[27]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_D[28]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_D[29]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_D[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_D[30]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_D[31]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_D[32]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_D[33]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_D[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_D[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_D[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_D[9]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_IN[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_IN[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1_IN[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1_IN[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_2[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_2[10]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_2[11]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_2[12]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_2[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_2[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_2[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_2[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_2[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_2[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_2[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_2[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_2[9]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_2_IN[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_2_IN[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_2_IN[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "G_SENSOR_CS_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "G_SENSOR_INT" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "I2C_SCLK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "I2C_SDAT" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "RND_OUT[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "RND_OUT[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "RND_OUT[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "RND_OUT[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:02
+Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
+Info (170189): Fitter placement preparation operations beginning
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:05
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 6% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 31% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:03
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+Info (11888): Total time spent on timing analysis during the Fitter is 2.19 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02
+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
+Warning (169177): 2 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
+    Info (169178): Pin reset_btn uses I/O standard 3.3-V LVTTL at J15
+    Info (169178): Pin UART_RX uses I/O standard 2.5 V at B4
+Info (144001): Generated suppressed messages file E:/Photonic/RISCV/output_files/xoro.fit.smsg
+Info: Quartus II 64-Bit Fitter was successful. 0 errors, 123 warnings
+    Info: Peak virtual memory: 5429 megabytes
+    Info: Processing ended: Sat Sep 16 21:12:45 2023
+    Info: Elapsed time: 00:00:16
+    Info: Total CPU time (on all processors): 00:00:10
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in E:/Photonic/RISCV/output_files/xoro.fit.smsg.
+
+
diff --git a/rtl/DE0-NANO/output_files/xoro.fit.smsg b/rtl/DE0-NANO/output_files/xoro.fit.smsg
new file mode 100644
index 0000000..ed080d6
--- /dev/null
+++ b/rtl/DE0-NANO/output_files/xoro.fit.smsg
@@ -0,0 +1,6 @@
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/rtl/DE0-NANO/output_files/xoro.fit.summary b/rtl/DE0-NANO/output_files/xoro.fit.summary
new file mode 100644
index 0000000..17ef2e4
--- /dev/null
+++ b/rtl/DE0-NANO/output_files/xoro.fit.summary
@@ -0,0 +1,16 @@
+Fitter Status : Successful - Sat Sep 16 21:12:44 2023
+Quartus II 64-Bit Version : 15.0.0 Build 145 04/22/2015 SJ Web Edition
+Revision Name : xoro
+Top-level Entity Name : xoro_top
+Family : Cyclone IV E
+Device : EP4CE22F17C6
+Timing Models : Final
+Total logic elements : 2,973 / 22,320 ( 13 % )
+    Total combinational functions : 2,743 / 22,320 ( 12 % )
+    Dedicated logic registers : 1,354 / 22,320 ( 6 % )
+Total registers : 1354
+Total pins : 46 / 154 ( 30 % )
+Total virtual pins : 0
+Total memory bits : 330,016 / 608,256 ( 54 % )
+Embedded Multiplier 9-bit elements : 8 / 132 ( 6 % )
+Total PLLs : 1 / 4 ( 25 % )
diff --git a/rtl/DE0-NANO/output_files/xoro.flow.rpt b/rtl/DE0-NANO/output_files/xoro.flow.rpt
new file mode 100644
index 0000000..ec16c24
--- /dev/null
+++ b/rtl/DE0-NANO/output_files/xoro.flow.rpt
@@ -0,0 +1,129 @@
+Flow report for xoro
+Sat Sep 16 21:12:47 2023
+Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus II License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; Flow Summary                                                                    ;
++------------------------------------+--------------------------------------------+
+; Flow Status                        ; Successful - Sat Sep 16 21:12:47 2023      ;
+; Quartus II 64-Bit Version          ; 15.0.0 Build 145 04/22/2015 SJ Web Edition ;
+; Revision Name                      ; xoro                                       ;
+; Top-level Entity Name              ; xoro_top                                   ;
+; Family                             ; Cyclone IV E                               ;
+; Device                             ; EP4CE22F17C6                               ;
+; Timing Models                      ; Final                                      ;
+; Total logic elements               ; 2,973 / 22,320 ( 13 % )                    ;
+;     Total combinational functions  ; 2,743 / 22,320 ( 12 % )                    ;
+;     Dedicated logic registers      ; 1,354 / 22,320 ( 6 % )                     ;
+; Total registers                    ; 1354                                       ;
+; Total pins                         ; 46 / 154 ( 30 % )                          ;
+; Total virtual pins                 ; 0                                          ;
+; Total memory bits                  ; 330,016 / 608,256 ( 54 % )                 ;
+; Embedded Multiplier 9-bit elements ; 8 / 132 ( 6 % )                            ;
+; Total PLLs                         ; 1 / 4 ( 25 % )                             ;
++------------------------------------+--------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 09/16/2023 21:12:15 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; xoro                ;
++-------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                       ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; Assignment Name                     ; Value                                 ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID               ; 101728417602065.169492393530232       ; --            ; --          ; --         ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                                    ; --            ; --          ; --         ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                                     ; --            ; --          ; --         ;
+; MISC_FILE                           ; qram32_inst.v                         ; --            ; --          ; --         ;
+; MISC_FILE                           ; qram32_bb.v                           ; --            ; --          ; --         ;
+; NOMINAL_CORE_SUPPLY_VOLTAGE         ; 1.2V                                  ; --            ; --          ; --         ;
+; NUM_PARALLEL_PROCESSORS             ; 2                                     ; --            ; --          ; --         ;
+; PARTITION_COLOR                     ; 16764057                              ; --            ; xoro_top    ; Top        ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING                 ; --            ; xoro_top    ; Top        ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                                ; --            ; xoro_top    ; Top        ;
+; POWER_BOARD_THERMAL_MODEL           ; None (CONSERVATIVE)                   ; --            ; --          ; --         ;
+; POWER_PRESET_COOLING_SOLUTION       ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; --            ; --          ; --         ;
+; PROJECT_OUTPUT_DIRECTORY            ; output_files                          ; --            ; --          ; --         ;
+; TOP_LEVEL_ENTITY                    ; xoro_top                              ; xoro          ; --          ; --         ;
+; VERILOG_INPUT_VERSION               ; SystemVerilog_2005                    ; Verilog_2001  ; --          ; --         ;
+; VERILOG_SHOW_LMF_MAPPING_MESSAGES   ; Off                                   ; --            ; --          ; --         ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                        ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:13     ; 1.0                     ; 4859 MB             ; 00:00:10                           ;
+; Fitter               ; 00:00:15     ; 1.4                     ; 5429 MB             ; 00:00:09                           ;
+; Assembler            ; 00:00:01     ; 1.0                     ; 4761 MB             ; 00:00:01                           ;
+; Total                ; 00:00:29     ; --                      ; --                  ; 00:00:20                           ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++-----------------------------------------------------------------------------------+
+; Flow OS Summary                                                                   ;
++----------------------+------------------+-----------+------------+----------------+
+; Module Name          ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++----------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis ; DESKTOP-5FH9OH3  ; Windows 7 ; 6.2        ; x86_64         ;
+; Fitter               ; DESKTOP-5FH9OH3  ; Windows 7 ; 6.2        ; x86_64         ;
+; Assembler            ; DESKTOP-5FH9OH3  ; Windows 7 ; 6.2        ; x86_64         ;
++----------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off xoro -c xoro
+quartus_fit --read_settings_files=off --write_settings_files=off xoro -c xoro
+quartus_asm --read_settings_files=off --write_settings_files=off xoro -c xoro
+
+
+
diff --git a/rtl/DE0-NANO/output_files/xoro.jdi b/rtl/DE0-NANO/output_files/xoro.jdi
new file mode 100644
index 0000000..0b7ee99
--- /dev/null
+++ b/rtl/DE0-NANO/output_files/xoro.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="7a39fa13c40e9d017722"/>
+  </project>
+  <file_info>
+    <file device="EP4CE22F17C6" path="xoro.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/rtl/DE0-NANO/output_files/xoro.map.rpt b/rtl/DE0-NANO/output_files/xoro.map.rpt
new file mode 100644
index 0000000..21d37c1
--- /dev/null
+++ b/rtl/DE0-NANO/output_files/xoro.map.rpt
@@ -0,0 +1,2677 @@
+Analysis & Synthesis report for xoro
+Sat Sep 16 21:12:28 2023
+Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. Analysis & Synthesis RAM Summary
+  9. Analysis & Synthesis DSP Block Usage Summary
+ 10. State Machine - |xoro_top|picorv32:cpu|mem_wordsize
+ 11. State Machine - |xoro_top|picorv32:cpu|cpu_state
+ 12. State Machine - |xoro_top|AsyncReceiver:uartRx|state
+ 13. State Machine - |xoro_top|uartTx:uartTx|state
+ 14. Registers Removed During Synthesis
+ 15. Removed Registers Triggering Further Register Optimizations
+ 16. General Register Statistics
+ 17. Inverted Register Statistics
+ 18. Registers Added for RAM Pass-Through Logic
+ 19. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 20. Source assignments for Memory:mem|altsyncram:memory_1_symbol0_rtl_0|altsyncram_bdi1:auto_generated
+ 21. Source assignments for Memory:mem|altsyncram:memory_1_symbol1_rtl_0|altsyncram_cdi1:auto_generated
+ 22. Source assignments for picorv32:cpu|altsyncram:cpuregs_rtl_0|altsyncram_trd1:auto_generated
+ 23. Source assignments for picorv32:cpu|altsyncram:cpuregs_rtl_1|altsyncram_trd1:auto_generated
+ 24. Source assignments for Memory:mem|altsyncram:memory_1_symbol3_rtl_0|altsyncram_edi1:auto_generated
+ 25. Source assignments for Memory:mem|altsyncram:memory_1_symbol2_rtl_0|altsyncram_ddi1:auto_generated
+ 26. Source assignments for AsyncReceiver:uartRx|Fifo:fifo_1|altsyncram:mem_rtl_0|altsyncram_s9c1:auto_generated
+ 27. Parameter Settings for User Entity Instance: pll_sys:pll_sys_inst|altpll:altpll_component
+ 28. Parameter Settings for User Entity Instance: picorv32:cpu
+ 29. Parameter Settings for User Entity Instance: picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul
+ 30. Parameter Settings for Inferred Entity Instance: Memory:mem|altsyncram:memory_1_symbol0_rtl_0
+ 31. Parameter Settings for Inferred Entity Instance: Memory:mem|altsyncram:memory_1_symbol1_rtl_0
+ 32. Parameter Settings for Inferred Entity Instance: picorv32:cpu|altsyncram:cpuregs_rtl_0
+ 33. Parameter Settings for Inferred Entity Instance: picorv32:cpu|altsyncram:cpuregs_rtl_1
+ 34. Parameter Settings for Inferred Entity Instance: Memory:mem|altsyncram:memory_1_symbol3_rtl_0
+ 35. Parameter Settings for Inferred Entity Instance: Memory:mem|altsyncram:memory_1_symbol2_rtl_0
+ 36. Parameter Settings for Inferred Entity Instance: AsyncReceiver:uartRx|Fifo:fifo_1|altsyncram:mem_rtl_0
+ 37. Parameter Settings for Inferred Entity Instance: picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0
+ 38. altpll Parameter Settings by Entity Instance
+ 39. altsyncram Parameter Settings by Entity Instance
+ 40. lpm_mult Parameter Settings by Entity Instance
+ 41. Port Connectivity Checks: "picorv32:cpu"
+ 42. Port Connectivity Checks: "busInterface:busInterface"
+ 43. Port Connectivity Checks: "prng:prng|xoroshiro128plus:prng"
+ 44. Port Connectivity Checks: "Memory:mem"
+ 45. Port Connectivity Checks: "hundredMsTick:hundredMsTick"
+ 46. Port Connectivity Checks: "AsyncReceiver:uartRx"
+ 47. Port Connectivity Checks: "gpio:gpio"
+ 48. Port Connectivity Checks: "pll_sys:pll_sys_inst"
+ 49. Post-Synthesis Netlist Statistics for Top Partition
+ 50. Elapsed Time Per Partition
+ 51. Analysis & Synthesis Messages
+ 52. Analysis & Synthesis Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus II License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                    ;
++------------------------------------+--------------------------------------------+
+; Analysis & Synthesis Status        ; Successful - Sat Sep 16 21:12:28 2023      ;
+; Quartus II 64-Bit Version          ; 15.0.0 Build 145 04/22/2015 SJ Web Edition ;
+; Revision Name                      ; xoro                                       ;
+; Top-level Entity Name              ; xoro_top                                   ;
+; Family                             ; Cyclone IV E                               ;
+; Total logic elements               ; 3,155                                      ;
+;     Total combinational functions  ; 2,709                                      ;
+;     Dedicated logic registers      ; 1,420                                      ;
+; Total registers                    ; 1420                                       ;
+; Total pins                         ; 46                                         ;
+; Total virtual pins                 ; 0                                          ;
+; Total memory bits                  ; 330,016                                    ;
+; Embedded Multiplier 9-bit elements ; 8                                          ;
+; Total PLLs                         ; 1                                          ;
++------------------------------------+--------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                        ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                     ; Setting            ; Default Value      ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                     ; EP4CE22F17C6       ;                    ;
+; Top-level entity name                                                      ; xoro_top           ; xoro               ;
+; Family name                                                                ; Cyclone IV E       ; Cyclone V          ;
+; Maximum processors allowed for parallel compilation                        ; 2                  ;                    ;
+; Verilog Show LMF Mapping Messages                                          ; Off                ;                    ;
+; Verilog Version                                                            ; SystemVerilog_2005 ; Verilog_2001       ;
+; Use smart compilation                                                      ; Off                ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
+; Enable compact report table                                                ; Off                ; Off                ;
+; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
+; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
+; Preserve fewer node names                                                  ; On                 ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
+; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                   ; Auto               ; Auto               ;
+; Safe State Machine                                                         ; Off                ; Off                ;
+; Extract Verilog State Machines                                             ; On                 ; On                 ;
+; Extract VHDL State Machines                                                ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
+; Parallel Synthesis                                                         ; On                 ; On                 ;
+; DSP Block Balancing                                                        ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                         ; On                 ; On                 ;
+; Power-Up Don't Care                                                        ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
+; Remove Duplicate Registers                                                 ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
+; Optimization Technique                                                     ; Balanced           ; Balanced           ;
+; Carry Chain Length                                                         ; 70                 ; 70                 ;
+; Auto Carry Chains                                                          ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
+; Auto ROM Replacement                                                       ; On                 ; On                 ;
+; Auto RAM Replacement                                                       ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
+; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
+; Strict RAM Replacement                                                     ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
+; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
+; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                      ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
+; Report Parameter Settings                                                  ; On                 ; On                 ;
+; Report Source Assignments                                                  ; On                 ; On                 ;
+; Report Connectivity Checks                                                 ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
+; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
+; PowerPlay Power Optimization During Synthesis                              ; Normal compilation ; Normal compilation ;
+; HDL message level                                                          ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
+; Clock MUX Protection                                                       ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
+; Block Design Naming                                                        ; Auto               ; Auto               ;
+; SDC constraint protection                                                  ; Off                ; Off                ;
+; Synthesis Effort                                                           ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
+; Synthesis Seed                                                             ; 1                  ; 1                  ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 16          ;
+; Maximum allowed            ; 2           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 2           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ; < 0.1%      ;
+;     Processors 3-16        ;   0.0%      ;
++----------------------------+-------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                                                            ;
++----------------------------------------+-----------------+-------------------------------------------------------+----------------------------------------------------------------------+---------+
+; File Name with User-Entered Path       ; Used in Netlist ; File Type                                             ; File Name with Absolute Path                                         ; Library ;
++----------------------------------------+-----------------+-------------------------------------------------------+----------------------------------------------------------------------+---------+
+; inc/timescale.vh                       ; yes             ; User Unspecified File                                 ; E:/Photonic/RISCV/inc/timescale.vh                                   ;         ;
+; pll_sys.v                              ; yes             ; User Wizard-Generated File                            ; E:/Photonic/RISCV/pll_sys.v                                          ;         ;
+; rtl/timer.v                            ; yes             ; User Verilog HDL File                                 ; E:/Photonic/RISCV/rtl/timer.v                                        ;         ;
+; rtl/uartTx.v                           ; yes             ; User Verilog HDL File                                 ; E:/Photonic/RISCV/rtl/uartTx.v                                       ;         ;
+; rtl/xoroshiro128plus.v                 ; yes             ; User Verilog HDL File                                 ; E:/Photonic/RISCV/rtl/xoroshiro128plus.v                             ;         ;
+; rtl/prng.v                             ; yes             ; User Verilog HDL File                                 ; E:/Photonic/RISCV/rtl/prng.v                                         ;         ;
+; rtl/xoro_top.v                         ; yes             ; User Verilog HDL File                                 ; E:/Photonic/RISCV/rtl/xoro_top.v                                     ;         ;
+; rtl/picorv32.v                         ; yes             ; User Verilog HDL File                                 ; E:/Photonic/RISCV/rtl/picorv32.v                                     ;         ;
+; rtl/memory.v                           ; yes             ; User Verilog HDL File                                 ; E:/Photonic/RISCV/rtl/memory.v                                       ;         ;
+; rtl/gpio.v                             ; yes             ; User Verilog HDL File                                 ; E:/Photonic/RISCV/rtl/gpio.v                                         ;         ;
+; rtl/busInterface.v                     ; yes             ; User Verilog HDL File                                 ; E:/Photonic/RISCV/rtl/busInterface.v                                 ;         ;
+; rtl/AsyncReceiver.v                    ; yes             ; User Verilog HDL File                                 ; E:/Photonic/RISCV/rtl/AsyncReceiver.v                                ;         ;
+; memory.v_toplevel_memory_1_symbol2.bin ; yes             ; Auto-Found Unspecified File                           ; E:/Photonic/RISCV/memory.v_toplevel_memory_1_symbol2.bin             ;         ;
+; memory.v_toplevel_memory_1_symbol1.bin ; yes             ; Auto-Found Unspecified File                           ; E:/Photonic/RISCV/memory.v_toplevel_memory_1_symbol1.bin             ;         ;
+; memory.v_toplevel_memory_1_symbol3.bin ; yes             ; Auto-Found Unspecified File                           ; E:/Photonic/RISCV/memory.v_toplevel_memory_1_symbol3.bin             ;         ;
+; memory.v_toplevel_memory_1_symbol0.bin ; yes             ; Auto-Found Unspecified File                           ; E:/Photonic/RISCV/memory.v_toplevel_memory_1_symbol0.bin             ;         ;
+; altpll.tdf                             ; yes             ; Megafunction                                          ; c:/altera/15.0/quartus/libraries/megafunctions/altpll.tdf            ;         ;
+; aglobal150.inc                         ; yes             ; Megafunction                                          ; c:/altera/15.0/quartus/libraries/megafunctions/aglobal150.inc        ;         ;
+; stratix_pll.inc                        ; yes             ; Megafunction                                          ; c:/altera/15.0/quartus/libraries/megafunctions/stratix_pll.inc       ;         ;
+; stratixii_pll.inc                      ; yes             ; Megafunction                                          ; c:/altera/15.0/quartus/libraries/megafunctions/stratixii_pll.inc     ;         ;
+; cycloneii_pll.inc                      ; yes             ; Megafunction                                          ; c:/altera/15.0/quartus/libraries/megafunctions/cycloneii_pll.inc     ;         ;
+; db/pll_sys_altpll.v                    ; yes             ; Auto-Generated Megafunction                           ; E:/Photonic/RISCV/db/pll_sys_altpll.v                                ;         ;
+; altsyncram.tdf                         ; yes             ; Megafunction                                          ; c:/altera/15.0/quartus/libraries/megafunctions/altsyncram.tdf        ;         ;
+; stratix_ram_block.inc                  ; yes             ; Megafunction                                          ; c:/altera/15.0/quartus/libraries/megafunctions/stratix_ram_block.inc ;         ;
+; lpm_mux.inc                            ; yes             ; Megafunction                                          ; c:/altera/15.0/quartus/libraries/megafunctions/lpm_mux.inc           ;         ;
+; lpm_decode.inc                         ; yes             ; Megafunction                                          ; c:/altera/15.0/quartus/libraries/megafunctions/lpm_decode.inc        ;         ;
+; a_rdenreg.inc                          ; yes             ; Megafunction                                          ; c:/altera/15.0/quartus/libraries/megafunctions/a_rdenreg.inc         ;         ;
+; altrom.inc                             ; yes             ; Megafunction                                          ; c:/altera/15.0/quartus/libraries/megafunctions/altrom.inc            ;         ;
+; altram.inc                             ; yes             ; Megafunction                                          ; c:/altera/15.0/quartus/libraries/megafunctions/altram.inc            ;         ;
+; altdpram.inc                           ; yes             ; Megafunction                                          ; c:/altera/15.0/quartus/libraries/megafunctions/altdpram.inc          ;         ;
+; db/altsyncram_bdi1.tdf                 ; yes             ; Auto-Generated Megafunction                           ; E:/Photonic/RISCV/db/altsyncram_bdi1.tdf                             ;         ;
+; db/xoro.ram0_Memory_a0c6519c.hdl.mif   ; yes             ; Auto-Generated Auto-Found Memory Initialization File  ; E:/Photonic/RISCV/db/xoro.ram0_Memory_a0c6519c.hdl.mif               ;         ;
+; db/decode_jsa.tdf                      ; yes             ; Auto-Generated Megafunction                           ; E:/Photonic/RISCV/db/decode_jsa.tdf                                  ;         ;
+; db/decode_c8a.tdf                      ; yes             ; Auto-Generated Megafunction                           ; E:/Photonic/RISCV/db/decode_c8a.tdf                                  ;         ;
+; db/mux_3nb.tdf                         ; yes             ; Auto-Generated Megafunction                           ; E:/Photonic/RISCV/db/mux_3nb.tdf                                     ;         ;
+; db/altsyncram_cdi1.tdf                 ; yes             ; Auto-Generated Megafunction                           ; E:/Photonic/RISCV/db/altsyncram_cdi1.tdf                             ;         ;
+; db/xoro.ram1_Memory_a0c6519c.hdl.mif   ; yes             ; Auto-Generated Auto-Found Memory Initialization File  ; E:/Photonic/RISCV/db/xoro.ram1_Memory_a0c6519c.hdl.mif               ;         ;
+; db/altsyncram_trd1.tdf                 ; yes             ; Auto-Generated Megafunction                           ; E:/Photonic/RISCV/db/altsyncram_trd1.tdf                             ;         ;
+; db/altsyncram_edi1.tdf                 ; yes             ; Auto-Generated Megafunction                           ; E:/Photonic/RISCV/db/altsyncram_edi1.tdf                             ;         ;
+; db/xoro.ram3_Memory_a0c6519c.hdl.mif   ; yes             ; Auto-Generated Auto-Found Memory Initialization File  ; E:/Photonic/RISCV/db/xoro.ram3_Memory_a0c6519c.hdl.mif               ;         ;
+; db/altsyncram_ddi1.tdf                 ; yes             ; Auto-Generated Megafunction                           ; E:/Photonic/RISCV/db/altsyncram_ddi1.tdf                             ;         ;
+; db/xoro.ram2_Memory_a0c6519c.hdl.mif   ; yes             ; Auto-Generated Auto-Found Memory Initialization File  ; E:/Photonic/RISCV/db/xoro.ram2_Memory_a0c6519c.hdl.mif               ;         ;
+; db/altsyncram_s9c1.tdf                 ; yes             ; Auto-Generated Megafunction                           ; E:/Photonic/RISCV/db/altsyncram_s9c1.tdf                             ;         ;
+; lpm_mult.tdf                           ; yes             ; Megafunction                                          ; c:/altera/15.0/quartus/libraries/megafunctions/lpm_mult.tdf          ;         ;
+; lpm_add_sub.inc                        ; yes             ; Megafunction                                          ; c:/altera/15.0/quartus/libraries/megafunctions/lpm_add_sub.inc       ;         ;
+; multcore.inc                           ; yes             ; Megafunction                                          ; c:/altera/15.0/quartus/libraries/megafunctions/multcore.inc          ;         ;
+; bypassff.inc                           ; yes             ; Megafunction                                          ; c:/altera/15.0/quartus/libraries/megafunctions/bypassff.inc          ;         ;
+; altshift.inc                           ; yes             ; Megafunction                                          ; c:/altera/15.0/quartus/libraries/megafunctions/altshift.inc          ;         ;
+; db/mult_86t.tdf                        ; yes             ; Auto-Generated Megafunction                           ; E:/Photonic/RISCV/db/mult_86t.tdf                                    ;         ;
++----------------------------------------+-----------------+-------------------------------------------------------+----------------------------------------------------------------------+---------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary                                                                                               ;
++---------------------------------------------+---------------------------------------------------------------------------------------------+
+; Resource                                    ; Usage                                                                                       ;
++---------------------------------------------+---------------------------------------------------------------------------------------------+
+; Estimated Total logic elements              ; 3,155                                                                                       ;
+;                                             ;                                                                                             ;
+; Total combinational functions               ; 2709                                                                                        ;
+; Logic element usage by number of LUT inputs ;                                                                                             ;
+;     -- 4 input functions                    ; 1274                                                                                        ;
+;     -- 3 input functions                    ; 1043                                                                                        ;
+;     -- <=2 input functions                  ; 392                                                                                         ;
+;                                             ;                                                                                             ;
+; Logic elements by mode                      ;                                                                                             ;
+;     -- normal mode                          ; 2148                                                                                        ;
+;     -- arithmetic mode                      ; 561                                                                                         ;
+;                                             ;                                                                                             ;
+; Total registers                             ; 1420                                                                                        ;
+;     -- Dedicated logic registers            ; 1420                                                                                        ;
+;     -- I/O registers                        ; 0                                                                                           ;
+;                                             ;                                                                                             ;
+; I/O pins                                    ; 46                                                                                          ;
+; Total memory bits                           ; 330016                                                                                      ;
+;                                             ;                                                                                             ;
+; Embedded Multiplier 9-bit elements          ; 8                                                                                           ;
+;                                             ;                                                                                             ;
+; Total PLLs                                  ; 1                                                                                           ;
+;     -- PLLs                                 ; 1                                                                                           ;
+;                                             ;                                                                                             ;
+; Maximum fan-out node                        ; pll_sys:pll_sys_inst|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] ;
+; Maximum fan-out                             ; 1399                                                                                        ;
+; Total fan-out                               ; 16283                                                                                       ;
+; Average fan-out                             ; 3.73                                                                                        ;
++---------------------------------------------+---------------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                ;
++----------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node                   ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                      ; Library Name ;
++----------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------+--------------+
+; |xoro_top                                    ; 2709 (11)         ; 1420 (9)     ; 330016      ; 8            ; 0       ; 4         ; 46   ; 0            ; |xoro_top                                                                                                ; work         ;
+;    |AsyncReceiver:uartRx|                    ; 110 (75)          ; 78 (36)      ; 256         ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|AsyncReceiver:uartRx                                                                           ; work         ;
+;       |Fifo:fifo_1|                          ; 35 (35)           ; 42 (42)      ; 256         ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|AsyncReceiver:uartRx|Fifo:fifo_1                                                               ; work         ;
+;          |altsyncram:mem_rtl_0|              ; 0 (0)             ; 0 (0)        ; 256         ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|AsyncReceiver:uartRx|Fifo:fifo_1|altsyncram:mem_rtl_0                                          ; work         ;
+;             |altsyncram_s9c1:auto_generated| ; 0 (0)             ; 0 (0)        ; 256         ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|AsyncReceiver:uartRx|Fifo:fifo_1|altsyncram:mem_rtl_0|altsyncram_s9c1:auto_generated           ; work         ;
+;    |Memory:mem|                              ; 70 (54)           ; 192 (180)    ; 327712      ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|Memory:mem                                                                                     ; work         ;
+;       |altsyncram:memory_1_symbol0_rtl_0|    ; 4 (0)             ; 3 (0)        ; 81928       ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol0_rtl_0                                                   ; work         ;
+;          |altsyncram_bdi1:auto_generated|    ; 4 (2)             ; 3 (3)        ; 81928       ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol0_rtl_0|altsyncram_bdi1:auto_generated                    ; work         ;
+;             |decode_jsa:decode2|             ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol0_rtl_0|altsyncram_bdi1:auto_generated|decode_jsa:decode2 ; work         ;
+;       |altsyncram:memory_1_symbol1_rtl_0|    ; 4 (0)             ; 3 (0)        ; 81928       ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol1_rtl_0                                                   ; work         ;
+;          |altsyncram_cdi1:auto_generated|    ; 4 (2)             ; 3 (3)        ; 81928       ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol1_rtl_0|altsyncram_cdi1:auto_generated                    ; work         ;
+;             |decode_jsa:decode2|             ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol1_rtl_0|altsyncram_cdi1:auto_generated|decode_jsa:decode2 ; work         ;
+;       |altsyncram:memory_1_symbol2_rtl_0|    ; 4 (0)             ; 3 (0)        ; 81928       ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol2_rtl_0                                                   ; work         ;
+;          |altsyncram_ddi1:auto_generated|    ; 4 (2)             ; 3 (3)        ; 81928       ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol2_rtl_0|altsyncram_ddi1:auto_generated                    ; work         ;
+;             |decode_jsa:decode2|             ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol2_rtl_0|altsyncram_ddi1:auto_generated|decode_jsa:decode2 ; work         ;
+;       |altsyncram:memory_1_symbol3_rtl_0|    ; 4 (0)             ; 3 (0)        ; 81928       ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol3_rtl_0                                                   ; work         ;
+;          |altsyncram_edi1:auto_generated|    ; 4 (2)             ; 3 (3)        ; 81928       ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol3_rtl_0|altsyncram_edi1:auto_generated                    ; work         ;
+;             |decode_jsa:decode2|             ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol3_rtl_0|altsyncram_edi1:auto_generated|decode_jsa:decode2 ; work         ;
+;    |busInterface:busInterface|               ; 171 (171)         ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|busInterface:busInterface                                                                      ; work         ;
+;    |gpio:gpio|                               ; 10 (10)           ; 17 (17)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|gpio:gpio                                                                                      ; work         ;
+;    |picorv32:cpu|                            ; 2112 (1671)       ; 866 (533)    ; 2048        ; 8            ; 0       ; 4         ; 0    ; 0            ; |xoro_top|picorv32:cpu                                                                                   ; work         ;
+;       |altsyncram:cpuregs_rtl_0|             ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|picorv32:cpu|altsyncram:cpuregs_rtl_0                                                          ; work         ;
+;          |altsyncram_trd1:auto_generated|    ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|picorv32:cpu|altsyncram:cpuregs_rtl_0|altsyncram_trd1:auto_generated                           ; work         ;
+;       |altsyncram:cpuregs_rtl_1|             ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|picorv32:cpu|altsyncram:cpuregs_rtl_1                                                          ; work         ;
+;          |altsyncram_trd1:auto_generated|    ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|picorv32:cpu|altsyncram:cpuregs_rtl_1|altsyncram_trd1:auto_generated                           ; work         ;
+;       |picorv32_pcpi_div:pcpi_div|           ; 343 (343)         ; 200 (200)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|picorv32:cpu|picorv32_pcpi_div:pcpi_div                                                        ; work         ;
+;       |picorv32_pcpi_fast_mul:pcpi_mul|      ; 98 (52)           ; 133 (133)    ; 0           ; 8            ; 0       ; 4         ; 0    ; 0            ; |xoro_top|picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul                                                   ; work         ;
+;          |lpm_mult:Mult0|                    ; 46 (0)            ; 0 (0)        ; 0           ; 8            ; 0       ; 4         ; 0    ; 0            ; |xoro_top|picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0                                    ; work         ;
+;             |mult_86t:auto_generated|        ; 46 (46)           ; 0 (0)        ; 0           ; 8            ; 0       ; 4         ; 0    ; 0            ; |xoro_top|picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated            ; work         ;
+;    |pll_sys:pll_sys_inst|                    ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|pll_sys:pll_sys_inst                                                                           ; work         ;
+;       |altpll:altpll_component|              ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|pll_sys:pll_sys_inst|altpll:altpll_component                                                   ; work         ;
+;          |pll_sys_altpll:auto_generated|     ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|pll_sys:pll_sys_inst|altpll:altpll_component|pll_sys_altpll:auto_generated                     ; work         ;
+;    |prng:prng|                               ; 160 (1)           ; 193 (34)     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|prng:prng                                                                                      ; work         ;
+;       |xoroshiro128plus:prng|                ; 159 (159)         ; 159 (159)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|prng:prng|xoroshiro128plus:prng                                                                ; work         ;
+;    |timer:timer|                             ; 33 (33)           ; 33 (33)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|timer:timer                                                                                    ; work         ;
+;    |uartTx:uartTx|                           ; 32 (26)           ; 32 (26)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|uartTx:uartTx                                                                                  ; work         ;
+;       |BaudRateGenerator:baudRateGenerator|  ; 6 (4)             ; 6 (4)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|uartTx:uartTx|BaudRateGenerator:baudRateGenerator                                              ; work         ;
+;          |EdgeDetect:baudClockEdgeDetect|    ; 1 (1)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|uartTx:uartTx|BaudRateGenerator:baudRateGenerator|EdgeDetect:baudClockEdgeDetect               ; work         ;
+;          |EdgeDetect:bitClockEdgeDetect|     ; 1 (1)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |xoro_top|uartTx:uartTx|BaudRateGenerator:baudRateGenerator|EdgeDetect:bitClockEdgeDetect                ; work         ;
++----------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis RAM Summary                                                                                                                                                                                                     ;
++-------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+--------------------------------------+
+; Name                                                                                            ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size  ; MIF                                  ;
++-------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+--------------------------------------+
+; AsyncReceiver:uartRx|Fifo:fifo_1|altsyncram:mem_rtl_0|altsyncram_s9c1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 32           ; 8            ; 32           ; 8            ; 256   ; None                                 ;
+; Memory:mem|altsyncram:memory_1_symbol0_rtl_0|altsyncram_bdi1:auto_generated|ALTSYNCRAM          ; AUTO ; Simple Dual Port ; 10241        ; 8            ; 10241        ; 8            ; 81928 ; db/xoro.ram0_Memory_a0c6519c.hdl.mif ;
+; Memory:mem|altsyncram:memory_1_symbol1_rtl_0|altsyncram_cdi1:auto_generated|ALTSYNCRAM          ; AUTO ; Simple Dual Port ; 10241        ; 8            ; 10241        ; 8            ; 81928 ; db/xoro.ram1_Memory_a0c6519c.hdl.mif ;
+; Memory:mem|altsyncram:memory_1_symbol2_rtl_0|altsyncram_ddi1:auto_generated|ALTSYNCRAM          ; AUTO ; Simple Dual Port ; 10241        ; 8            ; 10241        ; 8            ; 81928 ; db/xoro.ram2_Memory_a0c6519c.hdl.mif ;
+; Memory:mem|altsyncram:memory_1_symbol3_rtl_0|altsyncram_edi1:auto_generated|ALTSYNCRAM          ; AUTO ; Simple Dual Port ; 10241        ; 8            ; 10241        ; 8            ; 81928 ; db/xoro.ram3_Memory_a0c6519c.hdl.mif ;
+; picorv32:cpu|altsyncram:cpuregs_rtl_0|altsyncram_trd1:auto_generated|ALTSYNCRAM                 ; AUTO ; Simple Dual Port ; 32           ; 32           ; 32           ; 32           ; 1024  ; None                                 ;
+; picorv32:cpu|altsyncram:cpuregs_rtl_1|altsyncram_trd1:auto_generated|ALTSYNCRAM                 ; AUTO ; Simple Dual Port ; 32           ; 32           ; 32           ; 32           ; 1024  ; None                                 ;
++-------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+--------------------------------------+
+
+
++-----------------------------------------------------+
+; Analysis & Synthesis DSP Block Usage Summary        ;
++---------------------------------------+-------------+
+; Statistic                             ; Number Used ;
++---------------------------------------+-------------+
+; Simple Multipliers (9-bit)            ; 0           ;
+; Simple Multipliers (18-bit)           ; 4           ;
+; Embedded Multiplier Blocks            ; --          ;
+; Embedded Multiplier 9-bit elements    ; 8           ;
+; Signed Embedded Multipliers           ; 1           ;
+; Unsigned Embedded Multipliers         ; 1           ;
+; Mixed Sign Embedded Multipliers       ; 2           ;
+; Variable Sign Embedded Multipliers    ; 0           ;
+; Dedicated Input Shift Register Chains ; 0           ;
++---------------------------------------+-------------+
+Note: number of Embedded Multiplier Blocks used is only available after a successful fit.
+
+
+Encoding Type:  One-Hot
++-----------------------------------------------------------------------+
+; State Machine - |xoro_top|picorv32:cpu|mem_wordsize                   ;
++-----------------+-----------------+-----------------+-----------------+
+; Name            ; mem_wordsize.00 ; mem_wordsize.10 ; mem_wordsize.01 ;
++-----------------+-----------------+-----------------+-----------------+
+; mem_wordsize.00 ; 0               ; 0               ; 0               ;
+; mem_wordsize.01 ; 1               ; 0               ; 1               ;
+; mem_wordsize.10 ; 1               ; 1               ; 0               ;
++-----------------+-----------------+-----------------+-----------------+
+
+
+Encoding Type:  One-Hot
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; State Machine - |xoro_top|picorv32:cpu|cpu_state                                                                                                                                                                                                           ;
++----------------------------+--------------------------+---------------------------+----------------------------+----------------------------+--------------------------+---------------------------+---------------------------+---------------------------+
+; Name                       ; cpu_state.cpu_state_trap ; cpu_state.cpu_state_fetch ; cpu_state.cpu_state_ld_rs1 ; cpu_state.cpu_state_ld_rs2 ; cpu_state.cpu_state_exec ; cpu_state.cpu_state_shift ; cpu_state.cpu_state_stmem ; cpu_state.cpu_state_ldmem ;
++----------------------------+--------------------------+---------------------------+----------------------------+----------------------------+--------------------------+---------------------------+---------------------------+---------------------------+
+; cpu_state.cpu_state_trap   ; 0                        ; 0                         ; 0                          ; 0                          ; 0                        ; 0                         ; 0                         ; 0                         ;
+; cpu_state.cpu_state_stmem  ; 1                        ; 0                         ; 0                          ; 0                          ; 0                        ; 0                         ; 1                         ; 0                         ;
+; cpu_state.cpu_state_shift  ; 1                        ; 0                         ; 0                          ; 0                          ; 0                        ; 1                         ; 0                         ; 0                         ;
+; cpu_state.cpu_state_exec   ; 1                        ; 0                         ; 0                          ; 0                          ; 1                        ; 0                         ; 0                         ; 0                         ;
+; cpu_state.cpu_state_ld_rs2 ; 1                        ; 0                         ; 0                          ; 1                          ; 0                        ; 0                         ; 0                         ; 0                         ;
+; cpu_state.cpu_state_ld_rs1 ; 1                        ; 0                         ; 1                          ; 0                          ; 0                        ; 0                         ; 0                         ; 0                         ;
+; cpu_state.cpu_state_fetch  ; 1                        ; 1                         ; 0                          ; 0                          ; 0                        ; 0                         ; 0                         ; 0                         ;
+; cpu_state.cpu_state_ldmem  ; 1                        ; 0                         ; 0                          ; 0                          ; 0                        ; 0                         ; 0                         ; 1                         ;
++----------------------------+--------------------------+---------------------------+----------------------------+----------------------------+--------------------------+---------------------------+---------------------------+---------------------------+
+
+
+Encoding Type:  One-Hot
++------------------------------------------------------+
+; State Machine - |xoro_top|AsyncReceiver:uartRx|state ;
++----------+----------+----------+----------+----------+
+; Name     ; state.11 ; state.10 ; state.01 ; state.00 ;
++----------+----------+----------+----------+----------+
+; state.00 ; 0        ; 0        ; 0        ; 0        ;
+; state.01 ; 0        ; 0        ; 1        ; 1        ;
+; state.10 ; 0        ; 1        ; 0        ; 1        ;
+; state.11 ; 1        ; 0        ; 0        ; 1        ;
++----------+----------+----------+----------+----------+
+
+
+Encoding Type:  One-Hot
++-------------------------------------------------------------------+
+; State Machine - |xoro_top|uartTx:uartTx|state                     ;
++----------------+----------------+----------------+----------------+
+; Name           ; state.00000000 ; state.00000010 ; state.00000001 ;
++----------------+----------------+----------------+----------------+
+; state.00000000 ; 0              ; 0              ; 0              ;
+; state.00000001 ; 1              ; 0              ; 1              ;
+; state.00000010 ; 1              ; 1              ; 0              ;
++----------------+----------------+----------------+----------------+
+
+
++------------------------------------------------------------------------------------------------------------------+
+; Registers Removed During Synthesis                                                                               ;
++----------------------------------------------------+-------------------------------------------------------------+
+; Register name                                      ; Reason for Removal                                          ;
++----------------------------------------------------+-------------------------------------------------------------+
+; picorv32:cpu|instr_retirq                          ; Stuck at GND due to stuck port data_in                      ;
+; picorv32:cpu|instr_waitirq                         ; Stuck at GND due to stuck port data_in                      ;
+; picorv32:cpu|decoded_imm_uj[0]                     ; Stuck at GND due to stuck port data_in                      ;
+; picorv32:cpu|compressed_instr                      ; Stuck at GND due to stuck port data_in                      ;
+; picorv32:cpu|instr_rdcycle                         ; Stuck at GND due to stuck port data_in                      ;
+; picorv32:cpu|instr_rdcycleh                        ; Stuck at GND due to stuck port data_in                      ;
+; picorv32:cpu|instr_rdinstr                         ; Stuck at GND due to stuck port data_in                      ;
+; picorv32:cpu|instr_rdinstrh                        ; Stuck at GND due to stuck port data_in                      ;
+; picorv32:cpu|instr_getq                            ; Stuck at GND due to stuck port data_in                      ;
+; picorv32:cpu|instr_setq                            ; Stuck at GND due to stuck port data_in                      ;
+; picorv32:cpu|instr_maskirq                         ; Stuck at GND due to stuck port data_in                      ;
+; picorv32:cpu|instr_timer                           ; Stuck at GND due to stuck port data_in                      ;
+; picorv32:cpu|do_waitirq                            ; Stuck at GND due to stuck port data_in                      ;
+; picorv32:cpu|mem_addr[0,1]                         ; Stuck at GND due to stuck port data_in                      ;
+; picorv32:cpu|latched_compr                         ; Stuck at GND due to stuck port data_in                      ;
+; picorv32:cpu|decoded_imm_uj[20..30]                ; Merged with picorv32:cpu|decoded_imm_uj[31]                 ;
+; picorv32:cpu|decoded_rs1[4]                        ; Merged with picorv32:cpu|decoded_imm_uj[19]                 ;
+; picorv32:cpu|decoded_rs1[3]                        ; Merged with picorv32:cpu|decoded_imm_uj[18]                 ;
+; picorv32:cpu|decoded_rs1[2]                        ; Merged with picorv32:cpu|decoded_imm_uj[17]                 ;
+; picorv32:cpu|decoded_rs1[1]                        ; Merged with picorv32:cpu|decoded_imm_uj[16]                 ;
+; picorv32:cpu|decoded_rs1[0]                        ; Merged with picorv32:cpu|decoded_imm_uj[15]                 ;
+; picorv32:cpu|decoded_rs2[0]                        ; Merged with picorv32:cpu|decoded_imm_uj[11]                 ;
+; picorv32:cpu|decoded_rs2[4]                        ; Merged with picorv32:cpu|decoded_imm_uj[4]                  ;
+; picorv32:cpu|decoded_rs2[3]                        ; Merged with picorv32:cpu|decoded_imm_uj[3]                  ;
+; picorv32:cpu|decoded_rs2[2]                        ; Merged with picorv32:cpu|decoded_imm_uj[2]                  ;
+; picorv32:cpu|decoded_rs2[1]                        ; Merged with picorv32:cpu|decoded_imm_uj[1]                  ;
+; picorv32:cpu|reg_next_pc[0]                        ; Merged with picorv32:cpu|reg_pc[0]                          ;
+; picorv32:cpu|picorv32_pcpi_div:pcpi_div|pcpi_ready ; Merged with picorv32:cpu|picorv32_pcpi_div:pcpi_div|pcpi_wr ;
+; AsyncReceiver:uartRx|_zz_3                         ; Merged with AsyncReceiver:uartRx|_zz_1                      ;
+; AsyncReceiver:uartRx|Fifo:fifo_1|_zz_3             ; Merged with AsyncReceiver:uartRx|Fifo:fifo_1|_zz_1          ;
+; AsyncReceiver:uartRx|Fifo:fifo_1|_zz_4             ; Merged with AsyncReceiver:uartRx|Fifo:fifo_1|_zz_2          ;
+; picorv32:cpu|reg_pc[0]                             ; Stuck at GND due to stuck port data_in                      ;
+; prng:prng|xoroshiro128plus:prng|s1[36]             ; Merged with prng:prng|xoroshiro128plus:prng|ss[0]           ;
+; picorv32:cpu|latched_is_lu                         ; Lost fanout                                                 ;
+; picorv32:cpu|is_lbu_lhu_lw                         ; Lost fanout                                                 ;
+; AsyncReceiver:uartRx|state~4                       ; Lost fanout                                                 ;
+; AsyncReceiver:uartRx|state~5                       ; Lost fanout                                                 ;
+; uartTx:uartTx|state~9                              ; Lost fanout                                                 ;
+; uartTx:uartTx|state~10                             ; Lost fanout                                                 ;
+; uartTx:uartTx|state~11                             ; Lost fanout                                                 ;
+; uartTx:uartTx|state~12                             ; Lost fanout                                                 ;
+; uartTx:uartTx|state~13                             ; Lost fanout                                                 ;
+; uartTx:uartTx|state~14                             ; Lost fanout                                                 ;
+; picorv32:cpu|cpu_state.cpu_state_shift             ; Stuck at GND due to stuck port data_in                      ;
+; picorv32:cpu|cpu_state.cpu_state_ld_rs2            ; Stuck at GND due to stuck port data_in                      ;
+; Total Number of Removed Registers = 56             ;                                                             ;
++----------------------------------------------------+-------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Removed Registers Triggering Further Register Optimizations                                        ;
++-------------------------------+---------------------------+----------------------------------------+
+; Register name                 ; Reason for Removal        ; Registers Removed due to This Register ;
++-------------------------------+---------------------------+----------------------------------------+
+; picorv32:cpu|compressed_instr ; Stuck at GND              ; picorv32:cpu|latched_compr             ;
+;                               ; due to stuck port data_in ;                                        ;
+; picorv32:cpu|latched_is_lu    ; Lost Fanouts              ; picorv32:cpu|is_lbu_lhu_lw             ;
++-------------------------------+---------------------------+----------------------------------------+
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 1420  ;
+; Number of registers using Synchronous Clear  ; 129   ;
+; Number of registers using Synchronous Load   ; 172   ;
+; Number of registers using Asynchronous Clear ; 242   ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 660   ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++-------------------------------------------------------------------------------+
+; Inverted Register Statistics                                                  ;
++---------------------------------------------------------------------+---------+
+; Inverted Register                                                   ; Fan out ;
++---------------------------------------------------------------------+---------+
+; uartTx:uartTx|serialOut                                             ; 2       ;
+; uartTx:uartTx|bufferEmpty                                           ; 9       ;
+; uartTx:uartTx|BaudRateGenerator:baudRateGenerator|baudClockcount[2] ; 2       ;
+; uartTx:uartTx|BaudRateGenerator:baudRateGenerator|baudClockcount[0] ; 4       ;
+; uartTx:uartTx|BaudRateGenerator:baudRateGenerator|baudClockcount[1] ; 3       ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[42]                        ; 1       ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[41]                        ; 1       ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[42]                        ; 1       ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[42]                        ; 1       ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[41]                        ; 1       ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[42]                        ; 1       ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[38]                        ; 1       ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[38]                        ; 1       ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[38]                        ; 1       ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[38]                        ; 1       ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[40]                        ; 1       ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[39]                        ; 1       ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[40]                        ; 1       ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[40]                        ; 1       ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[40]                        ; 1       ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[44]                        ; 1       ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[44]                        ; 1       ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[44]                        ; 1       ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[44]                        ; 1       ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[36]                        ; 1       ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[36]                        ; 1       ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[35]                        ; 1       ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[34]                        ; 1       ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[34]                        ; 1       ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[32]                        ; 1       ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[32]                        ; 1       ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[30]                        ; 1       ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[30]                        ; 1       ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[30]                        ; 1       ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[36]                        ; 1       ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[34]                        ; 1       ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[32]                        ; 1       ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[32]                        ; 1       ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[31]                        ; 1       ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[30]                        ; 1       ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[29]                        ; 1       ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[36]                        ; 1       ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[35]                        ; 1       ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[34]                        ; 1       ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[33]                        ; 1       ;
+; AsyncReceiver:uartRx|Fifo:fifo_1|empty                              ; 5       ;
+; prng:prng|xoroshiro128plus:prng|s0[0]                               ; 2       ;
+; Total number of inverted registers = 47                             ;         ;
++---------------------------------------------------------------------+---------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Registers Added for RAM Pass-Through Logic                                                         ;
++-------------------------------------------------------+--------------------------------------------+
+; Register Name                                         ; RAM Name                                   ;
++-------------------------------------------------------+--------------------------------------------+
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[0]           ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[1]           ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[2]           ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[3]           ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[4]           ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[5]           ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[6]           ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[7]           ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[8]           ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[9]           ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[10]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[11]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[12]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[13]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[14]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[15]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[16]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[17]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[18]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[19]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[20]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[21]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[22]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[23]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[24]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[25]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[26]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[27]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[28]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[29]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[30]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[31]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[32]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[33]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[34]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[35]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[36]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[37]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[38]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[39]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[40]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[41]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[42]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[43]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol0_rtl_0_bypass[44]          ; Memory:mem|memory_1_symbol0_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[0]           ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[1]           ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[2]           ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[3]           ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[4]           ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[5]           ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[6]           ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[7]           ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[8]           ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[9]           ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[10]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[11]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[12]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[13]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[14]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[15]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[16]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[17]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[18]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[19]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[20]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[21]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[22]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[23]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[24]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[25]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[26]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[27]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[28]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[29]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[30]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[31]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[32]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[33]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[34]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[35]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[36]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[37]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[38]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[39]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[40]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[41]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[42]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[43]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; Memory:mem|memory_1_symbol1_rtl_0_bypass[44]          ; Memory:mem|memory_1_symbol1_rtl_0          ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[0]                  ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[1]                  ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[2]                  ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[3]                  ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[4]                  ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[5]                  ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[6]                  ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[7]                  ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[8]                  ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[9]                  ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[10]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[11]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[12]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[13]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[14]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[15]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[16]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[17]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[18]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[19]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[20]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[21]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[22]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[23]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[24]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[25]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[26]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[27]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[28]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[29]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[30]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[31]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[32]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[33]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[34]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[35]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[36]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[37]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[38]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[39]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[40]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[41]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_0_bypass[42]                 ; picorv32:cpu|cpuregs_rtl_0                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[0]                  ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[1]                  ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[2]                  ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[3]                  ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[4]                  ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[5]                  ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[6]                  ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[7]                  ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[8]                  ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[9]                  ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[10]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[11]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[12]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[13]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[14]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[15]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[16]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[17]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[18]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[19]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[20]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[21]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[22]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[23]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[24]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[25]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[26]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[27]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[28]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[29]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[30]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[31]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[32]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[33]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[34]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[35]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[36]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[37]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[38]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[39]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[40]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[41]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; picorv32:cpu|cpuregs_rtl_1_bypass[42]                 ; picorv32:cpu|cpuregs_rtl_1                 ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[0]           ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[1]           ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[2]           ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[3]           ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[4]           ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[5]           ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[6]           ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[7]           ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[8]           ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[9]           ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[10]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[11]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[12]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[13]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[14]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[15]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[16]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[17]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[18]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[19]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[20]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[21]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[22]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[23]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[24]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[25]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[26]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[27]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[28]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[29]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[30]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[31]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[32]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[33]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[34]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[35]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[36]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[37]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[38]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[39]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[40]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[41]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[42]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[43]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol3_rtl_0_bypass[44]          ; Memory:mem|memory_1_symbol3_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[0]           ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[1]           ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[2]           ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[3]           ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[4]           ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[5]           ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[6]           ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[7]           ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[8]           ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[9]           ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[10]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[11]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[12]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[13]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[14]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[15]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[16]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[17]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[18]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[19]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[20]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[21]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[22]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[23]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[24]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[25]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[26]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[27]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[28]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[29]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[30]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[31]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[32]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[33]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[34]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[35]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[36]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[37]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[38]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[39]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[40]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[41]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[42]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[43]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; Memory:mem|memory_1_symbol2_rtl_0_bypass[44]          ; Memory:mem|memory_1_symbol2_rtl_0          ;
+; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[0]  ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
+; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[1]  ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
+; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[2]  ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
+; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[3]  ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
+; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[4]  ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
+; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[5]  ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
+; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[6]  ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
+; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[7]  ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
+; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[8]  ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
+; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[9]  ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
+; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[10] ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
+; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[11] ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
+; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[12] ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
+; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[13] ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
+; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[14] ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
+; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[15] ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
+; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[16] ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
+; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[17] ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
+; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[18] ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
++-------------------------------------------------------+--------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                               ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                     ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------+
+; 3:1                ; 31 bits   ; 62 LEs        ; 31 LEs               ; 31 LEs                 ; Yes        ; |xoro_top|picorv32:cpu|reg_pc[22]                              ;
+; 3:1                ; 22 bits   ; 44 LEs        ; 22 LEs               ; 22 LEs                 ; Yes        ; |xoro_top|picorv32:cpu|instr_sltiu                             ;
+; 3:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |xoro_top|picorv32:cpu|mem_addr[29]                            ;
+; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |xoro_top|picorv32:cpu|pcpi_timeout_counter[0]                 ;
+; 3:1                ; 62 bits   ; 124 LEs       ; 62 LEs               ; 62 LEs                 ; Yes        ; |xoro_top|picorv32:cpu|picorv32_pcpi_div:pcpi_div|divisor[21]  ;
+; 4:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; Yes        ; |xoro_top|picorv32:cpu|picorv32_pcpi_div:pcpi_div|pcpi_rd[15]  ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |xoro_top|picorv32:cpu|reg_sh[0]                               ;
+; 3:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |xoro_top|picorv32:cpu|reg_sh[3]                               ;
+; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |xoro_top|picorv32:cpu|mem_wdata[31]                           ;
+; 4:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |xoro_top|gpio:gpio|gpio[0]                                    ;
+; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |xoro_top|picorv32:cpu|mem_wstrb[1]                            ;
+; 4:1                ; 31 bits   ; 62 LEs        ; 62 LEs               ; 0 LEs                  ; Yes        ; |xoro_top|picorv32:cpu|picorv32_pcpi_div:pcpi_div|divisor[31]  ;
+; 5:1                ; 30 bits   ; 90 LEs        ; 60 LEs               ; 30 LEs                 ; Yes        ; |xoro_top|picorv32:cpu|reg_next_pc[15]                         ;
+; 4:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; Yes        ; |xoro_top|picorv32:cpu|latched_rd[4]                           ;
+; 3:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; Yes        ; |xoro_top|picorv32:cpu|decoded_imm[5]                          ;
+; 3:1                ; 19 bits   ; 38 LEs        ; 38 LEs               ; 0 LEs                  ; Yes        ; |xoro_top|picorv32:cpu|decoded_imm[14]                         ;
+; 4:1                ; 5 bits    ; 10 LEs        ; 0 LEs                ; 10 LEs                 ; Yes        ; |xoro_top|AsyncReceiver:uartRx|Fifo:fifo_1|head[3]             ;
+; 5:1                ; 32 bits   ; 96 LEs        ; 64 LEs               ; 32 LEs                 ; Yes        ; |xoro_top|picorv32:cpu|picorv32_pcpi_div:pcpi_div|dividend[26] ;
+; 5:1                ; 4 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; Yes        ; |xoro_top|uartTx:uartTx|bitCount[3]                            ;
+; 5:1                ; 7 bits    ; 21 LEs        ; 7 LEs                ; 14 LEs                 ; Yes        ; |xoro_top|uartTx:uartTx|shifter[1]                             ;
+; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |xoro_top|picorv32:cpu|decoded_imm[4]                          ;
+; 4:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; Yes        ; |xoro_top|AsyncReceiver:uartRx|bitTimer[3]                     ;
+; 6:1                ; 5 bits    ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; Yes        ; |xoro_top|picorv32:cpu|reg_op2[1]                              ;
+; 11:1               ; 2 bits    ; 14 LEs        ; 6 LEs                ; 8 LEs                  ; Yes        ; |xoro_top|picorv32:cpu|mem_state[0]                            ;
+; 10:1               ; 8 bits    ; 48 LEs        ; 48 LEs               ; 0 LEs                  ; Yes        ; |xoro_top|picorv32:cpu|alu_out_q[19]                           ;
+; 10:1               ; 8 bits    ; 48 LEs        ; 48 LEs               ; 0 LEs                  ; Yes        ; |xoro_top|picorv32:cpu|alu_out_q[9]                            ;
+; 7:1                ; 27 bits   ; 108 LEs       ; 54 LEs               ; 54 LEs                 ; Yes        ; |xoro_top|picorv32:cpu|reg_op2[28]                             ;
+; 11:1               ; 4 bits    ; 28 LEs        ; 28 LEs               ; 0 LEs                  ; Yes        ; |xoro_top|picorv32:cpu|alu_out_q[24]                           ;
+; 11:1               ; 4 bits    ; 28 LEs        ; 28 LEs               ; 0 LEs                  ; Yes        ; |xoro_top|picorv32:cpu|alu_out_q[4]                            ;
+; 7:1                ; 8 bits    ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |xoro_top|picorv32:cpu|reg_out[15]                             ;
+; 12:1               ; 2 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |xoro_top|picorv32:cpu|alu_out_q[29]                           ;
+; 12:1               ; 2 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |xoro_top|picorv32:cpu|alu_out_q[3]                            ;
+; 13:1               ; 2 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |xoro_top|picorv32:cpu|alu_out_q[30]                           ;
+; 9:1                ; 16 bits   ; 96 LEs        ; 96 LEs               ; 0 LEs                  ; Yes        ; |xoro_top|picorv32:cpu|reg_out[30]                             ;
+; 9:1                ; 7 bits    ; 42 LEs        ; 35 LEs               ; 7 LEs                  ; Yes        ; |xoro_top|picorv32:cpu|reg_out[1]                              ;
+; 16:1               ; 3 bits    ; 30 LEs        ; 12 LEs               ; 18 LEs                 ; Yes        ; |xoro_top|picorv32:cpu|reg_op1[30]                             ;
+; 17:1               ; 3 bits    ; 33 LEs        ; 15 LEs               ; 18 LEs                 ; Yes        ; |xoro_top|picorv32:cpu|reg_op1[3]                              ;
+; 17:1               ; 24 bits   ; 264 LEs       ; 144 LEs              ; 120 LEs                ; Yes        ; |xoro_top|picorv32:cpu|reg_op1[17]                             ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |xoro_top|AsyncReceiver:uartRx|state                           ;
+; 3:1                ; 31 bits   ; 62 LEs        ; 31 LEs               ; 31 LEs                 ; No         ; |xoro_top|picorv32:cpu|current_pc                              ;
+; 3:1                ; 14 bits   ; 28 LEs        ; 28 LEs               ; 0 LEs                  ; No         ; |xoro_top|picorv32:cpu|mem_la_addr[15]                         ;
+; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; No         ; |xoro_top|picorv32:cpu|cpuregs_rs2[0]                          ;
+; 3:1                ; 7 bits    ; 14 LEs        ; 14 LEs               ; 0 LEs                  ; No         ; |xoro_top|AsyncReceiver:uartRx|Fifo:fifo_1|mem                 ;
+; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; No         ; |xoro_top|picorv32:cpu|latched_is_lh                           ;
+; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |xoro_top|picorv32:cpu|Selector41                              ;
+; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |xoro_top|picorv32:cpu|Selector44                              ;
+; 4:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; No         ; |xoro_top|AsyncReceiver:uartRx|Fifo:fifo_1|tail                ;
+; 9:1                ; 3 bits    ; 18 LEs        ; 6 LEs                ; 12 LEs                 ; No         ; |xoro_top|picorv32:cpu|mem_wordsize                            ;
+; 19:1               ; 5 bits    ; 60 LEs        ; 35 LEs               ; 25 LEs                 ; No         ; |xoro_top|picorv32:cpu|cpu_state                               ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Source assignments for Memory:mem|altsyncram:memory_1_symbol0_rtl_0|altsyncram_bdi1:auto_generated ;
++---------------------------------+--------------------+------+--------------------------------------+
+; Assignment                      ; Value              ; From ; To                                   ;
++---------------------------------+--------------------+------+--------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                    ;
++---------------------------------+--------------------+------+--------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Source assignments for Memory:mem|altsyncram:memory_1_symbol1_rtl_0|altsyncram_cdi1:auto_generated ;
++---------------------------------+--------------------+------+--------------------------------------+
+; Assignment                      ; Value              ; From ; To                                   ;
++---------------------------------+--------------------+------+--------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                    ;
++---------------------------------+--------------------+------+--------------------------------------+
+
+
++---------------------------------------------------------------------------------------------+
+; Source assignments for picorv32:cpu|altsyncram:cpuregs_rtl_0|altsyncram_trd1:auto_generated ;
++---------------------------------+--------------------+------+-------------------------------+
+; Assignment                      ; Value              ; From ; To                            ;
++---------------------------------+--------------------+------+-------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                             ;
++---------------------------------+--------------------+------+-------------------------------+
+
+
++---------------------------------------------------------------------------------------------+
+; Source assignments for picorv32:cpu|altsyncram:cpuregs_rtl_1|altsyncram_trd1:auto_generated ;
++---------------------------------+--------------------+------+-------------------------------+
+; Assignment                      ; Value              ; From ; To                            ;
++---------------------------------+--------------------+------+-------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                             ;
++---------------------------------+--------------------+------+-------------------------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Source assignments for Memory:mem|altsyncram:memory_1_symbol3_rtl_0|altsyncram_edi1:auto_generated ;
++---------------------------------+--------------------+------+--------------------------------------+
+; Assignment                      ; Value              ; From ; To                                   ;
++---------------------------------+--------------------+------+--------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                    ;
++---------------------------------+--------------------+------+--------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Source assignments for Memory:mem|altsyncram:memory_1_symbol2_rtl_0|altsyncram_ddi1:auto_generated ;
++---------------------------------+--------------------+------+--------------------------------------+
+; Assignment                      ; Value              ; From ; To                                   ;
++---------------------------------+--------------------+------+--------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                    ;
++---------------------------------+--------------------+------+--------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Source assignments for AsyncReceiver:uartRx|Fifo:fifo_1|altsyncram:mem_rtl_0|altsyncram_s9c1:auto_generated ;
++---------------------------------+--------------------+------+-----------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                            ;
++---------------------------------+--------------------+------+-----------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                             ;
++---------------------------------+--------------------+------+-----------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: pll_sys:pll_sys_inst|altpll:altpll_component ;
++-------------------------------+---------------------------+-------------------------------+
+; Parameter Name                ; Value                     ; Type                          ;
++-------------------------------+---------------------------+-------------------------------+
+; OPERATION_MODE                ; NORMAL                    ; Untyped                       ;
+; PLL_TYPE                      ; AUTO                      ; Untyped                       ;
+; LPM_HINT                      ; CBX_MODULE_PREFIX=pll_sys ; Untyped                       ;
+; QUALIFY_CONF_DONE             ; OFF                       ; Untyped                       ;
+; COMPENSATE_CLOCK              ; CLK0                      ; Untyped                       ;
+; SCAN_CHAIN                    ; LONG                      ; Untyped                       ;
+; PRIMARY_CLOCK                 ; INCLK0                    ; Untyped                       ;
+; INCLK0_INPUT_FREQUENCY        ; 20000                     ; Signed Integer                ;
+; INCLK1_INPUT_FREQUENCY        ; 0                         ; Untyped                       ;
+; GATE_LOCK_SIGNAL              ; NO                        ; Untyped                       ;
+; GATE_LOCK_COUNTER             ; 0                         ; Untyped                       ;
+; LOCK_HIGH                     ; 1                         ; Untyped                       ;
+; LOCK_LOW                      ; 1                         ; Untyped                       ;
+; VALID_LOCK_MULTIPLIER         ; 1                         ; Untyped                       ;
+; INVALID_LOCK_MULTIPLIER       ; 5                         ; Untyped                       ;
+; SWITCH_OVER_ON_LOSSCLK        ; OFF                       ; Untyped                       ;
+; SWITCH_OVER_ON_GATED_LOCK     ; OFF                       ; Untyped                       ;
+; ENABLE_SWITCH_OVER_COUNTER    ; OFF                       ; Untyped                       ;
+; SKIP_VCO                      ; OFF                       ; Untyped                       ;
+; SWITCH_OVER_COUNTER           ; 0                         ; Untyped                       ;
+; SWITCH_OVER_TYPE              ; AUTO                      ; Untyped                       ;
+; FEEDBACK_SOURCE               ; EXTCLK0                   ; Untyped                       ;
+; BANDWIDTH                     ; 0                         ; Untyped                       ;
+; BANDWIDTH_TYPE                ; AUTO                      ; Untyped                       ;
+; SPREAD_FREQUENCY              ; 0                         ; Untyped                       ;
+; DOWN_SPREAD                   ; 0                         ; Untyped                       ;
+; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF                       ; Untyped                       ;
+; SELF_RESET_ON_LOSS_LOCK       ; ON                        ; Untyped                       ;
+; CLK9_MULTIPLY_BY              ; 0                         ; Untyped                       ;
+; CLK8_MULTIPLY_BY              ; 0                         ; Untyped                       ;
+; CLK7_MULTIPLY_BY              ; 0                         ; Untyped                       ;
+; CLK6_MULTIPLY_BY              ; 0                         ; Untyped                       ;
+; CLK5_MULTIPLY_BY              ; 1                         ; Untyped                       ;
+; CLK4_MULTIPLY_BY              ; 1                         ; Untyped                       ;
+; CLK3_MULTIPLY_BY              ; 1                         ; Untyped                       ;
+; CLK2_MULTIPLY_BY              ; 576                       ; Signed Integer                ;
+; CLK1_MULTIPLY_BY              ; 2304                      ; Signed Integer                ;
+; CLK0_MULTIPLY_BY              ; 2                         ; Signed Integer                ;
+; CLK9_DIVIDE_BY                ; 0                         ; Untyped                       ;
+; CLK8_DIVIDE_BY                ; 0                         ; Untyped                       ;
+; CLK7_DIVIDE_BY                ; 0                         ; Untyped                       ;
+; CLK6_DIVIDE_BY                ; 0                         ; Untyped                       ;
+; CLK5_DIVIDE_BY                ; 1                         ; Untyped                       ;
+; CLK4_DIVIDE_BY                ; 1                         ; Untyped                       ;
+; CLK3_DIVIDE_BY                ; 1                         ; Untyped                       ;
+; CLK2_DIVIDE_BY                ; 15625                     ; Signed Integer                ;
+; CLK1_DIVIDE_BY                ; 15625                     ; Signed Integer                ;
+; CLK0_DIVIDE_BY                ; 1                         ; Signed Integer                ;
+; CLK9_PHASE_SHIFT              ; 0                         ; Untyped                       ;
+; CLK8_PHASE_SHIFT              ; 0                         ; Untyped                       ;
+; CLK7_PHASE_SHIFT              ; 0                         ; Untyped                       ;
+; CLK6_PHASE_SHIFT              ; 0                         ; Untyped                       ;
+; CLK5_PHASE_SHIFT              ; 0                         ; Untyped                       ;
+; CLK4_PHASE_SHIFT              ; 0                         ; Untyped                       ;
+; CLK3_PHASE_SHIFT              ; 0                         ; Untyped                       ;
+; CLK2_PHASE_SHIFT              ; 0                         ; Untyped                       ;
+; CLK1_PHASE_SHIFT              ; 0                         ; Untyped                       ;
+; CLK0_PHASE_SHIFT              ; 0                         ; Untyped                       ;
+; CLK5_TIME_DELAY               ; 0                         ; Untyped                       ;
+; CLK4_TIME_DELAY               ; 0                         ; Untyped                       ;
+; CLK3_TIME_DELAY               ; 0                         ; Untyped                       ;
+; CLK2_TIME_DELAY               ; 0                         ; Untyped                       ;
+; CLK1_TIME_DELAY               ; 0                         ; Untyped                       ;
+; CLK0_TIME_DELAY               ; 0                         ; Untyped                       ;
+; CLK9_DUTY_CYCLE               ; 50                        ; Untyped                       ;
+; CLK8_DUTY_CYCLE               ; 50                        ; Untyped                       ;
+; CLK7_DUTY_CYCLE               ; 50                        ; Untyped                       ;
+; CLK6_DUTY_CYCLE               ; 50                        ; Untyped                       ;
+; CLK5_DUTY_CYCLE               ; 50                        ; Untyped                       ;
+; CLK4_DUTY_CYCLE               ; 50                        ; Untyped                       ;
+; CLK3_DUTY_CYCLE               ; 50                        ; Untyped                       ;
+; CLK2_DUTY_CYCLE               ; 50                        ; Signed Integer                ;
+; CLK1_DUTY_CYCLE               ; 50                        ; Signed Integer                ;
+; CLK0_DUTY_CYCLE               ; 50                        ; Signed Integer                ;
+; CLK9_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                       ;
+; CLK8_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                       ;
+; CLK7_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                       ;
+; CLK6_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                       ;
+; CLK5_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                       ;
+; CLK4_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                       ;
+; CLK3_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                       ;
+; CLK2_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                       ;
+; CLK1_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                       ;
+; CLK0_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                       ;
+; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                       ;
+; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                       ;
+; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                       ;
+; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                       ;
+; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                       ;
+; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                       ;
+; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                       ;
+; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                       ;
+; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                       ;
+; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                       ;
+; LOCK_WINDOW_UI                ;  0.05                     ; Untyped                       ;
+; LOCK_WINDOW_UI_BITS           ; UNUSED                    ; Untyped                       ;
+; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED                    ; Untyped                       ;
+; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED                    ; Untyped                       ;
+; DPA_MULTIPLY_BY               ; 0                         ; Untyped                       ;
+; DPA_DIVIDE_BY                 ; 1                         ; Untyped                       ;
+; DPA_DIVIDER                   ; 0                         ; Untyped                       ;
+; EXTCLK3_MULTIPLY_BY           ; 1                         ; Untyped                       ;
+; EXTCLK2_MULTIPLY_BY           ; 1                         ; Untyped                       ;
+; EXTCLK1_MULTIPLY_BY           ; 1                         ; Untyped                       ;
+; EXTCLK0_MULTIPLY_BY           ; 1                         ; Untyped                       ;
+; EXTCLK3_DIVIDE_BY             ; 1                         ; Untyped                       ;
+; EXTCLK2_DIVIDE_BY             ; 1                         ; Untyped                       ;
+; EXTCLK1_DIVIDE_BY             ; 1                         ; Untyped                       ;
+; EXTCLK0_DIVIDE_BY             ; 1                         ; Untyped                       ;
+; EXTCLK3_PHASE_SHIFT           ; 0                         ; Untyped                       ;
+; EXTCLK2_PHASE_SHIFT           ; 0                         ; Untyped                       ;
+; EXTCLK1_PHASE_SHIFT           ; 0                         ; Untyped                       ;
+; EXTCLK0_PHASE_SHIFT           ; 0                         ; Untyped                       ;
+; EXTCLK3_TIME_DELAY            ; 0                         ; Untyped                       ;
+; EXTCLK2_TIME_DELAY            ; 0                         ; Untyped                       ;
+; EXTCLK1_TIME_DELAY            ; 0                         ; Untyped                       ;
+; EXTCLK0_TIME_DELAY            ; 0                         ; Untyped                       ;
+; EXTCLK3_DUTY_CYCLE            ; 50                        ; Untyped                       ;
+; EXTCLK2_DUTY_CYCLE            ; 50                        ; Untyped                       ;
+; EXTCLK1_DUTY_CYCLE            ; 50                        ; Untyped                       ;
+; EXTCLK0_DUTY_CYCLE            ; 50                        ; Untyped                       ;
+; VCO_MULTIPLY_BY               ; 0                         ; Untyped                       ;
+; VCO_DIVIDE_BY                 ; 0                         ; Untyped                       ;
+; SCLKOUT0_PHASE_SHIFT          ; 0                         ; Untyped                       ;
+; SCLKOUT1_PHASE_SHIFT          ; 0                         ; Untyped                       ;
+; VCO_MIN                       ; 0                         ; Untyped                       ;
+; VCO_MAX                       ; 0                         ; Untyped                       ;
+; VCO_CENTER                    ; 0                         ; Untyped                       ;
+; PFD_MIN                       ; 0                         ; Untyped                       ;
+; PFD_MAX                       ; 0                         ; Untyped                       ;
+; M_INITIAL                     ; 0                         ; Untyped                       ;
+; M                             ; 0                         ; Untyped                       ;
+; N                             ; 1                         ; Untyped                       ;
+; M2                            ; 1                         ; Untyped                       ;
+; N2                            ; 1                         ; Untyped                       ;
+; SS                            ; 1                         ; Untyped                       ;
+; C0_HIGH                       ; 0                         ; Untyped                       ;
+; C1_HIGH                       ; 0                         ; Untyped                       ;
+; C2_HIGH                       ; 0                         ; Untyped                       ;
+; C3_HIGH                       ; 0                         ; Untyped                       ;
+; C4_HIGH                       ; 0                         ; Untyped                       ;
+; C5_HIGH                       ; 0                         ; Untyped                       ;
+; C6_HIGH                       ; 0                         ; Untyped                       ;
+; C7_HIGH                       ; 0                         ; Untyped                       ;
+; C8_HIGH                       ; 0                         ; Untyped                       ;
+; C9_HIGH                       ; 0                         ; Untyped                       ;
+; C0_LOW                        ; 0                         ; Untyped                       ;
+; C1_LOW                        ; 0                         ; Untyped                       ;
+; C2_LOW                        ; 0                         ; Untyped                       ;
+; C3_LOW                        ; 0                         ; Untyped                       ;
+; C4_LOW                        ; 0                         ; Untyped                       ;
+; C5_LOW                        ; 0                         ; Untyped                       ;
+; C6_LOW                        ; 0                         ; Untyped                       ;
+; C7_LOW                        ; 0                         ; Untyped                       ;
+; C8_LOW                        ; 0                         ; Untyped                       ;
+; C9_LOW                        ; 0                         ; Untyped                       ;
+; C0_INITIAL                    ; 0                         ; Untyped                       ;
+; C1_INITIAL                    ; 0                         ; Untyped                       ;
+; C2_INITIAL                    ; 0                         ; Untyped                       ;
+; C3_INITIAL                    ; 0                         ; Untyped                       ;
+; C4_INITIAL                    ; 0                         ; Untyped                       ;
+; C5_INITIAL                    ; 0                         ; Untyped                       ;
+; C6_INITIAL                    ; 0                         ; Untyped                       ;
+; C7_INITIAL                    ; 0                         ; Untyped                       ;
+; C8_INITIAL                    ; 0                         ; Untyped                       ;
+; C9_INITIAL                    ; 0                         ; Untyped                       ;
+; C0_MODE                       ; BYPASS                    ; Untyped                       ;
+; C1_MODE                       ; BYPASS                    ; Untyped                       ;
+; C2_MODE                       ; BYPASS                    ; Untyped                       ;
+; C3_MODE                       ; BYPASS                    ; Untyped                       ;
+; C4_MODE                       ; BYPASS                    ; Untyped                       ;
+; C5_MODE                       ; BYPASS                    ; Untyped                       ;
+; C6_MODE                       ; BYPASS                    ; Untyped                       ;
+; C7_MODE                       ; BYPASS                    ; Untyped                       ;
+; C8_MODE                       ; BYPASS                    ; Untyped                       ;
+; C9_MODE                       ; BYPASS                    ; Untyped                       ;
+; C0_PH                         ; 0                         ; Untyped                       ;
+; C1_PH                         ; 0                         ; Untyped                       ;
+; C2_PH                         ; 0                         ; Untyped                       ;
+; C3_PH                         ; 0                         ; Untyped                       ;
+; C4_PH                         ; 0                         ; Untyped                       ;
+; C5_PH                         ; 0                         ; Untyped                       ;
+; C6_PH                         ; 0                         ; Untyped                       ;
+; C7_PH                         ; 0                         ; Untyped                       ;
+; C8_PH                         ; 0                         ; Untyped                       ;
+; C9_PH                         ; 0                         ; Untyped                       ;
+; L0_HIGH                       ; 1                         ; Untyped                       ;
+; L1_HIGH                       ; 1                         ; Untyped                       ;
+; G0_HIGH                       ; 1                         ; Untyped                       ;
+; G1_HIGH                       ; 1                         ; Untyped                       ;
+; G2_HIGH                       ; 1                         ; Untyped                       ;
+; G3_HIGH                       ; 1                         ; Untyped                       ;
+; E0_HIGH                       ; 1                         ; Untyped                       ;
+; E1_HIGH                       ; 1                         ; Untyped                       ;
+; E2_HIGH                       ; 1                         ; Untyped                       ;
+; E3_HIGH                       ; 1                         ; Untyped                       ;
+; L0_LOW                        ; 1                         ; Untyped                       ;
+; L1_LOW                        ; 1                         ; Untyped                       ;
+; G0_LOW                        ; 1                         ; Untyped                       ;
+; G1_LOW                        ; 1                         ; Untyped                       ;
+; G2_LOW                        ; 1                         ; Untyped                       ;
+; G3_LOW                        ; 1                         ; Untyped                       ;
+; E0_LOW                        ; 1                         ; Untyped                       ;
+; E1_LOW                        ; 1                         ; Untyped                       ;
+; E2_LOW                        ; 1                         ; Untyped                       ;
+; E3_LOW                        ; 1                         ; Untyped                       ;
+; L0_INITIAL                    ; 1                         ; Untyped                       ;
+; L1_INITIAL                    ; 1                         ; Untyped                       ;
+; G0_INITIAL                    ; 1                         ; Untyped                       ;
+; G1_INITIAL                    ; 1                         ; Untyped                       ;
+; G2_INITIAL                    ; 1                         ; Untyped                       ;
+; G3_INITIAL                    ; 1                         ; Untyped                       ;
+; E0_INITIAL                    ; 1                         ; Untyped                       ;
+; E1_INITIAL                    ; 1                         ; Untyped                       ;
+; E2_INITIAL                    ; 1                         ; Untyped                       ;
+; E3_INITIAL                    ; 1                         ; Untyped                       ;
+; L0_MODE                       ; BYPASS                    ; Untyped                       ;
+; L1_MODE                       ; BYPASS                    ; Untyped                       ;
+; G0_MODE                       ; BYPASS                    ; Untyped                       ;
+; G1_MODE                       ; BYPASS                    ; Untyped                       ;
+; G2_MODE                       ; BYPASS                    ; Untyped                       ;
+; G3_MODE                       ; BYPASS                    ; Untyped                       ;
+; E0_MODE                       ; BYPASS                    ; Untyped                       ;
+; E1_MODE                       ; BYPASS                    ; Untyped                       ;
+; E2_MODE                       ; BYPASS                    ; Untyped                       ;
+; E3_MODE                       ; BYPASS                    ; Untyped                       ;
+; L0_PH                         ; 0                         ; Untyped                       ;
+; L1_PH                         ; 0                         ; Untyped                       ;
+; G0_PH                         ; 0                         ; Untyped                       ;
+; G1_PH                         ; 0                         ; Untyped                       ;
+; G2_PH                         ; 0                         ; Untyped                       ;
+; G3_PH                         ; 0                         ; Untyped                       ;
+; E0_PH                         ; 0                         ; Untyped                       ;
+; E1_PH                         ; 0                         ; Untyped                       ;
+; E2_PH                         ; 0                         ; Untyped                       ;
+; E3_PH                         ; 0                         ; Untyped                       ;
+; M_PH                          ; 0                         ; Untyped                       ;
+; C1_USE_CASC_IN                ; OFF                       ; Untyped                       ;
+; C2_USE_CASC_IN                ; OFF                       ; Untyped                       ;
+; C3_USE_CASC_IN                ; OFF                       ; Untyped                       ;
+; C4_USE_CASC_IN                ; OFF                       ; Untyped                       ;
+; C5_USE_CASC_IN                ; OFF                       ; Untyped                       ;
+; C6_USE_CASC_IN                ; OFF                       ; Untyped                       ;
+; C7_USE_CASC_IN                ; OFF                       ; Untyped                       ;
+; C8_USE_CASC_IN                ; OFF                       ; Untyped                       ;
+; C9_USE_CASC_IN                ; OFF                       ; Untyped                       ;
+; CLK0_COUNTER                  ; G0                        ; Untyped                       ;
+; CLK1_COUNTER                  ; G0                        ; Untyped                       ;
+; CLK2_COUNTER                  ; G0                        ; Untyped                       ;
+; CLK3_COUNTER                  ; G0                        ; Untyped                       ;
+; CLK4_COUNTER                  ; G0                        ; Untyped                       ;
+; CLK5_COUNTER                  ; G0                        ; Untyped                       ;
+; CLK6_COUNTER                  ; E0                        ; Untyped                       ;
+; CLK7_COUNTER                  ; E1                        ; Untyped                       ;
+; CLK8_COUNTER                  ; E2                        ; Untyped                       ;
+; CLK9_COUNTER                  ; E3                        ; Untyped                       ;
+; L0_TIME_DELAY                 ; 0                         ; Untyped                       ;
+; L1_TIME_DELAY                 ; 0                         ; Untyped                       ;
+; G0_TIME_DELAY                 ; 0                         ; Untyped                       ;
+; G1_TIME_DELAY                 ; 0                         ; Untyped                       ;
+; G2_TIME_DELAY                 ; 0                         ; Untyped                       ;
+; G3_TIME_DELAY                 ; 0                         ; Untyped                       ;
+; E0_TIME_DELAY                 ; 0                         ; Untyped                       ;
+; E1_TIME_DELAY                 ; 0                         ; Untyped                       ;
+; E2_TIME_DELAY                 ; 0                         ; Untyped                       ;
+; E3_TIME_DELAY                 ; 0                         ; Untyped                       ;
+; M_TIME_DELAY                  ; 0                         ; Untyped                       ;
+; N_TIME_DELAY                  ; 0                         ; Untyped                       ;
+; EXTCLK3_COUNTER               ; E3                        ; Untyped                       ;
+; EXTCLK2_COUNTER               ; E2                        ; Untyped                       ;
+; EXTCLK1_COUNTER               ; E1                        ; Untyped                       ;
+; EXTCLK0_COUNTER               ; E0                        ; Untyped                       ;
+; ENABLE0_COUNTER               ; L0                        ; Untyped                       ;
+; ENABLE1_COUNTER               ; L0                        ; Untyped                       ;
+; CHARGE_PUMP_CURRENT           ; 2                         ; Untyped                       ;
+; LOOP_FILTER_R                 ;  1.000000                 ; Untyped                       ;
+; LOOP_FILTER_C                 ; 5                         ; Untyped                       ;
+; CHARGE_PUMP_CURRENT_BITS      ; 9999                      ; Untyped                       ;
+; LOOP_FILTER_R_BITS            ; 9999                      ; Untyped                       ;
+; LOOP_FILTER_C_BITS            ; 9999                      ; Untyped                       ;
+; VCO_POST_SCALE                ; 0                         ; Untyped                       ;
+; CLK2_OUTPUT_FREQUENCY         ; 0                         ; Untyped                       ;
+; CLK1_OUTPUT_FREQUENCY         ; 0                         ; Untyped                       ;
+; CLK0_OUTPUT_FREQUENCY         ; 0                         ; Untyped                       ;
+; INTENDED_DEVICE_FAMILY        ; Cyclone IV E              ; Untyped                       ;
+; PORT_CLKENA0                  ; PORT_UNUSED               ; Untyped                       ;
+; PORT_CLKENA1                  ; PORT_UNUSED               ; Untyped                       ;
+; PORT_CLKENA2                  ; PORT_UNUSED               ; Untyped                       ;
+; PORT_CLKENA3                  ; PORT_UNUSED               ; Untyped                       ;
+; PORT_CLKENA4                  ; PORT_UNUSED               ; Untyped                       ;
+; PORT_CLKENA5                  ; PORT_UNUSED               ; Untyped                       ;
+; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY         ; Untyped                       ;
+; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY         ; Untyped                       ;
+; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY         ; Untyped                       ;
+; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY         ; Untyped                       ;
+; PORT_EXTCLK0                  ; PORT_UNUSED               ; Untyped                       ;
+; PORT_EXTCLK1                  ; PORT_UNUSED               ; Untyped                       ;
+; PORT_EXTCLK2                  ; PORT_UNUSED               ; Untyped                       ;
+; PORT_EXTCLK3                  ; PORT_UNUSED               ; Untyped                       ;
+; PORT_CLKBAD0                  ; PORT_UNUSED               ; Untyped                       ;
+; PORT_CLKBAD1                  ; PORT_UNUSED               ; Untyped                       ;
+; PORT_CLK0                     ; PORT_USED                 ; Untyped                       ;
+; PORT_CLK1                     ; PORT_USED                 ; Untyped                       ;
+; PORT_CLK2                     ; PORT_USED                 ; Untyped                       ;
+; PORT_CLK3                     ; PORT_UNUSED               ; Untyped                       ;
+; PORT_CLK4                     ; PORT_UNUSED               ; Untyped                       ;
+; PORT_CLK5                     ; PORT_UNUSED               ; Untyped                       ;
+; PORT_CLK6                     ; PORT_UNUSED               ; Untyped                       ;
+; PORT_CLK7                     ; PORT_UNUSED               ; Untyped                       ;
+; PORT_CLK8                     ; PORT_UNUSED               ; Untyped                       ;
+; PORT_CLK9                     ; PORT_UNUSED               ; Untyped                       ;
+; PORT_SCANDATA                 ; PORT_UNUSED               ; Untyped                       ;
+; PORT_SCANDATAOUT              ; PORT_UNUSED               ; Untyped                       ;
+; PORT_SCANDONE                 ; PORT_UNUSED               ; Untyped                       ;
+; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY         ; Untyped                       ;
+; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY         ; Untyped                       ;
+; PORT_ACTIVECLOCK              ; PORT_UNUSED               ; Untyped                       ;
+; PORT_CLKLOSS                  ; PORT_UNUSED               ; Untyped                       ;
+; PORT_INCLK1                   ; PORT_UNUSED               ; Untyped                       ;
+; PORT_INCLK0                   ; PORT_USED                 ; Untyped                       ;
+; PORT_FBIN                     ; PORT_UNUSED               ; Untyped                       ;
+; PORT_PLLENA                   ; PORT_UNUSED               ; Untyped                       ;
+; PORT_CLKSWITCH                ; PORT_UNUSED               ; Untyped                       ;
+; PORT_ARESET                   ; PORT_UNUSED               ; Untyped                       ;
+; PORT_PFDENA                   ; PORT_UNUSED               ; Untyped                       ;
+; PORT_SCANCLK                  ; PORT_UNUSED               ; Untyped                       ;
+; PORT_SCANACLR                 ; PORT_UNUSED               ; Untyped                       ;
+; PORT_SCANREAD                 ; PORT_UNUSED               ; Untyped                       ;
+; PORT_SCANWRITE                ; PORT_UNUSED               ; Untyped                       ;
+; PORT_ENABLE0                  ; PORT_CONNECTIVITY         ; Untyped                       ;
+; PORT_ENABLE1                  ; PORT_CONNECTIVITY         ; Untyped                       ;
+; PORT_LOCKED                   ; PORT_USED                 ; Untyped                       ;
+; PORT_CONFIGUPDATE             ; PORT_UNUSED               ; Untyped                       ;
+; PORT_FBOUT                    ; PORT_CONNECTIVITY         ; Untyped                       ;
+; PORT_PHASEDONE                ; PORT_UNUSED               ; Untyped                       ;
+; PORT_PHASESTEP                ; PORT_UNUSED               ; Untyped                       ;
+; PORT_PHASEUPDOWN              ; PORT_UNUSED               ; Untyped                       ;
+; PORT_SCANCLKENA               ; PORT_UNUSED               ; Untyped                       ;
+; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED               ; Untyped                       ;
+; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY         ; Untyped                       ;
+; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY         ; Untyped                       ;
+; M_TEST_SOURCE                 ; 5                         ; Untyped                       ;
+; C0_TEST_SOURCE                ; 5                         ; Untyped                       ;
+; C1_TEST_SOURCE                ; 5                         ; Untyped                       ;
+; C2_TEST_SOURCE                ; 5                         ; Untyped                       ;
+; C3_TEST_SOURCE                ; 5                         ; Untyped                       ;
+; C4_TEST_SOURCE                ; 5                         ; Untyped                       ;
+; C5_TEST_SOURCE                ; 5                         ; Untyped                       ;
+; C6_TEST_SOURCE                ; 5                         ; Untyped                       ;
+; C7_TEST_SOURCE                ; 5                         ; Untyped                       ;
+; C8_TEST_SOURCE                ; 5                         ; Untyped                       ;
+; C9_TEST_SOURCE                ; 5                         ; Untyped                       ;
+; CBXI_PARAMETER                ; pll_sys_altpll            ; Untyped                       ;
+; VCO_FREQUENCY_CONTROL         ; AUTO                      ; Untyped                       ;
+; VCO_PHASE_SHIFT_STEP          ; 0                         ; Untyped                       ;
+; WIDTH_CLOCK                   ; 5                         ; Signed Integer                ;
+; WIDTH_PHASECOUNTERSELECT      ; 4                         ; Untyped                       ;
+; USING_FBMIMICBIDIR_PORT       ; OFF                       ; Untyped                       ;
+; DEVICE_FAMILY                 ; Cyclone IV E              ; Untyped                       ;
+; SCAN_CHAIN_MIF_FILE           ; UNUSED                    ; Untyped                       ;
+; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF                       ; Untyped                       ;
+; AUTO_CARRY_CHAINS             ; ON                        ; AUTO_CARRY                    ;
+; IGNORE_CARRY_BUFFERS          ; OFF                       ; IGNORE_CARRY                  ;
+; AUTO_CASCADE_CHAINS           ; ON                        ; AUTO_CASCADE                  ;
+; IGNORE_CASCADE_BUFFERS        ; OFF                       ; IGNORE_CASCADE                ;
++-------------------------------+---------------------------+-------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: picorv32:cpu                 ;
++----------------------+----------------------------------+-----------------+
+; Parameter Name       ; Value                            ; Type            ;
++----------------------+----------------------------------+-----------------+
+; ENABLE_COUNTERS      ; 0                                ; Signed Integer  ;
+; ENABLE_COUNTERS64    ; 0                                ; Signed Integer  ;
+; ENABLE_REGS_16_31    ; 1                                ; Unsigned Binary ;
+; ENABLE_REGS_DUALPORT ; 1                                ; Unsigned Binary ;
+; LATCHED_MEM_RDATA    ; 0                                ; Unsigned Binary ;
+; TWO_STAGE_SHIFT      ; 1                                ; Unsigned Binary ;
+; BARREL_SHIFTER       ; 1                                ; Signed Integer  ;
+; TWO_CYCLE_COMPARE    ; 0                                ; Signed Integer  ;
+; TWO_CYCLE_ALU        ; 0                                ; Signed Integer  ;
+; COMPRESSED_ISA       ; 0                                ; Unsigned Binary ;
+; CATCH_MISALIGN       ; 1                                ; Unsigned Binary ;
+; CATCH_ILLINSN        ; 1                                ; Unsigned Binary ;
+; ENABLE_PCPI          ; 0                                ; Signed Integer  ;
+; ENABLE_MUL           ; 0                                ; Unsigned Binary ;
+; ENABLE_FAST_MUL      ; 1                                ; Signed Integer  ;
+; ENABLE_DIV           ; 1                                ; Signed Integer  ;
+; ENABLE_IRQ           ; 0                                ; Unsigned Binary ;
+; ENABLE_IRQ_QREGS     ; 1                                ; Unsigned Binary ;
+; ENABLE_IRQ_TIMER     ; 1                                ; Unsigned Binary ;
+; ENABLE_TRACE         ; 0                                ; Unsigned Binary ;
+; REGS_INIT_ZERO       ; 0                                ; Unsigned Binary ;
+; MASKED_IRQ           ; 00000000000000000000000000000000 ; Unsigned Binary ;
+; LATCHED_IRQ          ; 11111111111111111111111111111111 ; Unsigned Binary ;
+; PROGADDR_RESET       ; 00000000000000000000000000000000 ; Unsigned Binary ;
+; PROGADDR_IRQ         ; 00000000000000000000000000010000 ; Unsigned Binary ;
+; STACKADDR            ; 11111111111111111111111111111111 ; Unsigned Binary ;
++----------------------+----------------------------------+-----------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul ;
++----------------+-------+------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                             ;
++----------------+-------+------------------------------------------------------------------+
+; EXTRA_MUL_FFS  ; 0     ; Signed Integer                                                   ;
+; EXTRA_INSN_FFS ; 0     ; Signed Integer                                                   ;
+; MUL_CLKGATE    ; 0     ; Signed Integer                                                   ;
++----------------+-------+------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: Memory:mem|altsyncram:memory_1_symbol0_rtl_0 ;
++------------------------------------+--------------------------------------+-------------------+
+; Parameter Name                     ; Value                                ; Type              ;
++------------------------------------+--------------------------------------+-------------------+
+; BYTE_SIZE_BLOCK                    ; 8                                    ; Untyped           ;
+; AUTO_CARRY_CHAINS                  ; ON                                   ; AUTO_CARRY        ;
+; IGNORE_CARRY_BUFFERS               ; OFF                                  ; IGNORE_CARRY      ;
+; AUTO_CASCADE_CHAINS                ; ON                                   ; AUTO_CASCADE      ;
+; IGNORE_CASCADE_BUFFERS             ; OFF                                  ; IGNORE_CASCADE    ;
+; WIDTH_BYTEENA                      ; 1                                    ; Untyped           ;
+; OPERATION_MODE                     ; DUAL_PORT                            ; Untyped           ;
+; WIDTH_A                            ; 8                                    ; Untyped           ;
+; WIDTHAD_A                          ; 14                                   ; Untyped           ;
+; NUMWORDS_A                         ; 10241                                ; Untyped           ;
+; OUTDATA_REG_A                      ; UNREGISTERED                         ; Untyped           ;
+; ADDRESS_ACLR_A                     ; NONE                                 ; Untyped           ;
+; OUTDATA_ACLR_A                     ; NONE                                 ; Untyped           ;
+; WRCONTROL_ACLR_A                   ; NONE                                 ; Untyped           ;
+; INDATA_ACLR_A                      ; NONE                                 ; Untyped           ;
+; BYTEENA_ACLR_A                     ; NONE                                 ; Untyped           ;
+; WIDTH_B                            ; 8                                    ; Untyped           ;
+; WIDTHAD_B                          ; 14                                   ; Untyped           ;
+; NUMWORDS_B                         ; 10241                                ; Untyped           ;
+; INDATA_REG_B                       ; CLOCK1                               ; Untyped           ;
+; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                               ; Untyped           ;
+; RDCONTROL_REG_B                    ; CLOCK1                               ; Untyped           ;
+; ADDRESS_REG_B                      ; CLOCK0                               ; Untyped           ;
+; OUTDATA_REG_B                      ; UNREGISTERED                         ; Untyped           ;
+; BYTEENA_REG_B                      ; CLOCK1                               ; Untyped           ;
+; INDATA_ACLR_B                      ; NONE                                 ; Untyped           ;
+; WRCONTROL_ACLR_B                   ; NONE                                 ; Untyped           ;
+; ADDRESS_ACLR_B                     ; NONE                                 ; Untyped           ;
+; OUTDATA_ACLR_B                     ; NONE                                 ; Untyped           ;
+; RDCONTROL_ACLR_B                   ; NONE                                 ; Untyped           ;
+; BYTEENA_ACLR_B                     ; NONE                                 ; Untyped           ;
+; WIDTH_BYTEENA_A                    ; 1                                    ; Untyped           ;
+; WIDTH_BYTEENA_B                    ; 1                                    ; Untyped           ;
+; RAM_BLOCK_TYPE                     ; AUTO                                 ; Untyped           ;
+; BYTE_SIZE                          ; 8                                    ; Untyped           ;
+; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                            ; Untyped           ;
+; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ                 ; Untyped           ;
+; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ                 ; Untyped           ;
+; INIT_FILE                          ; db/xoro.ram0_Memory_a0c6519c.hdl.mif ; Untyped           ;
+; INIT_FILE_LAYOUT                   ; PORT_A                               ; Untyped           ;
+; MAXIMUM_DEPTH                      ; 0                                    ; Untyped           ;
+; CLOCK_ENABLE_INPUT_A               ; NORMAL                               ; Untyped           ;
+; CLOCK_ENABLE_INPUT_B               ; NORMAL                               ; Untyped           ;
+; CLOCK_ENABLE_OUTPUT_A              ; NORMAL                               ; Untyped           ;
+; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                               ; Untyped           ;
+; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN                      ; Untyped           ;
+; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN                      ; Untyped           ;
+; ENABLE_ECC                         ; FALSE                                ; Untyped           ;
+; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                                ; Untyped           ;
+; WIDTH_ECCSTATUS                    ; 3                                    ; Untyped           ;
+; DEVICE_FAMILY                      ; Cyclone IV E                         ; Untyped           ;
+; CBXI_PARAMETER                     ; altsyncram_bdi1                      ; Untyped           ;
++------------------------------------+--------------------------------------+-------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: Memory:mem|altsyncram:memory_1_symbol1_rtl_0 ;
++------------------------------------+--------------------------------------+-------------------+
+; Parameter Name                     ; Value                                ; Type              ;
++------------------------------------+--------------------------------------+-------------------+
+; BYTE_SIZE_BLOCK                    ; 8                                    ; Untyped           ;
+; AUTO_CARRY_CHAINS                  ; ON                                   ; AUTO_CARRY        ;
+; IGNORE_CARRY_BUFFERS               ; OFF                                  ; IGNORE_CARRY      ;
+; AUTO_CASCADE_CHAINS                ; ON                                   ; AUTO_CASCADE      ;
+; IGNORE_CASCADE_BUFFERS             ; OFF                                  ; IGNORE_CASCADE    ;
+; WIDTH_BYTEENA                      ; 1                                    ; Untyped           ;
+; OPERATION_MODE                     ; DUAL_PORT                            ; Untyped           ;
+; WIDTH_A                            ; 8                                    ; Untyped           ;
+; WIDTHAD_A                          ; 14                                   ; Untyped           ;
+; NUMWORDS_A                         ; 10241                                ; Untyped           ;
+; OUTDATA_REG_A                      ; UNREGISTERED                         ; Untyped           ;
+; ADDRESS_ACLR_A                     ; NONE                                 ; Untyped           ;
+; OUTDATA_ACLR_A                     ; NONE                                 ; Untyped           ;
+; WRCONTROL_ACLR_A                   ; NONE                                 ; Untyped           ;
+; INDATA_ACLR_A                      ; NONE                                 ; Untyped           ;
+; BYTEENA_ACLR_A                     ; NONE                                 ; Untyped           ;
+; WIDTH_B                            ; 8                                    ; Untyped           ;
+; WIDTHAD_B                          ; 14                                   ; Untyped           ;
+; NUMWORDS_B                         ; 10241                                ; Untyped           ;
+; INDATA_REG_B                       ; CLOCK1                               ; Untyped           ;
+; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                               ; Untyped           ;
+; RDCONTROL_REG_B                    ; CLOCK1                               ; Untyped           ;
+; ADDRESS_REG_B                      ; CLOCK0                               ; Untyped           ;
+; OUTDATA_REG_B                      ; UNREGISTERED                         ; Untyped           ;
+; BYTEENA_REG_B                      ; CLOCK1                               ; Untyped           ;
+; INDATA_ACLR_B                      ; NONE                                 ; Untyped           ;
+; WRCONTROL_ACLR_B                   ; NONE                                 ; Untyped           ;
+; ADDRESS_ACLR_B                     ; NONE                                 ; Untyped           ;
+; OUTDATA_ACLR_B                     ; NONE                                 ; Untyped           ;
+; RDCONTROL_ACLR_B                   ; NONE                                 ; Untyped           ;
+; BYTEENA_ACLR_B                     ; NONE                                 ; Untyped           ;
+; WIDTH_BYTEENA_A                    ; 1                                    ; Untyped           ;
+; WIDTH_BYTEENA_B                    ; 1                                    ; Untyped           ;
+; RAM_BLOCK_TYPE                     ; AUTO                                 ; Untyped           ;
+; BYTE_SIZE                          ; 8                                    ; Untyped           ;
+; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                            ; Untyped           ;
+; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ                 ; Untyped           ;
+; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ                 ; Untyped           ;
+; INIT_FILE                          ; db/xoro.ram1_Memory_a0c6519c.hdl.mif ; Untyped           ;
+; INIT_FILE_LAYOUT                   ; PORT_A                               ; Untyped           ;
+; MAXIMUM_DEPTH                      ; 0                                    ; Untyped           ;
+; CLOCK_ENABLE_INPUT_A               ; NORMAL                               ; Untyped           ;
+; CLOCK_ENABLE_INPUT_B               ; NORMAL                               ; Untyped           ;
+; CLOCK_ENABLE_OUTPUT_A              ; NORMAL                               ; Untyped           ;
+; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                               ; Untyped           ;
+; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN                      ; Untyped           ;
+; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN                      ; Untyped           ;
+; ENABLE_ECC                         ; FALSE                                ; Untyped           ;
+; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                                ; Untyped           ;
+; WIDTH_ECCSTATUS                    ; 3                                    ; Untyped           ;
+; DEVICE_FAMILY                      ; Cyclone IV E                         ; Untyped           ;
+; CBXI_PARAMETER                     ; altsyncram_cdi1                      ; Untyped           ;
++------------------------------------+--------------------------------------+-------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: picorv32:cpu|altsyncram:cpuregs_rtl_0 ;
++------------------------------------+----------------------+----------------------------+
+; Parameter Name                     ; Value                ; Type                       ;
++------------------------------------+----------------------+----------------------------+
+; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                    ;
+; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                 ;
+; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY               ;
+; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE               ;
+; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE             ;
+; WIDTH_BYTEENA                      ; 1                    ; Untyped                    ;
+; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                    ;
+; WIDTH_A                            ; 32                   ; Untyped                    ;
+; WIDTHAD_A                          ; 5                    ; Untyped                    ;
+; NUMWORDS_A                         ; 32                   ; Untyped                    ;
+; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                    ;
+; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                    ;
+; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                    ;
+; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                    ;
+; INDATA_ACLR_A                      ; NONE                 ; Untyped                    ;
+; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                    ;
+; WIDTH_B                            ; 32                   ; Untyped                    ;
+; WIDTHAD_B                          ; 5                    ; Untyped                    ;
+; NUMWORDS_B                         ; 32                   ; Untyped                    ;
+; INDATA_REG_B                       ; CLOCK1               ; Untyped                    ;
+; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                    ;
+; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                    ;
+; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                    ;
+; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                    ;
+; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                    ;
+; INDATA_ACLR_B                      ; NONE                 ; Untyped                    ;
+; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                    ;
+; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                    ;
+; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                    ;
+; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                    ;
+; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                    ;
+; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                    ;
+; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                    ;
+; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                    ;
+; BYTE_SIZE                          ; 8                    ; Untyped                    ;
+; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                    ;
+; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                    ;
+; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                    ;
+; INIT_FILE                          ; UNUSED               ; Untyped                    ;
+; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                    ;
+; MAXIMUM_DEPTH                      ; 0                    ; Untyped                    ;
+; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                    ;
+; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                    ;
+; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                    ;
+; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                    ;
+; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                    ;
+; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                    ;
+; ENABLE_ECC                         ; FALSE                ; Untyped                    ;
+; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped                    ;
+; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                    ;
+; DEVICE_FAMILY                      ; Cyclone IV E         ; Untyped                    ;
+; CBXI_PARAMETER                     ; altsyncram_trd1      ; Untyped                    ;
++------------------------------------+----------------------+----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: picorv32:cpu|altsyncram:cpuregs_rtl_1 ;
++------------------------------------+----------------------+----------------------------+
+; Parameter Name                     ; Value                ; Type                       ;
++------------------------------------+----------------------+----------------------------+
+; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                    ;
+; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                 ;
+; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY               ;
+; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE               ;
+; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE             ;
+; WIDTH_BYTEENA                      ; 1                    ; Untyped                    ;
+; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                    ;
+; WIDTH_A                            ; 32                   ; Untyped                    ;
+; WIDTHAD_A                          ; 5                    ; Untyped                    ;
+; NUMWORDS_A                         ; 32                   ; Untyped                    ;
+; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                    ;
+; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                    ;
+; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                    ;
+; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                    ;
+; INDATA_ACLR_A                      ; NONE                 ; Untyped                    ;
+; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                    ;
+; WIDTH_B                            ; 32                   ; Untyped                    ;
+; WIDTHAD_B                          ; 5                    ; Untyped                    ;
+; NUMWORDS_B                         ; 32                   ; Untyped                    ;
+; INDATA_REG_B                       ; CLOCK1               ; Untyped                    ;
+; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                    ;
+; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                    ;
+; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                    ;
+; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                    ;
+; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                    ;
+; INDATA_ACLR_B                      ; NONE                 ; Untyped                    ;
+; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                    ;
+; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                    ;
+; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                    ;
+; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                    ;
+; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                    ;
+; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                    ;
+; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                    ;
+; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                    ;
+; BYTE_SIZE                          ; 8                    ; Untyped                    ;
+; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                    ;
+; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                    ;
+; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                    ;
+; INIT_FILE                          ; UNUSED               ; Untyped                    ;
+; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                    ;
+; MAXIMUM_DEPTH                      ; 0                    ; Untyped                    ;
+; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                    ;
+; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                    ;
+; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                    ;
+; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                    ;
+; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                    ;
+; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                    ;
+; ENABLE_ECC                         ; FALSE                ; Untyped                    ;
+; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped                    ;
+; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                    ;
+; DEVICE_FAMILY                      ; Cyclone IV E         ; Untyped                    ;
+; CBXI_PARAMETER                     ; altsyncram_trd1      ; Untyped                    ;
++------------------------------------+----------------------+----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: Memory:mem|altsyncram:memory_1_symbol3_rtl_0 ;
++------------------------------------+--------------------------------------+-------------------+
+; Parameter Name                     ; Value                                ; Type              ;
++------------------------------------+--------------------------------------+-------------------+
+; BYTE_SIZE_BLOCK                    ; 8                                    ; Untyped           ;
+; AUTO_CARRY_CHAINS                  ; ON                                   ; AUTO_CARRY        ;
+; IGNORE_CARRY_BUFFERS               ; OFF                                  ; IGNORE_CARRY      ;
+; AUTO_CASCADE_CHAINS                ; ON                                   ; AUTO_CASCADE      ;
+; IGNORE_CASCADE_BUFFERS             ; OFF                                  ; IGNORE_CASCADE    ;
+; WIDTH_BYTEENA                      ; 1                                    ; Untyped           ;
+; OPERATION_MODE                     ; DUAL_PORT                            ; Untyped           ;
+; WIDTH_A                            ; 8                                    ; Untyped           ;
+; WIDTHAD_A                          ; 14                                   ; Untyped           ;
+; NUMWORDS_A                         ; 10241                                ; Untyped           ;
+; OUTDATA_REG_A                      ; UNREGISTERED                         ; Untyped           ;
+; ADDRESS_ACLR_A                     ; NONE                                 ; Untyped           ;
+; OUTDATA_ACLR_A                     ; NONE                                 ; Untyped           ;
+; WRCONTROL_ACLR_A                   ; NONE                                 ; Untyped           ;
+; INDATA_ACLR_A                      ; NONE                                 ; Untyped           ;
+; BYTEENA_ACLR_A                     ; NONE                                 ; Untyped           ;
+; WIDTH_B                            ; 8                                    ; Untyped           ;
+; WIDTHAD_B                          ; 14                                   ; Untyped           ;
+; NUMWORDS_B                         ; 10241                                ; Untyped           ;
+; INDATA_REG_B                       ; CLOCK1                               ; Untyped           ;
+; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                               ; Untyped           ;
+; RDCONTROL_REG_B                    ; CLOCK1                               ; Untyped           ;
+; ADDRESS_REG_B                      ; CLOCK0                               ; Untyped           ;
+; OUTDATA_REG_B                      ; UNREGISTERED                         ; Untyped           ;
+; BYTEENA_REG_B                      ; CLOCK1                               ; Untyped           ;
+; INDATA_ACLR_B                      ; NONE                                 ; Untyped           ;
+; WRCONTROL_ACLR_B                   ; NONE                                 ; Untyped           ;
+; ADDRESS_ACLR_B                     ; NONE                                 ; Untyped           ;
+; OUTDATA_ACLR_B                     ; NONE                                 ; Untyped           ;
+; RDCONTROL_ACLR_B                   ; NONE                                 ; Untyped           ;
+; BYTEENA_ACLR_B                     ; NONE                                 ; Untyped           ;
+; WIDTH_BYTEENA_A                    ; 1                                    ; Untyped           ;
+; WIDTH_BYTEENA_B                    ; 1                                    ; Untyped           ;
+; RAM_BLOCK_TYPE                     ; AUTO                                 ; Untyped           ;
+; BYTE_SIZE                          ; 8                                    ; Untyped           ;
+; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                            ; Untyped           ;
+; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ                 ; Untyped           ;
+; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ                 ; Untyped           ;
+; INIT_FILE                          ; db/xoro.ram3_Memory_a0c6519c.hdl.mif ; Untyped           ;
+; INIT_FILE_LAYOUT                   ; PORT_A                               ; Untyped           ;
+; MAXIMUM_DEPTH                      ; 0                                    ; Untyped           ;
+; CLOCK_ENABLE_INPUT_A               ; NORMAL                               ; Untyped           ;
+; CLOCK_ENABLE_INPUT_B               ; NORMAL                               ; Untyped           ;
+; CLOCK_ENABLE_OUTPUT_A              ; NORMAL                               ; Untyped           ;
+; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                               ; Untyped           ;
+; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN                      ; Untyped           ;
+; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN                      ; Untyped           ;
+; ENABLE_ECC                         ; FALSE                                ; Untyped           ;
+; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                                ; Untyped           ;
+; WIDTH_ECCSTATUS                    ; 3                                    ; Untyped           ;
+; DEVICE_FAMILY                      ; Cyclone IV E                         ; Untyped           ;
+; CBXI_PARAMETER                     ; altsyncram_edi1                      ; Untyped           ;
++------------------------------------+--------------------------------------+-------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: Memory:mem|altsyncram:memory_1_symbol2_rtl_0 ;
++------------------------------------+--------------------------------------+-------------------+
+; Parameter Name                     ; Value                                ; Type              ;
++------------------------------------+--------------------------------------+-------------------+
+; BYTE_SIZE_BLOCK                    ; 8                                    ; Untyped           ;
+; AUTO_CARRY_CHAINS                  ; ON                                   ; AUTO_CARRY        ;
+; IGNORE_CARRY_BUFFERS               ; OFF                                  ; IGNORE_CARRY      ;
+; AUTO_CASCADE_CHAINS                ; ON                                   ; AUTO_CASCADE      ;
+; IGNORE_CASCADE_BUFFERS             ; OFF                                  ; IGNORE_CASCADE    ;
+; WIDTH_BYTEENA                      ; 1                                    ; Untyped           ;
+; OPERATION_MODE                     ; DUAL_PORT                            ; Untyped           ;
+; WIDTH_A                            ; 8                                    ; Untyped           ;
+; WIDTHAD_A                          ; 14                                   ; Untyped           ;
+; NUMWORDS_A                         ; 10241                                ; Untyped           ;
+; OUTDATA_REG_A                      ; UNREGISTERED                         ; Untyped           ;
+; ADDRESS_ACLR_A                     ; NONE                                 ; Untyped           ;
+; OUTDATA_ACLR_A                     ; NONE                                 ; Untyped           ;
+; WRCONTROL_ACLR_A                   ; NONE                                 ; Untyped           ;
+; INDATA_ACLR_A                      ; NONE                                 ; Untyped           ;
+; BYTEENA_ACLR_A                     ; NONE                                 ; Untyped           ;
+; WIDTH_B                            ; 8                                    ; Untyped           ;
+; WIDTHAD_B                          ; 14                                   ; Untyped           ;
+; NUMWORDS_B                         ; 10241                                ; Untyped           ;
+; INDATA_REG_B                       ; CLOCK1                               ; Untyped           ;
+; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                               ; Untyped           ;
+; RDCONTROL_REG_B                    ; CLOCK1                               ; Untyped           ;
+; ADDRESS_REG_B                      ; CLOCK0                               ; Untyped           ;
+; OUTDATA_REG_B                      ; UNREGISTERED                         ; Untyped           ;
+; BYTEENA_REG_B                      ; CLOCK1                               ; Untyped           ;
+; INDATA_ACLR_B                      ; NONE                                 ; Untyped           ;
+; WRCONTROL_ACLR_B                   ; NONE                                 ; Untyped           ;
+; ADDRESS_ACLR_B                     ; NONE                                 ; Untyped           ;
+; OUTDATA_ACLR_B                     ; NONE                                 ; Untyped           ;
+; RDCONTROL_ACLR_B                   ; NONE                                 ; Untyped           ;
+; BYTEENA_ACLR_B                     ; NONE                                 ; Untyped           ;
+; WIDTH_BYTEENA_A                    ; 1                                    ; Untyped           ;
+; WIDTH_BYTEENA_B                    ; 1                                    ; Untyped           ;
+; RAM_BLOCK_TYPE                     ; AUTO                                 ; Untyped           ;
+; BYTE_SIZE                          ; 8                                    ; Untyped           ;
+; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                            ; Untyped           ;
+; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ                 ; Untyped           ;
+; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ                 ; Untyped           ;
+; INIT_FILE                          ; db/xoro.ram2_Memory_a0c6519c.hdl.mif ; Untyped           ;
+; INIT_FILE_LAYOUT                   ; PORT_A                               ; Untyped           ;
+; MAXIMUM_DEPTH                      ; 0                                    ; Untyped           ;
+; CLOCK_ENABLE_INPUT_A               ; NORMAL                               ; Untyped           ;
+; CLOCK_ENABLE_INPUT_B               ; NORMAL                               ; Untyped           ;
+; CLOCK_ENABLE_OUTPUT_A              ; NORMAL                               ; Untyped           ;
+; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                               ; Untyped           ;
+; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN                      ; Untyped           ;
+; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN                      ; Untyped           ;
+; ENABLE_ECC                         ; FALSE                                ; Untyped           ;
+; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                                ; Untyped           ;
+; WIDTH_ECCSTATUS                    ; 3                                    ; Untyped           ;
+; DEVICE_FAMILY                      ; Cyclone IV E                         ; Untyped           ;
+; CBXI_PARAMETER                     ; altsyncram_ddi1                      ; Untyped           ;
++------------------------------------+--------------------------------------+-------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: AsyncReceiver:uartRx|Fifo:fifo_1|altsyncram:mem_rtl_0 ;
++------------------------------------+----------------------+--------------------------------------------+
+; Parameter Name                     ; Value                ; Type                                       ;
++------------------------------------+----------------------+--------------------------------------------+
+; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                    ;
+; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                 ;
+; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                               ;
+; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                               ;
+; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                             ;
+; WIDTH_BYTEENA                      ; 1                    ; Untyped                                    ;
+; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                    ;
+; WIDTH_A                            ; 8                    ; Untyped                                    ;
+; WIDTHAD_A                          ; 5                    ; Untyped                                    ;
+; NUMWORDS_A                         ; 32                   ; Untyped                                    ;
+; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                    ;
+; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                    ;
+; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                    ;
+; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                    ;
+; INDATA_ACLR_A                      ; NONE                 ; Untyped                                    ;
+; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                    ;
+; WIDTH_B                            ; 8                    ; Untyped                                    ;
+; WIDTHAD_B                          ; 5                    ; Untyped                                    ;
+; NUMWORDS_B                         ; 32                   ; Untyped                                    ;
+; INDATA_REG_B                       ; CLOCK1               ; Untyped                                    ;
+; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                    ;
+; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                                    ;
+; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                    ;
+; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                    ;
+; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                    ;
+; INDATA_ACLR_B                      ; NONE                 ; Untyped                                    ;
+; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                    ;
+; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                    ;
+; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                    ;
+; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                    ;
+; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                    ;
+; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                    ;
+; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                    ;
+; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                    ;
+; BYTE_SIZE                          ; 8                    ; Untyped                                    ;
+; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                                    ;
+; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                    ;
+; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                    ;
+; INIT_FILE                          ; UNUSED               ; Untyped                                    ;
+; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                    ;
+; MAXIMUM_DEPTH                      ; 0                    ; Untyped                                    ;
+; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                    ;
+; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                    ;
+; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                    ;
+; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                    ;
+; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                    ;
+; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                    ;
+; ENABLE_ECC                         ; FALSE                ; Untyped                                    ;
+; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped                                    ;
+; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                    ;
+; DEVICE_FAMILY                      ; Cyclone IV E         ; Untyped                                    ;
+; CBXI_PARAMETER                     ; altsyncram_s9c1      ; Untyped                                    ;
++------------------------------------+----------------------+--------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0 ;
++------------------------------------------------+--------------+----------------------------------------------+
+; Parameter Name                                 ; Value        ; Type                                         ;
++------------------------------------------------+--------------+----------------------------------------------+
+; AUTO_CARRY_CHAINS                              ; ON           ; AUTO_CARRY                                   ;
+; IGNORE_CARRY_BUFFERS                           ; OFF          ; IGNORE_CARRY                                 ;
+; AUTO_CASCADE_CHAINS                            ; ON           ; AUTO_CASCADE                                 ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF          ; IGNORE_CASCADE                               ;
+; LPM_WIDTHA                                     ; 33           ; Untyped                                      ;
+; LPM_WIDTHB                                     ; 33           ; Untyped                                      ;
+; LPM_WIDTHP                                     ; 66           ; Untyped                                      ;
+; LPM_WIDTHR                                     ; 66           ; Untyped                                      ;
+; LPM_WIDTHS                                     ; 1            ; Untyped                                      ;
+; LPM_REPRESENTATION                             ; SIGNED       ; Untyped                                      ;
+; LPM_PIPELINE                                   ; 0            ; Untyped                                      ;
+; LATENCY                                        ; 0            ; Untyped                                      ;
+; INPUT_A_IS_CONSTANT                            ; NO           ; Untyped                                      ;
+; INPUT_B_IS_CONSTANT                            ; NO           ; Untyped                                      ;
+; USE_EAB                                        ; OFF          ; Untyped                                      ;
+; MAXIMIZE_SPEED                                 ; 5            ; Untyped                                      ;
+; DEVICE_FAMILY                                  ; Cyclone IV E ; Untyped                                      ;
+; CARRY_CHAIN                                    ; MANUAL       ; Untyped                                      ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT          ; TECH_MAPPER_APEX20K                          ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO         ; Untyped                                      ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0            ; Untyped                                      ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0            ; Untyped                                      ;
+; CBXI_PARAMETER                                 ; mult_86t     ; Untyped                                      ;
+; INPUT_A_FIXED_VALUE                            ; Bx           ; Untyped                                      ;
+; INPUT_B_FIXED_VALUE                            ; Bx           ; Untyped                                      ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF          ; Untyped                                      ;
++------------------------------------------------+--------------+----------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------+
+; altpll Parameter Settings by Entity Instance                                 ;
++-------------------------------+----------------------------------------------+
+; Name                          ; Value                                        ;
++-------------------------------+----------------------------------------------+
+; Number of entity instances    ; 1                                            ;
+; Entity Instance               ; pll_sys:pll_sys_inst|altpll:altpll_component ;
+;     -- OPERATION_MODE         ; NORMAL                                       ;
+;     -- PLL_TYPE               ; AUTO                                         ;
+;     -- PRIMARY_CLOCK          ; INCLK0                                       ;
+;     -- INCLK0_INPUT_FREQUENCY ; 20000                                        ;
+;     -- INCLK1_INPUT_FREQUENCY ; 0                                            ;
+;     -- VCO_MULTIPLY_BY        ; 0                                            ;
+;     -- VCO_DIVIDE_BY          ; 0                                            ;
++-------------------------------+----------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; altsyncram Parameter Settings by Entity Instance                                                  ;
++-------------------------------------------+-------------------------------------------------------+
+; Name                                      ; Value                                                 ;
++-------------------------------------------+-------------------------------------------------------+
+; Number of entity instances                ; 7                                                     ;
+; Entity Instance                           ; Memory:mem|altsyncram:memory_1_symbol0_rtl_0          ;
+;     -- OPERATION_MODE                     ; DUAL_PORT                                             ;
+;     -- WIDTH_A                            ; 8                                                     ;
+;     -- NUMWORDS_A                         ; 10241                                                 ;
+;     -- OUTDATA_REG_A                      ; UNREGISTERED                                          ;
+;     -- WIDTH_B                            ; 8                                                     ;
+;     -- NUMWORDS_B                         ; 10241                                                 ;
+;     -- ADDRESS_REG_B                      ; CLOCK0                                                ;
+;     -- OUTDATA_REG_B                      ; UNREGISTERED                                          ;
+;     -- RAM_BLOCK_TYPE                     ; AUTO                                                  ;
+;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                             ;
+; Entity Instance                           ; Memory:mem|altsyncram:memory_1_symbol1_rtl_0          ;
+;     -- OPERATION_MODE                     ; DUAL_PORT                                             ;
+;     -- WIDTH_A                            ; 8                                                     ;
+;     -- NUMWORDS_A                         ; 10241                                                 ;
+;     -- OUTDATA_REG_A                      ; UNREGISTERED                                          ;
+;     -- WIDTH_B                            ; 8                                                     ;
+;     -- NUMWORDS_B                         ; 10241                                                 ;
+;     -- ADDRESS_REG_B                      ; CLOCK0                                                ;
+;     -- OUTDATA_REG_B                      ; UNREGISTERED                                          ;
+;     -- RAM_BLOCK_TYPE                     ; AUTO                                                  ;
+;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                             ;
+; Entity Instance                           ; picorv32:cpu|altsyncram:cpuregs_rtl_0                 ;
+;     -- OPERATION_MODE                     ; DUAL_PORT                                             ;
+;     -- WIDTH_A                            ; 32                                                    ;
+;     -- NUMWORDS_A                         ; 32                                                    ;
+;     -- OUTDATA_REG_A                      ; UNREGISTERED                                          ;
+;     -- WIDTH_B                            ; 32                                                    ;
+;     -- NUMWORDS_B                         ; 32                                                    ;
+;     -- ADDRESS_REG_B                      ; CLOCK0                                                ;
+;     -- OUTDATA_REG_B                      ; UNREGISTERED                                          ;
+;     -- RAM_BLOCK_TYPE                     ; AUTO                                                  ;
+;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                             ;
+; Entity Instance                           ; picorv32:cpu|altsyncram:cpuregs_rtl_1                 ;
+;     -- OPERATION_MODE                     ; DUAL_PORT                                             ;
+;     -- WIDTH_A                            ; 32                                                    ;
+;     -- NUMWORDS_A                         ; 32                                                    ;
+;     -- OUTDATA_REG_A                      ; UNREGISTERED                                          ;
+;     -- WIDTH_B                            ; 32                                                    ;
+;     -- NUMWORDS_B                         ; 32                                                    ;
+;     -- ADDRESS_REG_B                      ; CLOCK0                                                ;
+;     -- OUTDATA_REG_B                      ; UNREGISTERED                                          ;
+;     -- RAM_BLOCK_TYPE                     ; AUTO                                                  ;
+;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                             ;
+; Entity Instance                           ; Memory:mem|altsyncram:memory_1_symbol3_rtl_0          ;
+;     -- OPERATION_MODE                     ; DUAL_PORT                                             ;
+;     -- WIDTH_A                            ; 8                                                     ;
+;     -- NUMWORDS_A                         ; 10241                                                 ;
+;     -- OUTDATA_REG_A                      ; UNREGISTERED                                          ;
+;     -- WIDTH_B                            ; 8                                                     ;
+;     -- NUMWORDS_B                         ; 10241                                                 ;
+;     -- ADDRESS_REG_B                      ; CLOCK0                                                ;
+;     -- OUTDATA_REG_B                      ; UNREGISTERED                                          ;
+;     -- RAM_BLOCK_TYPE                     ; AUTO                                                  ;
+;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                             ;
+; Entity Instance                           ; Memory:mem|altsyncram:memory_1_symbol2_rtl_0          ;
+;     -- OPERATION_MODE                     ; DUAL_PORT                                             ;
+;     -- WIDTH_A                            ; 8                                                     ;
+;     -- NUMWORDS_A                         ; 10241                                                 ;
+;     -- OUTDATA_REG_A                      ; UNREGISTERED                                          ;
+;     -- WIDTH_B                            ; 8                                                     ;
+;     -- NUMWORDS_B                         ; 10241                                                 ;
+;     -- ADDRESS_REG_B                      ; CLOCK0                                                ;
+;     -- OUTDATA_REG_B                      ; UNREGISTERED                                          ;
+;     -- RAM_BLOCK_TYPE                     ; AUTO                                                  ;
+;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                             ;
+; Entity Instance                           ; AsyncReceiver:uartRx|Fifo:fifo_1|altsyncram:mem_rtl_0 ;
+;     -- OPERATION_MODE                     ; DUAL_PORT                                             ;
+;     -- WIDTH_A                            ; 8                                                     ;
+;     -- NUMWORDS_A                         ; 32                                                    ;
+;     -- OUTDATA_REG_A                      ; UNREGISTERED                                          ;
+;     -- WIDTH_B                            ; 8                                                     ;
+;     -- NUMWORDS_B                         ; 32                                                    ;
+;     -- ADDRESS_REG_B                      ; CLOCK0                                                ;
+;     -- OUTDATA_REG_B                      ; UNREGISTERED                                          ;
+;     -- RAM_BLOCK_TYPE                     ; AUTO                                                  ;
+;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                             ;
++-------------------------------------------+-------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; lpm_mult Parameter Settings by Entity Instance                                                      ;
++---------------------------------------+-------------------------------------------------------------+
+; Name                                  ; Value                                                       ;
++---------------------------------------+-------------------------------------------------------------+
+; Number of entity instances            ; 1                                                           ;
+; Entity Instance                       ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0 ;
+;     -- LPM_WIDTHA                     ; 33                                                          ;
+;     -- LPM_WIDTHB                     ; 33                                                          ;
+;     -- LPM_WIDTHP                     ; 66                                                          ;
+;     -- LPM_REPRESENTATION             ; SIGNED                                                      ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                                          ;
+;     -- INPUT_B_IS_CONSTANT            ; NO                                                          ;
+;     -- USE_EAB                        ; OFF                                                         ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                                        ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                                          ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                                          ;
++---------------------------------------+-------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "picorv32:cpu"                                                                               ;
++--------------+--------+----------+-------------------------------------------------------------------------------------+
+; Port         ; Type   ; Severity ; Details                                                                             ;
++--------------+--------+----------+-------------------------------------------------------------------------------------+
+; trap         ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; mem_la_read  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; mem_la_write ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; mem_la_addr  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; mem_la_wdata ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; mem_la_wstrb ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; pcpi_valid   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; pcpi_insn    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; pcpi_rs1     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; pcpi_rs2     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; pcpi_wr      ; Input  ; Info     ; Stuck at GND                                                                        ;
+; pcpi_rd      ; Input  ; Info     ; Stuck at GND                                                                        ;
+; pcpi_wait    ; Input  ; Info     ; Stuck at GND                                                                        ;
+; pcpi_ready   ; Input  ; Info     ; Stuck at GND                                                                        ;
+; irq          ; Input  ; Info     ; Stuck at GND                                                                        ;
+; eoi          ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; trace_valid  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; trace_data   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++--------------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "busInterface:busInterface"                                                                   ;
++---------------+--------+----------+-------------------------------------------------------------------------------------+
+; Port          ; Type   ; Severity ; Details                                                                             ;
++---------------+--------+----------+-------------------------------------------------------------------------------------+
+; enables[1..0] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++---------------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "prng:prng|xoroshiro128plus:prng"                                                           ;
++-------------+--------+----------+-------------------------------------------------------------------------------------+
+; Port        ; Type   ; Severity ; Details                                                                             ;
++-------------+--------+----------+-------------------------------------------------------------------------------------+
+; out[63..32] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++-------------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "Memory:mem"                                                                                                                                                                               ;
++-------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port        ; Type  ; Severity ; Details                                                                                                                                                                             ;
++-------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; io_mem_addr ; Input ; Warning  ; Input port expression (32 bits) is wider than the input port (16 bits) it drives.  The 16 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; reset       ; Input ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND.                                        ;
++-------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "hundredMsTick:hundredMsTick"                                                        ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+; Port ; Type   ; Severity ; Details                                                                             ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+; tick ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "AsyncReceiver:uartRx"                                                                                                                                                                    ;
++-------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port        ; Type  ; Severity ; Details                                                                                                                                                                            ;
++-------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; io_mem_addr ; Input ; Warning  ; Input port expression (32 bits) is wider than the input port (4 bits) it drives.  The 28 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
++-------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "gpio:gpio"                                                                                 ;
++-------------+--------+----------+-------------------------------------------------------------------------------------+
+; Port        ; Type   ; Severity ; Details                                                                             ;
++-------------+--------+----------+-------------------------------------------------------------------------------------+
+; gpio[31..8] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++-------------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "pll_sys:pll_sys_inst"                                                                 ;
++--------+--------+----------+-------------------------------------------------------------------------------------+
+; Port   ; Type   ; Severity ; Details                                                                             ;
++--------+--------+----------+-------------------------------------------------------------------------------------+
+; locked ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++--------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------+
+; Post-Synthesis Netlist Statistics for Top Partition ;
++-----------------------+-----------------------------+
+; Type                  ; Count                       ;
++-----------------------+-----------------------------+
+; boundary_port         ; 46                          ;
+; cycloneiii_ff         ; 1420                        ;
+;     CLR               ; 214                         ;
+;     ENA               ; 439                         ;
+;     ENA CLR           ; 28                          ;
+;     ENA SCLR          ; 54                          ;
+;     ENA SCLR SLD      ; 27                          ;
+;     ENA SLD           ; 112                         ;
+;     SCLR              ; 47                          ;
+;     SCLR SLD          ; 1                           ;
+;     SLD               ; 32                          ;
+;     plain             ; 466                         ;
+; cycloneiii_lcell_comb ; 2711                        ;
+;     arith             ; 561                         ;
+;         2 data inputs ; 155                         ;
+;         3 data inputs ; 406                         ;
+;     normal            ; 2150                        ;
+;         0 data inputs ; 1                           ;
+;         1 data inputs ; 21                          ;
+;         2 data inputs ; 217                         ;
+;         3 data inputs ; 637                         ;
+;         4 data inputs ; 1274                        ;
+; cycloneiii_mac_mult   ; 4                           ;
+; cycloneiii_mac_out    ; 4                           ;
+; cycloneiii_pll        ; 1                           ;
+; cycloneiii_ram_block  ; 136                         ;
+;                       ;                             ;
+; Max LUT depth         ; 13.00                       ;
+; Average LUT depth     ; 4.99                        ;
++-----------------------+-----------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:04     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Analysis & Synthesis
+    Info: Version 15.0.0 Build 145 04/22/2015 SJ Web Edition
+    Info: Processing started: Sat Sep 16 21:12:14 2023
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off xoro -c xoro
+Info (20032): Parallel compilation is enabled and will use up to 2 processors
+Info (12021): Found 1 design units, including 1 entities, in source file pll_sys.v
+    Info (12023): Found entity 1: pll_sys
+Info (12021): Found 1 design units, including 1 entities, in source file rtl/timer.v
+    Info (12023): Found entity 1: timer
+Info (12021): Found 3 design units, including 3 entities, in source file rtl/uarttx.v
+    Info (12023): Found entity 1: EdgeDetect
+    Info (12023): Found entity 2: BaudRateGenerator
+    Info (12023): Found entity 3: uartTx
+Info (12021): Found 1 design units, including 1 entities, in source file rtl/xoroshiro128plus.v
+    Info (12023): Found entity 1: xoroshiro128plus
+Info (12021): Found 1 design units, including 1 entities, in source file rtl/prng.v
+    Info (12023): Found entity 1: prng
+Info (12021): Found 4 design units, including 4 entities, in source file rtl/xoro_top.v
+    Info (12023): Found entity 1: hundredMsTick
+    Info (12023): Found entity 2: gpio_test
+    Info (12023): Found entity 3: uart_test
+    Info (12023): Found entity 4: xoro_top
+Warning (10335): Unrecognized synthesis attribute "parallel_case" at rtl/picorv32.v(315)
+Warning (10335): Unrecognized synthesis attribute "full_case" at rtl/picorv32.v(386)
+Warning (10335): Unrecognized synthesis attribute "parallel_case" at rtl/picorv32.v(1100)
+Warning (10335): Unrecognized synthesis attribute "parallel_case" at rtl/picorv32.v(1230)
+Warning (10335): Unrecognized synthesis attribute "full_case" at rtl/picorv32.v(1230)
+Warning (10335): Unrecognized synthesis attribute "parallel_case" at rtl/picorv32.v(1247)
+Warning (10335): Unrecognized synthesis attribute "full_case" at rtl/picorv32.v(1247)
+Warning (10335): Unrecognized synthesis attribute "parallel_case" at rtl/picorv32.v(1293)
+Warning (10335): Unrecognized synthesis attribute "parallel_case" at rtl/picorv32.v(1464)
+Warning (10335): Unrecognized synthesis attribute "full_case" at rtl/picorv32.v(1464)
+Warning (10335): Unrecognized synthesis attribute "parallel_case" at rtl/picorv32.v(1476)
+Warning (10335): Unrecognized synthesis attribute "parallel_case" at rtl/picorv32.v(1562)
+Warning (10335): Unrecognized synthesis attribute "parallel_case" at rtl/picorv32.v(1606)
+Warning (10335): Unrecognized synthesis attribute "full_case" at rtl/picorv32.v(1606)
+Warning (10335): Unrecognized synthesis attribute "parallel_case" at rtl/picorv32.v(1714)
+Warning (10335): Unrecognized synthesis attribute "parallel_case" at rtl/picorv32.v(1745)
+Warning (10335): Unrecognized synthesis attribute "parallel_case" at rtl/picorv32.v(1815)
+Warning (10335): Unrecognized synthesis attribute "full_case" at rtl/picorv32.v(1815)
+Warning (10335): Unrecognized synthesis attribute "parallel_case" at rtl/picorv32.v(1823)
+Warning (10335): Unrecognized synthesis attribute "full_case" at rtl/picorv32.v(1823)
+Warning (10335): Unrecognized synthesis attribute "parallel_case" at rtl/picorv32.v(1838)
+Warning (10335): Unrecognized synthesis attribute "full_case" at rtl/picorv32.v(1838)
+Warning (10335): Unrecognized synthesis attribute "parallel_case" at rtl/picorv32.v(1863)
+Warning (10335): Unrecognized synthesis attribute "full_case" at rtl/picorv32.v(1863)
+Warning (10335): Unrecognized synthesis attribute "parallel_case" at rtl/picorv32.v(1880)
+Warning (10335): Unrecognized synthesis attribute "full_case" at rtl/picorv32.v(1880)
+Info (12021): Found 8 design units, including 8 entities, in source file rtl/picorv32.v
+    Info (12023): Found entity 1: picorv32
+    Info (12023): Found entity 2: picorv32_regs
+    Info (12023): Found entity 3: picorv32_pcpi_mul
+    Info (12023): Found entity 4: picorv32_pcpi_fast_mul
+    Info (12023): Found entity 5: picorv32_pcpi_div
+    Info (12023): Found entity 6: picorv32_axi
+    Info (12023): Found entity 7: picorv32_axi_adapter
+    Info (12023): Found entity 8: picorv32_wb
+Info (12021): Found 1 design units, including 1 entities, in source file rtl/memory.v
+    Info (12023): Found entity 1: Memory
+Info (12021): Found 1 design units, including 1 entities, in source file rtl/gpio.v
+    Info (12023): Found entity 1: gpio
+Info (12021): Found 1 design units, including 1 entities, in source file qram32.v
+    Info (12023): Found entity 1: qram32
+Info (12021): Found 1 design units, including 1 entities, in source file rtl/businterface.v
+    Info (12023): Found entity 1: busInterface
+Info (12021): Found 2 design units, including 2 entities, in source file rtl/asyncreceiver.v
+    Info (12023): Found entity 1: Fifo
+    Info (12023): Found entity 2: AsyncReceiver
+Warning (10236): Verilog HDL Implicit Net warning at uartTx.v(51): created implicit net for "baudRateClock"
+Warning (10236): Verilog HDL Implicit Net warning at uartTx.v(104): created implicit net for "bitStart"
+Warning (10236): Verilog HDL Implicit Net warning at xoro_top.v(204): created implicit net for "CLOCK_1843200"
+Info (12127): Elaborating entity "xoro_top" for the top level hierarchy
+Warning (10030): Net "pcpi_rd" at xoro_top.v(166) has no driver or initial value, using a default initial value '0'
+Warning (10030): Net "irq" at xoro_top.v(171) has no driver or initial value, using a default initial value '0'
+Warning (10030): Net "pcpi_wr" at xoro_top.v(165) has no driver or initial value, using a default initial value '0'
+Warning (10030): Net "pcpi_wait" at xoro_top.v(167) has no driver or initial value, using a default initial value '0'
+Warning (10030): Net "pcpi_ready" at xoro_top.v(168) has no driver or initial value, using a default initial value '0'
+Warning (10034): Output port "GPIO_1_D[32]" at xoro_top.v(141) has no driver
+Warning (10034): Output port "GPIO_1_D[30..0]" at xoro_top.v(141) has no driver
+Info (12128): Elaborating entity "pll_sys" for hierarchy "pll_sys:pll_sys_inst"
+Info (12128): Elaborating entity "altpll" for hierarchy "pll_sys:pll_sys_inst|altpll:altpll_component"
+Info (12130): Elaborated megafunction instantiation "pll_sys:pll_sys_inst|altpll:altpll_component"
+Info (12133): Instantiated megafunction "pll_sys:pll_sys_inst|altpll:altpll_component" with the following parameter:
+    Info (12134): Parameter "bandwidth_type" = "AUTO"
+    Info (12134): Parameter "clk0_divide_by" = "1"
+    Info (12134): Parameter "clk0_duty_cycle" = "50"
+    Info (12134): Parameter "clk0_multiply_by" = "2"
+    Info (12134): Parameter "clk0_phase_shift" = "0"
+    Info (12134): Parameter "clk1_divide_by" = "15625"
+    Info (12134): Parameter "clk1_duty_cycle" = "50"
+    Info (12134): Parameter "clk1_multiply_by" = "2304"
+    Info (12134): Parameter "clk1_phase_shift" = "0"
+    Info (12134): Parameter "clk2_divide_by" = "15625"
+    Info (12134): Parameter "clk2_duty_cycle" = "50"
+    Info (12134): Parameter "clk2_multiply_by" = "576"
+    Info (12134): Parameter "clk2_phase_shift" = "0"
+    Info (12134): Parameter "compensate_clock" = "CLK0"
+    Info (12134): Parameter "inclk0_input_frequency" = "20000"
+    Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
+    Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=pll_sys"
+    Info (12134): Parameter "lpm_type" = "altpll"
+    Info (12134): Parameter "operation_mode" = "NORMAL"
+    Info (12134): Parameter "pll_type" = "AUTO"
+    Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
+    Info (12134): Parameter "port_areset" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
+    Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
+    Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
+    Info (12134): Parameter "port_inclk0" = "PORT_USED"
+    Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
+    Info (12134): Parameter "port_locked" = "PORT_USED"
+    Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
+    Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
+    Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
+    Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
+    Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
+    Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clk0" = "PORT_USED"
+    Info (12134): Parameter "port_clk1" = "PORT_USED"
+    Info (12134): Parameter "port_clk2" = "PORT_USED"
+    Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
+    Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
+    Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
+    Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
+    Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
+    Info (12134): Parameter "self_reset_on_loss_lock" = "ON"
+    Info (12134): Parameter "width_clock" = "5"
+Info (12021): Found 1 design units, including 1 entities, in source file db/pll_sys_altpll.v
+    Info (12023): Found entity 1: pll_sys_altpll
+Info (12128): Elaborating entity "pll_sys_altpll" for hierarchy "pll_sys:pll_sys_inst|altpll:altpll_component|pll_sys_altpll:auto_generated"
+Info (12128): Elaborating entity "gpio" for hierarchy "gpio:gpio"
+Warning (10230): Verilog HDL assignment warning at gpio.v(47): truncated value with size 32 to match size of target (8)
+Info (12128): Elaborating entity "uartTx" for hierarchy "uartTx:uartTx"
+Info (12128): Elaborating entity "BaudRateGenerator" for hierarchy "uartTx:uartTx|BaudRateGenerator:baudRateGenerator"
+Warning (10230): Verilog HDL assignment warning at uartTx.v(63): truncated value with size 32 to match size of target (4)
+Info (12128): Elaborating entity "EdgeDetect" for hierarchy "uartTx:uartTx|BaudRateGenerator:baudRateGenerator|EdgeDetect:baudClockEdgeDetect"
+Info (12128): Elaborating entity "AsyncReceiver" for hierarchy "AsyncReceiver:uartRx"
+Info (10264): Verilog HDL Case Statement information at AsyncReceiver.v(154): all case item expressions in this case statement are onehot
+Info (10264): Verilog HDL Case Statement information at AsyncReceiver.v(194): all case item expressions in this case statement are onehot
+Info (12128): Elaborating entity "Fifo" for hierarchy "AsyncReceiver:uartRx|Fifo:fifo_1"
+Info (12128): Elaborating entity "hundredMsTick" for hierarchy "hundredMsTick:hundredMsTick"
+Info (12128): Elaborating entity "Memory" for hierarchy "Memory:mem"
+Warning (10850): Verilog HDL warning at memory.v(32): number of words (16384) in memory file does not match the number of elements in the address range [0:10240]
+Warning (10850): Verilog HDL warning at memory.v(33): number of words (16384) in memory file does not match the number of elements in the address range [0:10240]
+Warning (10850): Verilog HDL warning at memory.v(34): number of words (16384) in memory file does not match the number of elements in the address range [0:10240]
+Warning (10850): Verilog HDL warning at memory.v(35): number of words (16384) in memory file does not match the number of elements in the address range [0:10240]
+Warning (10230): Verilog HDL assignment warning at memory.v(56): truncated value with size 16 to match size of target (14)
+Info (12128): Elaborating entity "prng" for hierarchy "prng:prng"
+Warning (10230): Verilog HDL assignment warning at prng.v(43): truncated value with size 64 to match size of target (32)
+Info (12128): Elaborating entity "xoroshiro128plus" for hierarchy "prng:prng|xoroshiro128plus:prng"
+Info (12128): Elaborating entity "timer" for hierarchy "timer:timer"
+Info (12128): Elaborating entity "busInterface" for hierarchy "busInterface:busInterface"
+Info (12128): Elaborating entity "picorv32" for hierarchy "picorv32:cpu"
+Warning (10036): Verilog HDL or VHDL warning at picorv32.v(165): object "dbg_insn_addr" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at picorv32.v(167): object "dbg_mem_valid" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at picorv32.v(168): object "dbg_mem_instr" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at picorv32.v(169): object "dbg_mem_ready" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at picorv32.v(170): object "dbg_mem_addr" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at picorv32.v(171): object "dbg_mem_wdata" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at picorv32.v(172): object "dbg_mem_wstrb" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at picorv32.v(173): object "dbg_mem_rdata" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at picorv32.v(359): object "mem_busy" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at picorv32.v(679): object "dbg_rs1val" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at picorv32.v(680): object "dbg_rs2val" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at picorv32.v(681): object "dbg_rs1val_valid" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at picorv32.v(682): object "dbg_rs2val_valid" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at picorv32.v(751): object "dbg_valid_insn" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at picorv32.v(1163): object "dbg_ascii_state" assigned a value but never read
+Warning (10763): Verilog HDL warning at picorv32.v(316): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness
+Warning (10270): Verilog HDL Case Statement warning at picorv32.v(316): incomplete case statement has no default case item
+Warning (10230): Verilog HDL assignment warning at picorv32.v(601): truncated value with size 32 to match size of target (2)
+Warning (10230): Verilog HDL assignment warning at picorv32.v(1224): truncated value with size 33 to match size of target (32)
+Warning (10230): Verilog HDL assignment warning at picorv32.v(1229): truncated value with size 32 to match size of target (1)
+Warning (10763): Verilog HDL warning at picorv32.v(1231): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness
+Warning (10208): Verilog HDL Case Statement warning at picorv32.v(1231): honored full_case synthesis attribute - differences between design synthesis and simulation may occur
+Warning (10763): Verilog HDL warning at picorv32.v(1248): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness
+Warning (10208): Verilog HDL Case Statement warning at picorv32.v(1248): honored full_case synthesis attribute - differences between design synthesis and simulation may occur
+Warning (10763): Verilog HDL warning at picorv32.v(1294): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness
+Warning (10270): Verilog HDL Case Statement warning at picorv32.v(1294): incomplete case statement has no default case item
+Warning (10230): Verilog HDL assignment warning at picorv32.v(1322): truncated value with size 32 to match size of target (5)
+Warning (10230): Verilog HDL assignment warning at picorv32.v(1377): truncated value with size 32 to match size of target (5)
+Warning (10230): Verilog HDL assignment warning at picorv32.v(1399): truncated value with size 32 to match size of target (4)
+Warning (10230): Verilog HDL assignment warning at picorv32.v(1401): truncated value with size 32 to match size of target (4)
+Warning (10763): Verilog HDL warning at picorv32.v(1477): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness
+Warning (10230): Verilog HDL assignment warning at picorv32.v(1573): truncated value with size 32 to match size of target (5)
+Warning (10230): Verilog HDL assignment warning at picorv32.v(1710): truncated value with size 32 to match size of target (5)
+Warning (10230): Verilog HDL assignment warning at picorv32.v(1740): truncated value with size 32 to match size of target (5)
+Warning (10763): Verilog HDL warning at picorv32.v(1816): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness
+Warning (10208): Verilog HDL Case Statement warning at picorv32.v(1816): honored full_case synthesis attribute - differences between design synthesis and simulation may occur
+Warning (10230): Verilog HDL assignment warning at picorv32.v(1821): truncated value with size 32 to match size of target (5)
+Warning (10763): Verilog HDL warning at picorv32.v(1824): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness
+Warning (10208): Verilog HDL Case Statement warning at picorv32.v(1824): honored full_case synthesis attribute - differences between design synthesis and simulation may occur
+Warning (10230): Verilog HDL assignment warning at picorv32.v(1829): truncated value with size 32 to match size of target (5)
+Warning (10763): Verilog HDL warning at picorv32.v(1839): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness
+Warning (10208): Verilog HDL Case Statement warning at picorv32.v(1839): honored full_case synthesis attribute - differences between design synthesis and simulation may occur
+Warning (10763): Verilog HDL warning at picorv32.v(1864): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness
+Warning (10208): Verilog HDL Case Statement warning at picorv32.v(1864): honored full_case synthesis attribute - differences between design synthesis and simulation may occur
+Warning (10763): Verilog HDL warning at picorv32.v(1881): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness
+Warning (10208): Verilog HDL Case Statement warning at picorv32.v(1881): honored full_case synthesis attribute - differences between design synthesis and simulation may occur
+Info (12128): Elaborating entity "picorv32_pcpi_fast_mul" for hierarchy "picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul"
+Warning (10270): Verilog HDL Case Statement warning at picorv32.v(2285): incomplete case statement has no default case item
+Warning (10230): Verilog HDL assignment warning at picorv32.v(2324): truncated value with size 4 to match size of target (3)
+Warning (10230): Verilog HDL assignment warning at picorv32.v(2341): truncated value with size 64 to match size of target (32)
+Info (12128): Elaborating entity "picorv32_pcpi_div" for hierarchy "picorv32:cpu|picorv32_pcpi_div:pcpi_div"
+Warning (10259): Verilog HDL error at picorv32.v(2408): constant value overflow
+Warning (10230): Verilog HDL assignment warning at picorv32.v(2429): truncated value with size 63 to match size of target (32)
+Critical Warning (127005): Memory depth (16384) in the design file differs from memory depth (10241) in the Memory Initialization File "E:/Photonic/RISCV/db/xoro.ram0_Memory_a0c6519c.hdl.mif" -- setting initial value for remaining addresses to 0
+Warning (276020): Inferred RAM node "Memory:mem|memory_1_symbol0_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
+Critical Warning (127005): Memory depth (16384) in the design file differs from memory depth (10241) in the Memory Initialization File "E:/Photonic/RISCV/db/xoro.ram1_Memory_a0c6519c.hdl.mif" -- setting initial value for remaining addresses to 0
+Warning (276020): Inferred RAM node "Memory:mem|memory_1_symbol1_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
+Warning (276020): Inferred RAM node "picorv32:cpu|cpuregs_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
+Warning (276020): Inferred RAM node "picorv32:cpu|cpuregs_rtl_1" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
+Critical Warning (127005): Memory depth (16384) in the design file differs from memory depth (10241) in the Memory Initialization File "E:/Photonic/RISCV/db/xoro.ram3_Memory_a0c6519c.hdl.mif" -- setting initial value for remaining addresses to 0
+Warning (276020): Inferred RAM node "Memory:mem|memory_1_symbol3_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
+Critical Warning (127005): Memory depth (16384) in the design file differs from memory depth (10241) in the Memory Initialization File "E:/Photonic/RISCV/db/xoro.ram2_Memory_a0c6519c.hdl.mif" -- setting initial value for remaining addresses to 0
+Warning (276020): Inferred RAM node "Memory:mem|memory_1_symbol2_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
+Warning (276020): Inferred RAM node "AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
+Info (19000): Inferred 7 megafunctions from design logic
+    Info (276029): Inferred altsyncram megafunction from the following design logic: "Memory:mem|memory_1_symbol0_rtl_0" 
+        Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
+        Info (286033): Parameter WIDTH_A set to 8
+        Info (286033): Parameter WIDTHAD_A set to 14
+        Info (286033): Parameter NUMWORDS_A set to 10241
+        Info (286033): Parameter WIDTH_B set to 8
+        Info (286033): Parameter WIDTHAD_B set to 14
+        Info (286033): Parameter NUMWORDS_B set to 10241
+        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
+        Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
+        Info (286033): Parameter ADDRESS_ACLR_B set to NONE
+        Info (286033): Parameter OUTDATA_ACLR_B set to NONE
+        Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
+        Info (286033): Parameter INDATA_ACLR_A set to NONE
+        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
+        Info (286033): Parameter INIT_FILE set to db/xoro.ram0_Memory_a0c6519c.hdl.mif
+    Info (276029): Inferred altsyncram megafunction from the following design logic: "Memory:mem|memory_1_symbol1_rtl_0" 
+        Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
+        Info (286033): Parameter WIDTH_A set to 8
+        Info (286033): Parameter WIDTHAD_A set to 14
+        Info (286033): Parameter NUMWORDS_A set to 10241
+        Info (286033): Parameter WIDTH_B set to 8
+        Info (286033): Parameter WIDTHAD_B set to 14
+        Info (286033): Parameter NUMWORDS_B set to 10241
+        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
+        Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
+        Info (286033): Parameter ADDRESS_ACLR_B set to NONE
+        Info (286033): Parameter OUTDATA_ACLR_B set to NONE
+        Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
+        Info (286033): Parameter INDATA_ACLR_A set to NONE
+        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
+        Info (286033): Parameter INIT_FILE set to db/xoro.ram1_Memory_a0c6519c.hdl.mif
+    Info (276029): Inferred altsyncram megafunction from the following design logic: "picorv32:cpu|cpuregs_rtl_0" 
+        Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
+        Info (286033): Parameter WIDTH_A set to 32
+        Info (286033): Parameter WIDTHAD_A set to 5
+        Info (286033): Parameter NUMWORDS_A set to 32
+        Info (286033): Parameter WIDTH_B set to 32
+        Info (286033): Parameter WIDTHAD_B set to 5
+        Info (286033): Parameter NUMWORDS_B set to 32
+        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
+        Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
+        Info (286033): Parameter ADDRESS_ACLR_B set to NONE
+        Info (286033): Parameter OUTDATA_ACLR_B set to NONE
+        Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
+        Info (286033): Parameter INDATA_ACLR_A set to NONE
+        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
+    Info (276029): Inferred altsyncram megafunction from the following design logic: "picorv32:cpu|cpuregs_rtl_1" 
+        Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
+        Info (286033): Parameter WIDTH_A set to 32
+        Info (286033): Parameter WIDTHAD_A set to 5
+        Info (286033): Parameter NUMWORDS_A set to 32
+        Info (286033): Parameter WIDTH_B set to 32
+        Info (286033): Parameter WIDTHAD_B set to 5
+        Info (286033): Parameter NUMWORDS_B set to 32
+        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
+        Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
+        Info (286033): Parameter ADDRESS_ACLR_B set to NONE
+        Info (286033): Parameter OUTDATA_ACLR_B set to NONE
+        Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
+        Info (286033): Parameter INDATA_ACLR_A set to NONE
+        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
+    Info (276029): Inferred altsyncram megafunction from the following design logic: "Memory:mem|memory_1_symbol3_rtl_0" 
+        Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
+        Info (286033): Parameter WIDTH_A set to 8
+        Info (286033): Parameter WIDTHAD_A set to 14
+        Info (286033): Parameter NUMWORDS_A set to 10241
+        Info (286033): Parameter WIDTH_B set to 8
+        Info (286033): Parameter WIDTHAD_B set to 14
+        Info (286033): Parameter NUMWORDS_B set to 10241
+        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
+        Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
+        Info (286033): Parameter ADDRESS_ACLR_B set to NONE
+        Info (286033): Parameter OUTDATA_ACLR_B set to NONE
+        Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
+        Info (286033): Parameter INDATA_ACLR_A set to NONE
+        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
+        Info (286033): Parameter INIT_FILE set to db/xoro.ram3_Memory_a0c6519c.hdl.mif
+    Info (276029): Inferred altsyncram megafunction from the following design logic: "Memory:mem|memory_1_symbol2_rtl_0" 
+        Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
+        Info (286033): Parameter WIDTH_A set to 8
+        Info (286033): Parameter WIDTHAD_A set to 14
+        Info (286033): Parameter NUMWORDS_A set to 10241
+        Info (286033): Parameter WIDTH_B set to 8
+        Info (286033): Parameter WIDTHAD_B set to 14
+        Info (286033): Parameter NUMWORDS_B set to 10241
+        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
+        Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
+        Info (286033): Parameter ADDRESS_ACLR_B set to NONE
+        Info (286033): Parameter OUTDATA_ACLR_B set to NONE
+        Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
+        Info (286033): Parameter INDATA_ACLR_A set to NONE
+        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
+        Info (286033): Parameter INIT_FILE set to db/xoro.ram2_Memory_a0c6519c.hdl.mif
+    Info (276029): Inferred altsyncram megafunction from the following design logic: "AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0" 
+        Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
+        Info (286033): Parameter WIDTH_A set to 8
+        Info (286033): Parameter WIDTHAD_A set to 5
+        Info (286033): Parameter NUMWORDS_A set to 32
+        Info (286033): Parameter WIDTH_B set to 8
+        Info (286033): Parameter WIDTHAD_B set to 5
+        Info (286033): Parameter NUMWORDS_B set to 32
+        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
+        Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
+        Info (286033): Parameter ADDRESS_ACLR_B set to NONE
+        Info (286033): Parameter OUTDATA_ACLR_B set to NONE
+        Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
+        Info (286033): Parameter INDATA_ACLR_A set to NONE
+        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
+Info (278001): Inferred 1 megafunctions from design logic
+    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|Mult0"
+Info (12130): Elaborated megafunction instantiation "Memory:mem|altsyncram:memory_1_symbol0_rtl_0"
+Info (12133): Instantiated megafunction "Memory:mem|altsyncram:memory_1_symbol0_rtl_0" with the following parameter:
+    Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT"
+    Info (12134): Parameter "WIDTH_A" = "8"
+    Info (12134): Parameter "WIDTHAD_A" = "14"
+    Info (12134): Parameter "NUMWORDS_A" = "10241"
+    Info (12134): Parameter "WIDTH_B" = "8"
+    Info (12134): Parameter "WIDTHAD_B" = "14"
+    Info (12134): Parameter "NUMWORDS_B" = "10241"
+    Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
+    Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED"
+    Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE"
+    Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE"
+    Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0"
+    Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
+    Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
+    Info (12134): Parameter "INIT_FILE" = "db/xoro.ram0_Memory_a0c6519c.hdl.mif"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_bdi1.tdf
+    Info (12023): Found entity 1: altsyncram_bdi1
+Info (12021): Found 1 design units, including 1 entities, in source file db/decode_jsa.tdf
+    Info (12023): Found entity 1: decode_jsa
+Info (12021): Found 1 design units, including 1 entities, in source file db/decode_c8a.tdf
+    Info (12023): Found entity 1: decode_c8a
+Info (12021): Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf
+    Info (12023): Found entity 1: mux_3nb
+Info (12130): Elaborated megafunction instantiation "Memory:mem|altsyncram:memory_1_symbol1_rtl_0"
+Info (12133): Instantiated megafunction "Memory:mem|altsyncram:memory_1_symbol1_rtl_0" with the following parameter:
+    Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT"
+    Info (12134): Parameter "WIDTH_A" = "8"
+    Info (12134): Parameter "WIDTHAD_A" = "14"
+    Info (12134): Parameter "NUMWORDS_A" = "10241"
+    Info (12134): Parameter "WIDTH_B" = "8"
+    Info (12134): Parameter "WIDTHAD_B" = "14"
+    Info (12134): Parameter "NUMWORDS_B" = "10241"
+    Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
+    Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED"
+    Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE"
+    Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE"
+    Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0"
+    Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
+    Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
+    Info (12134): Parameter "INIT_FILE" = "db/xoro.ram1_Memory_a0c6519c.hdl.mif"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_cdi1.tdf
+    Info (12023): Found entity 1: altsyncram_cdi1
+Info (12130): Elaborated megafunction instantiation "picorv32:cpu|altsyncram:cpuregs_rtl_0"
+Info (12133): Instantiated megafunction "picorv32:cpu|altsyncram:cpuregs_rtl_0" with the following parameter:
+    Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT"
+    Info (12134): Parameter "WIDTH_A" = "32"
+    Info (12134): Parameter "WIDTHAD_A" = "5"
+    Info (12134): Parameter "NUMWORDS_A" = "32"
+    Info (12134): Parameter "WIDTH_B" = "32"
+    Info (12134): Parameter "WIDTHAD_B" = "5"
+    Info (12134): Parameter "NUMWORDS_B" = "32"
+    Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
+    Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED"
+    Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE"
+    Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE"
+    Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0"
+    Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
+    Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_trd1.tdf
+    Info (12023): Found entity 1: altsyncram_trd1
+Info (12130): Elaborated megafunction instantiation "Memory:mem|altsyncram:memory_1_symbol3_rtl_0"
+Info (12133): Instantiated megafunction "Memory:mem|altsyncram:memory_1_symbol3_rtl_0" with the following parameter:
+    Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT"
+    Info (12134): Parameter "WIDTH_A" = "8"
+    Info (12134): Parameter "WIDTHAD_A" = "14"
+    Info (12134): Parameter "NUMWORDS_A" = "10241"
+    Info (12134): Parameter "WIDTH_B" = "8"
+    Info (12134): Parameter "WIDTHAD_B" = "14"
+    Info (12134): Parameter "NUMWORDS_B" = "10241"
+    Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
+    Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED"
+    Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE"
+    Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE"
+    Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0"
+    Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
+    Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
+    Info (12134): Parameter "INIT_FILE" = "db/xoro.ram3_Memory_a0c6519c.hdl.mif"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_edi1.tdf
+    Info (12023): Found entity 1: altsyncram_edi1
+Info (12130): Elaborated megafunction instantiation "Memory:mem|altsyncram:memory_1_symbol2_rtl_0"
+Info (12133): Instantiated megafunction "Memory:mem|altsyncram:memory_1_symbol2_rtl_0" with the following parameter:
+    Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT"
+    Info (12134): Parameter "WIDTH_A" = "8"
+    Info (12134): Parameter "WIDTHAD_A" = "14"
+    Info (12134): Parameter "NUMWORDS_A" = "10241"
+    Info (12134): Parameter "WIDTH_B" = "8"
+    Info (12134): Parameter "WIDTHAD_B" = "14"
+    Info (12134): Parameter "NUMWORDS_B" = "10241"
+    Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
+    Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED"
+    Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE"
+    Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE"
+    Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0"
+    Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
+    Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
+    Info (12134): Parameter "INIT_FILE" = "db/xoro.ram2_Memory_a0c6519c.hdl.mif"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_ddi1.tdf
+    Info (12023): Found entity 1: altsyncram_ddi1
+Info (12130): Elaborated megafunction instantiation "AsyncReceiver:uartRx|Fifo:fifo_1|altsyncram:mem_rtl_0"
+Info (12133): Instantiated megafunction "AsyncReceiver:uartRx|Fifo:fifo_1|altsyncram:mem_rtl_0" with the following parameter:
+    Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT"
+    Info (12134): Parameter "WIDTH_A" = "8"
+    Info (12134): Parameter "WIDTHAD_A" = "5"
+    Info (12134): Parameter "NUMWORDS_A" = "32"
+    Info (12134): Parameter "WIDTH_B" = "8"
+    Info (12134): Parameter "WIDTHAD_B" = "5"
+    Info (12134): Parameter "NUMWORDS_B" = "32"
+    Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
+    Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED"
+    Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE"
+    Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE"
+    Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0"
+    Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
+    Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_s9c1.tdf
+    Info (12023): Found entity 1: altsyncram_s9c1
+Info (12130): Elaborated megafunction instantiation "picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0"
+Info (12133): Instantiated megafunction "picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0" with the following parameter:
+    Info (12134): Parameter "LPM_WIDTHA" = "33"
+    Info (12134): Parameter "LPM_WIDTHB" = "33"
+    Info (12134): Parameter "LPM_WIDTHP" = "66"
+    Info (12134): Parameter "LPM_WIDTHR" = "66"
+    Info (12134): Parameter "LPM_WIDTHS" = "1"
+    Info (12134): Parameter "LPM_REPRESENTATION" = "SIGNED"
+    Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
+    Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "NO"
+    Info (12134): Parameter "MAXIMIZE_SPEED" = "5"
+Info (12021): Found 1 design units, including 1 entities, in source file db/mult_86t.tdf
+    Info (12023): Found entity 1: mult_86t
+Warning (12241): 2 hierarchies have connectivity warnings - see the Connectivity Checks report folder
+Info (13014): Ignored 204 buffer(s)
+    Info (13019): Ignored 204 SOFT buffer(s)
+Info (13000): Registers with preset signals will power-up high
+Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
+Warning (13024): Output pins are stuck at VCC or GND
+    Warning (13410): Pin "GPIO_1_D[0]" is stuck at GND
+    Warning (13410): Pin "GPIO_1_D[1]" is stuck at GND
+    Warning (13410): Pin "GPIO_1_D[2]" is stuck at GND
+    Warning (13410): Pin "GPIO_1_D[3]" is stuck at GND
+    Warning (13410): Pin "GPIO_1_D[4]" is stuck at GND
+    Warning (13410): Pin "GPIO_1_D[5]" is stuck at GND
+    Warning (13410): Pin "GPIO_1_D[6]" is stuck at GND
+    Warning (13410): Pin "GPIO_1_D[7]" is stuck at GND
+    Warning (13410): Pin "GPIO_1_D[8]" is stuck at GND
+    Warning (13410): Pin "GPIO_1_D[9]" is stuck at GND
+    Warning (13410): Pin "GPIO_1_D[10]" is stuck at GND
+    Warning (13410): Pin "GPIO_1_D[11]" is stuck at GND
+    Warning (13410): Pin "GPIO_1_D[12]" is stuck at GND
+    Warning (13410): Pin "GPIO_1_D[13]" is stuck at GND
+    Warning (13410): Pin "GPIO_1_D[14]" is stuck at GND
+    Warning (13410): Pin "GPIO_1_D[15]" is stuck at GND
+    Warning (13410): Pin "GPIO_1_D[16]" is stuck at GND
+    Warning (13410): Pin "GPIO_1_D[17]" is stuck at GND
+    Warning (13410): Pin "GPIO_1_D[18]" is stuck at GND
+    Warning (13410): Pin "GPIO_1_D[19]" is stuck at GND
+    Warning (13410): Pin "GPIO_1_D[20]" is stuck at GND
+    Warning (13410): Pin "GPIO_1_D[21]" is stuck at GND
+    Warning (13410): Pin "GPIO_1_D[22]" is stuck at GND
+    Warning (13410): Pin "GPIO_1_D[23]" is stuck at GND
+    Warning (13410): Pin "GPIO_1_D[24]" is stuck at GND
+    Warning (13410): Pin "GPIO_1_D[25]" is stuck at GND
+    Warning (13410): Pin "GPIO_1_D[26]" is stuck at GND
+    Warning (13410): Pin "GPIO_1_D[27]" is stuck at GND
+    Warning (13410): Pin "GPIO_1_D[28]" is stuck at GND
+    Warning (13410): Pin "GPIO_1_D[29]" is stuck at GND
+    Warning (13410): Pin "GPIO_1_D[30]" is stuck at GND
+    Warning (13410): Pin "GPIO_1_D[32]" is stuck at GND
+Info (286030): Timing-Driven Synthesis is running
+Info (17049): 10 registers lost all their fanouts during netlist optimizations.
+Info (144001): Generated suppressed messages file E:/Photonic/RISCV/output_files/xoro.map.smsg
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
+Warning (21074): Design contains 1 input pin(s) that do not drive logic
+    Warning (15610): No output dependent on input pin "reset_btn"
+Info (21057): Implemented 3480 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 3 input pins
+    Info (21059): Implemented 43 output pins
+    Info (21061): Implemented 3289 logic cells
+    Info (21064): Implemented 136 RAM segments
+    Info (21065): Implemented 1 PLLs
+    Info (21062): Implemented 8 DSP elements
+Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 142 warnings
+    Info: Peak virtual memory: 4859 megabytes
+    Info: Processing ended: Sat Sep 16 21:12:28 2023
+    Info: Elapsed time: 00:00:14
+    Info: Total CPU time (on all processors): 00:00:11
+
+
++------------------------------------------+
+; Analysis & Synthesis Suppressed Messages ;
++------------------------------------------+
+The suppressed messages can be found in E:/Photonic/RISCV/output_files/xoro.map.smsg.
+
+
diff --git a/rtl/DE0-NANO/output_files/xoro.map.smsg b/rtl/DE0-NANO/output_files/xoro.map.smsg
new file mode 100644
index 0000000..9e4f21a
--- /dev/null
+++ b/rtl/DE0-NANO/output_files/xoro.map.smsg
@@ -0,0 +1,23 @@
+Warning (10273): Verilog HDL warning at picorv32.v(284): extended using "x" or "z"
+Warning (10273): Verilog HDL warning at picorv32.v(304): extended using "x" or "z"
+Warning (10273): Verilog HDL warning at picorv32.v(311): extended using "x" or "z"
+Warning (10273): Verilog HDL warning at picorv32.v(370): extended using "x" or "z"
+Warning (10273): Verilog HDL warning at picorv32.v(372): extended using "x" or "z"
+Warning (10273): Verilog HDL warning at picorv32.v(1020): extended using "x" or "z"
+Warning (10273): Verilog HDL warning at picorv32.v(1229): extended using "x" or "z"
+Warning (10273): Verilog HDL warning at picorv32.v(1246): extended using "x" or "z"
+Warning (10273): Verilog HDL warning at picorv32.v(1290): extended using "x" or "z"
+Warning (10273): Verilog HDL warning at picorv32.v(1322): extended using "x" or "z"
+Warning (10273): Verilog HDL warning at picorv32.v(1377): extended using "x" or "z"
+Warning (10273): Verilog HDL warning at picorv32.v(1378): extended using "x" or "z"
+Warning (10273): Verilog HDL warning at picorv32.v(1390): extended using "x" or "z"
+Warning (10273): Verilog HDL warning at picorv32.v(1391): extended using "x" or "z"
+Warning (10273): Verilog HDL warning at picorv32.v(1409): extended using "x" or "z"
+Warning (10273): Verilog HDL warning at picorv32.v(1410): extended using "x" or "z"
+Warning (10273): Verilog HDL warning at picorv32.v(1413): extended using "x" or "z"
+Warning (10273): Verilog HDL warning at picorv32.v(1434): extended using "x" or "z"
+Warning (10273): Verilog HDL warning at picorv32.v(1559): extended using "x" or "z"
+Warning (10273): Verilog HDL warning at picorv32.v(1560): extended using "x" or "z"
+Warning (10273): Verilog HDL warning at picorv32.v(1946): extended using "x" or "z"
+Warning (10268): Verilog HDL information at picorv32.v(1375): always construct contains both blocking and non-blocking assignments
+Warning (10273): Verilog HDL warning at picorv32.v(2397): extended using "x" or "z"
diff --git a/rtl/DE0-NANO/output_files/xoro.map.summary b/rtl/DE0-NANO/output_files/xoro.map.summary
new file mode 100644
index 0000000..5c186f6
--- /dev/null
+++ b/rtl/DE0-NANO/output_files/xoro.map.summary
@@ -0,0 +1,14 @@
+Analysis & Synthesis Status : Successful - Sat Sep 16 21:12:28 2023
+Quartus II 64-Bit Version : 15.0.0 Build 145 04/22/2015 SJ Web Edition
+Revision Name : xoro
+Top-level Entity Name : xoro_top
+Family : Cyclone IV E
+Total logic elements : 3,155
+    Total combinational functions : 2,709
+    Dedicated logic registers : 1,420
+Total registers : 1420
+Total pins : 46
+Total virtual pins : 0
+Total memory bits : 330,016
+Embedded Multiplier 9-bit elements : 8
+Total PLLs : 1
diff --git a/rtl/DE0-NANO/output_files/xoro.pin b/rtl/DE0-NANO/output_files/xoro.pin
new file mode 100644
index 0000000..d999f37
--- /dev/null
+++ b/rtl/DE0-NANO/output_files/xoro.pin
@@ -0,0 +1,327 @@
+ -- Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, the Altera Quartus II License Agreement,
+ -- the Altera MegaCore Function License Agreement, or other 
+ -- applicable license agreement, including, without limitation, 
+ -- that your use is for the sole purpose of programming logic 
+ -- devices manufactured by Altera and sold by Altera or its 
+ -- authorized distributors.  Please refer to the applicable 
+ -- agreement for further details.
+ -- 
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --                  Bank 1:       3.3V
+ --                  Bank 2:       3.3V
+ --                  Bank 3:       1.2V
+ --                  Bank 4:       3.3V
+ --                  Bank 5:       3.3V
+ --                  Bank 6:       3.3V
+ --                  Bank 7:       3.3V
+ --                  Bank 8:       3.3V
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --                  It can also be used to report unused dedicated pins. The connection
+ --                  on the board for unused dedicated pins depends on whether this will
+ --                  be used in a future design. One example is device migration. When
+ --                  using device migration, refer to the device pin-tables. If it is a
+ --                  GND pin in the pin table or if it will not be used in a future design
+ --                  for another purpose the it MUST be connected to GND. If it is an unused
+ --                  dedicated pin, then it can be connected to a valid signal on the board
+ --                  (low, high, or toggling) if that signal is required for a different
+ --                  revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --                  This pin should be connected to GND. It may also be connected  to a
+ --                  valid signal  on the board  (low, high, or toggling)  if that signal
+ --                  is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --                  or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Web Edition
+CHIP  "xoro"  ASSIGNED TO AN: EP4CE22F17C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+VCCIO8                       : A1        : power  :                   : 3.3V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A2        :        :                   :         : 8         :                
+UART_TX                      : A3        : output : 3.3-V LVTTL       :         : 8         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A7        :        :                   :         : 8         :                
+GND+                         : A8        :        :                   :         : 8         :                
+GND+                         : A9        :        :                   :         : 7         :                
+GPIO_1_D[1]                  : A10       : output : 3.3-V LVTTL       :         : 7         : N              
+LED[3]                       : A11       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : A12       :        :                   :         : 7         :                
+LED[1]                       : A13       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7         :                
+LED[0]                       : A15       : output : 3.3-V LVTTL       :         : 7         : Y              
+VCCIO7                       : A16       : power  :                   : 3.3V    : 7         :                
+LED[6]                       : B1        : output : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : B2        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8         :                
+UART_RX                      : B4        : input  : 2.5 V             :         : 8         : Y              
+GPIO_1_D[3]                  : B5        : output : 3.3-V LVTTL       :         : 8         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8         :                
+GND+                         : B8        :        :                   :         : 8         :                
+GND+                         : B9        :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B10       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B11       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B12       :        :                   :         : 7         :                
+LED[2]                       : B13       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B14       :        :                   :         : 7         :                
+GND                          : B15       : gnd    :                   :         :           :                
+GPIO_1_D[7]                  : B16       : output : 3.3-V LVTTL       :         : 6         : N              
+~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C1        : input  : 3.3-V LVTTL       :         : 1         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : C2        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8         :                
+VCCIO8                       : C4        : power  :                   : 3.3V    : 8         :                
+GND                          : C5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C6        :        :                   :         : 8         :                
+VCCIO8                       : C7        : power  :                   : 3.3V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C9        :        :                   :         : 7         :                
+VCCIO7                       : C10       : power  :                   : 3.3V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C11       :        :                   :         : 7         :                
+GND                          : C12       : gnd    :                   :         :           :                
+VCCIO7                       : C13       : power  :                   : 3.3V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C16       :        :                   :         : 6         :                
+LED[4]                       : D1        : output : 3.3-V LVTTL       :         : 1         : Y              
+~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D2        : input  : 3.3-V LVTTL       :         : 1         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : D3        :        :                   :         : 8         :                
+VCCD_PLL3                    : D4        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8         :                
+GND                          : D7        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D9        :        :                   :         : 7         :                
+GND                          : D10       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D11       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D12       :        :                   :         : 7         :                
+VCCD_PLL2                    : D13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D16       :        :                   :         : 6         :                
+GND+                         : E1        :        :                   :         : 1         :                
+GND                          : E2        : gnd    :                   :         :           :                
+VCCIO1                       : E3        : power  :                   : 3.3V    : 1         :                
+GND                          : E4        : gnd    :                   :         :           :                
+GNDA3                        : E5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E10       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 7         :                
+GNDA2                        : E12       : gnd    :                   :         :           :                
+GND                          : E13       : gnd    :                   :         :           :                
+VCCIO6                       : E14       : power  :                   : 3.3V    : 6         :                
+GND+                         : E15       :        :                   :         : 6         :                
+GND+                         : E16       :        :                   :         : 6         :                
+GPIO_1_D[0]                  : F1        : output : 3.3-V LVTTL       :         : 1         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : F2        :        :                   :         : 1         :                
+LED[5]                       : F3        : output : 3.3-V LVTTL       :         : 1         : Y              
+nSTATUS                      : F4        :        :                   :         : 1         :                
+VCCA3                        : F5        : power  :                   : 2.5V    :           :                
+GND                          : F6        : gnd    :                   :         :           :                
+VCCINT                       : F7        : power  :                   : 1.2V    :           :                
+GPIO_1_D[5]                  : F8        : output : 3.3-V LVTTL       :         : 8         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 7         :                
+GND                          : F10       : gnd    :                   :         :           :                
+VCCINT                       : F11       : power  :                   : 1.2V    :           :                
+VCCA2                        : F12       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 6         :                
+~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : F16       : output : 3.3-V LVTTL       :         : 6         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G1        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G2        :        :                   :         : 1         :                
+VCCIO1                       : G3        : power  :                   : 3.3V    : 1         :                
+GND                          : G4        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G5        :        :                   :         : 1         :                
+VCCINT                       : G6        : power  :                   : 1.2V    :           :                
+VCCINT                       : G7        : power  :                   : 1.2V    :           :                
+VCCINT                       : G8        : power  :                   : 1.2V    :           :                
+VCCINT                       : G9        : power  :                   : 1.2V    :           :                
+VCCINT                       : G10       : power  :                   : 1.2V    :           :                
+GND                          : G11       : gnd    :                   :         :           :                
+MSEL2                        : G12       :        :                   :         : 6         :                
+GND                          : G13       : gnd    :                   :         :           :                
+VCCIO6                       : G14       : power  :                   : 3.3V    : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 6         :                
+~ALTERA_DCLK~                : H1        : output : 3.3-V LVTTL       :         : 1         : N              
+~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H2        : input  : 3.3-V LVTTL       :         : 1         : N              
+TCK                          : H3        : input  :                   :         : 1         :                
+TDI                          : H4        : input  :                   :         : 1         :                
+nCONFIG                      : H5        :        :                   :         : 1         :                
+VCCINT                       : H6        : power  :                   : 1.2V    :           :                
+GND                          : H7        : gnd    :                   :         :           :                
+GND                          : H8        : gnd    :                   :         :           :                
+GND                          : H9        : gnd    :                   :         :           :                
+GND                          : H10       : gnd    :                   :         :           :                
+VCCINT                       : H11       : power  :                   : 1.2V    :           :                
+MSEL1                        : H12       :        :                   :         : 6         :                
+MSEL0                        : H13       :        :                   :         : 6         :                
+CONF_DONE                    : H14       :        :                   :         : 6         :                
+GND                          : H15       : gnd    :                   :         :           :                
+GND                          : H16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J2        :        :                   :         : 2         :                
+nCE                          : J3        :        :                   :         : 1         :                
+TDO                          : J4        : output :                   :         : 1         :                
+TMS                          : J5        : input  :                   :         : 1         :                
+VCCINT                       : J6        : power  :                   : 1.2V    :           :                
+GND                          : J7        : gnd    :                   :         :           :                
+GND                          : J8        : gnd    :                   :         :           :                
+GND                          : J9        : gnd    :                   :         :           :                
+GND                          : J10       : gnd    :                   :         :           :                
+GND                          : J11       : gnd    :                   :         :           :                
+VCCINT                       : J12       : power  :                   : 1.2V    :           :                
+GPIO_1_D[32]                 : J13       : output : 3.3-V LVTTL       :         : 5         : Y              
+GPIO_1_D[33]                 : J14       : output : 3.3-V LVTTL       :         : 5         : Y              
+reset_btn                    : J15       : input  : 3.3-V LVTTL       :         : 5         : Y              
+GPIO_1_D[30]                 : J16       : output : 3.3-V LVTTL       :         : 5         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : K1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K2        :        :                   :         : 2         :                
+VCCIO2                       : K3        : power  :                   : 3.3V    : 2         :                
+GND                          : K4        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K5        :        :                   :         : 2         :                
+GND                          : K6        : gnd    :                   :         :           :                
+VCCINT                       : K7        : power  :                   : 1.2V    :           :                
+GND                          : K8        : gnd    :                   :         :           :                
+VCCINT                       : K9        : power  :                   : 1.2V    :           :                
+VCCINT                       : K10       : power  :                   : 1.2V    :           :                
+VCCINT                       : K11       : power  :                   : 1.2V    :           :                
+GND                          : K12       : gnd    :                   :         :           :                
+GND                          : K13       : gnd    :                   :         :           :                
+VCCIO5                       : K14       : power  :                   : 3.3V    : 5         :                
+GPIO_1_D[31]                 : K15       : output : 3.3-V LVTTL       :         : 5         : Y              
+GPIO_1_D[17]                 : K16       : output : 3.3-V LVTTL       :         : 5         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : L1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L2        :        :                   :         : 2         :                
+LED[7]                       : L3        : output : 3.3-V LVTTL       :         : 2         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : L4        :        :                   :         : 2         :                
+VCCA1                        : L5        : power  :                   : 2.5V    :           :                
+VCCINT                       : L6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L8        :        :                   :         : 3         :                
+GND                          : L9        : gnd    :                   :         :           :                
+GND                          : L10       : gnd    :                   :         :           :                
+GND                          : L11       : gnd    :                   :         :           :                
+VCCA4                        : L12       : power  :                   : 2.5V    :           :                
+GPIO_1_D[29]                 : L13       : output : 3.3-V LVTTL       :         : 5         : Y              
+GPIO_1_D[26]                 : L14       : output : 3.3-V LVTTL       :         : 5         : Y              
+GPIO_1_D[19]                 : L15       : output : 3.3-V LVTTL       :         : 5         : Y              
+GPIO_1_D[16]                 : L16       : output : 3.3-V LVTTL       :         : 5         : Y              
+GND+                         : M1        :        :                   :         : 2         :                
+GND+                         : M2        :        :                   :         : 2         :                
+VCCIO2                       : M3        : power  :                   : 3.3V    : 2         :                
+GND                          : M4        : gnd    :                   :         :           :                
+GNDA1                        : M5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M8        :        :                   :         : 3         :                
+VCCINT                       : M9        : power  :                   : 1.2V    :           :                
+GPIO_1_D[28]                 : M10       : output : 3.3-V LVTTL       :         : 4         : Y              
+VCCINT                       : M11       : power  :                   : 1.2V    :           :                
+GNDA4                        : M12       : gnd    :                   :         :           :                
+GND                          : M13       : gnd    :                   :         :           :                
+VCCIO5                       : M14       : power  :                   : 3.3V    : 5         :                
+GND+                         : M15       :        :                   :         : 5         :                
+GND+                         : M16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N3        :        :                   :         : 3         :                
+VCCD_PLL1                    : N4        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N5        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 3         :                
+GND                          : N7        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N8        :        :                   :         : 3         :                
+GPIO_1_D[14]                 : N9        : output : 3.3-V LVTTL       :         : 4         : Y              
+GND                          : N10       : gnd    :                   :         :           :                
+GPIO_1_D[15]                 : N11       : output : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1_D[12]                 : N12       : output : 3.3-V LVTTL       :         : 4         : Y              
+VCCD_PLL4                    : N13       : power  :                   : 1.2V    :           :                
+GPIO_1_D[27]                 : N14       : output : 3.3-V LVTTL       :         : 5         : Y              
+GPIO_1_D[24]                 : N15       : output : 3.3-V LVTTL       :         : 5         : Y              
+GPIO_1_D[23]                 : N16       : output : 3.3-V LVTTL       :         : 5         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : P1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P3        :        :                   :         : 3         :                
+VCCIO3                       : P4        : power  :                   : 1.2V    : 3         :                
+GND                          : P5        : gnd    :                   :         :           :                
+VREFB3N0                     : P6        :        :                   : 0.6V    : 3         :                
+VCCIO3                       : P7        : power  :                   : 1.2V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P8        :        :                   :         : 3         :                
+GPIO_1_D[13]                 : P9        : output : 3.3-V LVTTL       :         : 4         : Y              
+VCCIO4                       : P10       : power  :                   : 3.3V    : 4         :                
+GPIO_1_D[10]                 : P11       : output : 3.3-V LVTTL       :         : 4         : Y              
+GND                          : P12       : gnd    :                   :         :           :                
+VCCIO4                       : P13       : power  :                   : 3.3V    : 4         :                
+GPIO_1_D[25]                 : P14       : output : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1_D[20]                 : P15       : output : 3.3-V LVTTL       :         : 5         : Y              
+GPIO_1_D[21]                 : P16       : output : 3.3-V LVTTL       :         : 5         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : R1        :        :                   :         : 2         :                
+GND                          : R2        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R3        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R4        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R5        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R7        :        :                   :         : 3         :                
+CLOCK_50                     : R8        : input  : 1.2-V HSTL Class II :         : 3         : Y              
+GND+                         : R9        :        :                   :         : 4         :                
+GPIO_1_D[11]                 : R10       : output : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1_D[9]                  : R11       : output : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1_D[6]                  : R12       : output : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1_D[4]                  : R13       : output : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1_D[22]                 : R14       : output : 3.3-V LVTTL       :         : 4         : Y              
+GND                          : R15       : gnd    :                   :         :           :                
+GPIO_1_D[18]                 : R16       : output : 3.3-V LVTTL       :         : 5         : Y              
+VCCIO3                       : T1        : power  :                   : 1.2V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T2        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T3        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T4        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T5        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T7        :        :                   :         : 3         :                
+GND+                         : T8        :        :                   :         : 3         :                
+GND+                         : T9        :        :                   :         : 4         :                
+GPIO_1_D[8]                  : T10       : output : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : T11       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T13       :        :                   :         : 4         :                
+GPIO_1_D[2]                  : T14       : output : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : T15       :        :                   :         : 4         :                
+VCCIO4                       : T16       : power  :                   : 3.3V    : 4         :                
diff --git a/rtl/DE0-NANO/output_files/xoro.sld b/rtl/DE0-NANO/output_files/xoro.sld
new file mode 100644
index 0000000..f7d3ed7
--- /dev/null
+++ b/rtl/DE0-NANO/output_files/xoro.sld
@@ -0,0 +1 @@
+<sld_project_info/>
diff --git a/rtl/DE0-NANO/output_files/xoro.sof b/rtl/DE0-NANO/output_files/xoro.sof
new file mode 100644
index 0000000..4069299
Binary files /dev/null and b/rtl/DE0-NANO/output_files/xoro.sof differ