forked from FPGALover/RISCV_picorv32_fpga
71 lines
1.4 KiB
Verilog
71 lines
1.4 KiB
Verilog
//
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// Test bench for xoro_top.v
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//
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`include "timescale.vh"
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`define SIMULATION
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module xoro_top_tb;
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// Define all inputs
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reg clk;
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reg resn;
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// Define all outputs
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wire [3:0] leds;
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wire [3:0] rnd;
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wire serialOut;
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// Instantiate DUT.
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xoro_top xoro_top (
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.CLOCK_50(clk),
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.reset_btn(resn),
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.LED(leds),
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.RND_OUT(rnd),
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.UART_TX(serialOut)
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);
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// Initialize all inputs
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initial
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begin
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clk = 0;
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resn = 0;
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end
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// Specify file for waveform dump
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initial begin
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$dumpfile ("xoro_top_tb.vcd");
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$dumpvars;
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end
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// Monitor all signals
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initial begin
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$display("\tclk,\tresn,\tleds,\trnd,\tserialOut,\txoro_top.mem_addr, \txoro_top.mem_rdata,\txoro_top.resetn");
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$monitor("\t%b,\t%b,\t%b,\t%b,\t%b,\t\t%h,\t\t%h,\t\t%b", clk, resn, leds, rnd, serialOut, xoro_top.mem_addr, xoro_top.mem_rdata, xoro_top.resetn);
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end
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// Generate a clock tick
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always
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#5clk = !clk;
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// Generate a reset on start up
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event reset_trigger;
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event reset_done_trigger;
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initial begin
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forever begin
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@ (reset_trigger);
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@ (negedge clk);
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resn = 0;
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@ (negedge clk);
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resn = 1;
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-> reset_done_trigger;
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end
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end
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/*
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initial begin
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-> reset_trigger;
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end
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*/
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endmodule
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