forked from FPGALover/RISCV_picorv32_fpga
39 lines
1.5 KiB
Markdown
39 lines
1.5 KiB
Markdown
# RISCV(picorv32) on FPGA
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## Building RISC-V from scratch, using Linux or WSL
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```html
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sudo apt-get update
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sudo apt-get install autoconf automake autotools-dev curl python3 python3-pip libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev ninja-build git cmake libglib2.0-dev
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git clone https://github.com/riscv/riscv-gnu-toolchain
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cd riscv-gnu-toolchain/
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mkdir build/
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cd build
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sudo mkdir /opt/riscv32im
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sudo chown $USER /opt/riscv32im
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./configure --with-arch=rv32im --prefix=/opt/riscv32im
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make -j$(nproc)
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```
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## For other architectures or variations of RISC-V
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| Command | ISA |
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|:---------------------------------------- |:-------- |
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|`./configure --with-arch=rv32i --prefix=/opt/riscv32i/ `| `RV32I `|
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|`./configure --with-arch=rv32ic --prefix=/opt/riscv32ic/ `| `RV32IC `|
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|`./configure --with-arch=rv32im --prefix=/opt/riscv32im/` | `RV32IM `|
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|`./configure --with-arch=rv32imc --prefix=/opt/riscv32imc/`| `RV32IMC `|
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## Other Linux and Windows precompiled Toolchains
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- https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/ for mingw64
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- https://gnutoolchains.com/risc-v/
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# Build the firmware
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```html
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git clone https://gitea.squirrelnut.synology.me:5001/FPGALover/RISCV_picorv32_fpga
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cd RISCV_picorv32_fpga/sw
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make clean
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make firmware/firmware.fpga
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cp firmware/Memory.v_toplevel_memory_1_symbol* ../rtl/DE0-NANO
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```
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*Now you can compile or synthesize the FPGA harware using Quartus or any other Design tool*
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